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eth: Add some notes to HTG-9200 constraints files

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-08-10 21:02:14 -07:00
parent ad7bf4c9ce
commit 4b779732ec
2 changed files with 43 additions and 4 deletions
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18
src/eth/example/HTG9200/fpga/syn/i2c.xdc
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@@ -11,6 +11,24 @@
# part: xcvu13p-fhgb2104-2-e
# I2C
# U12 PCA9548 0x70
# S0 4/5: J8 QSFP28 5 0x50
# S1 6/7: J7 QSFP28 4 0x50
# S2 8/9: J5 QSFP28 3 0x50
# S3 10/11: J4 QSFP28 2 0x50
# S4 13/14: J1 QSFP28 1 0x50
# S5 15/16: J14 QSFP28 6 0x50
# S6 17/18: J10 QSFP28 7 0x50
# S7 19/20: J11 QSFP28 8 0x50
# U30 PCA9548 0x71
# S0 4/5: U29 ICS8N4Q001L OSC GTH 0x6E
# S1 6/7: J9 FMC
# S2 8/9: U48 SI5341A-A-GM CLK GTY2 0x77
# S3 10/11: U5 ICS8N4Q001L OSC DDR4 0x6E
# S4 13/14: U47 ICS8N4Q001L OSC GTY2 0x6E
# S5 15/16: J15 QSFP28 9 0x50
# S6 17/18: U27 5P49V6901AdddNLGI CLK GTH 0xD4
# S7 19/20: U24 ICS8N4Q001L OSC REFCLK 0x6E
set_property -dict {LOC BB21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_main_scl]
set_property -dict {LOC BC21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_main_sda]
set_property -dict {LOC BF20 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_main_rst_n]

29
src/eth/example/HTG9200/fpga/syn/pll.xdc
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@@ -10,7 +10,22 @@
# part: xcvu9p-flgb2104-2-e
# part: xcvu13p-fhgb2104-2-e
# PLL control
# PLL U48 Si5341A-D-GM
# A1/A0: 11 (I2C addr 0x77)
# IN0: X29/X30
# IN1: U47
# IN2: NC
# FB: X31/X32
# OUT0: GTY 129
# OUT1: GTY 133
# OUT2: FF / X33/X34
# OUT3: GTY 132
# OUT4: GTY 131
# OUT5: GTY 130
# OUT6: GTY 126
# OUT7: GTY 125
# OUT8: GTY 127
# OUT9: GTY 128
set_property -dict {LOC L24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_fdec}]
set_property -dict {LOC K25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_finc}]
set_property -dict {LOC K23 IOSTANDARD LVCMOS18} [get_ports {clk_gty2_intr_n}]
@@ -19,10 +34,16 @@ set_property -dict {LOC L23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {
set_property -dict {LOC L22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_sync_n}]
set_property -dict {LOC K22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_rst_n}]
#set_property -dict {LOC BE20 IOSTANDARD LVCMOS18} [get_ports {clk_gth_sd_oe}]
#set_property -dict {LOC BD20 IOSTANDARD LVCMOS18} [get_ports {clk_gth_out0_sel_i2cb}]
set_false_path -to [get_ports {clk_gty2_fdec clk_gty2_finc clk_gty2_oe_n clk_gty2_sync_n clk_gty2_rst_n}]
set_output_delay 0 [get_ports {clk_gty2_fdec clk_gty2_finc clk_gty2_oe_n clk_gty2_sync_n clk_gty2_rst_n}]
set_false_path -from [get_ports {clk_gty2_intr_n clk_gty2_lol_n}]
set_input_delay 0 [get_ports {clk_gty2_intr_n clk_gty2_lol_n}]
# PLL U27 5P49V6901AdddNLGI
# IN: U29
# OUT1: FMC REFCLK C2M
# OUT2: FMC CLK2
# OUT3: FMC CLK1
# OUT4: FMC CLK2
#set_property -dict {LOC BE20 IOSTANDARD LVCMOS18} [get_ports {clk_gth_sd_oe}]
#set_property -dict {LOC BD20 IOSTANDARD LVCMOS18} [get_ports {clk_gth_out0_sel_i2cb}]