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example/ADM_PCIE_9V3: Testbench cleanup

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-02-24 21:42:23 -08:00
parent ffe667b047
commit 4cdc4be47e
1 changed files with 6 additions and 5 deletions
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11
example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py
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@@ -46,12 +46,13 @@ class TB:
self.qsfp_sources = []
self.qsfp_sinks = []
for ch in list(dut.qsfp_0_mac_inst.ch)+list(dut.qsfp_1_mac_inst.ch):
cocotb.start_soon(Clock(ch.ch_inst.tx_clk, 2.56, units="ns").start())
cocotb.start_soon(Clock(ch.ch_inst.rx_clk, 2.56, units="ns").start())
for inst in [dut.qsfp_0_mac_inst, dut.qsfp_1_mac_inst]:
for ch in inst.ch:
cocotb.start_soon(Clock(ch.ch_inst.tx_clk, 2.56, units="ns").start())
cocotb.start_soon(Clock(ch.ch_inst.rx_clk, 2.56, units="ns").start())
self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True))
self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True))
dut.user_sw.setimmediatevalue(0)