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example/Nexus_K3P_Q: Add example design for Cisco Nexus K3P-Q
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
@@ -95,6 +95,7 @@ Example designs are provided for several different FPGA boards, showcasing many
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* Alpha Data ADM-PCIE-9V3 (Xilinx Virtex UltraScale+ XCVU3P)
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* Cisco Nexus K35-S/ExaNIC X10 (Xilinx Kintex UltraScale XCKU035)
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* Cisco Nexus K3P-S/ExaNIC X25 (Xilinx Kintex UltraScale+ XCKU3P)
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* Cisco Nexus K3P-Q/ExaNIC X100 (Xilinx Kintex UltraScale+ XCKU3P)
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* Digilent Arty A7 (Xilinx Artix 7 XC7A35T)
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* HiTech Global HTG-940 (Xilinx Virtex UltraScale+ XCVU9P/XCVU13P)
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* Xilinx KC705 (Xilinx Kintex 7 XC7K325T)
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32
example/Nexus_K3P_Q/fpga/README.md
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32
example/Nexus_K3P_Q/fpga/README.md
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@@ -0,0 +1,32 @@
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# Taxi Example Design for Nexus K3P-Q (ExaNIC X100)
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## Introduction
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This example design targets the Cisco Nexus K3P-Q (ExaNIC X100) FPGA board.
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The design places looped-back MACs on the QSFP28 cages.
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* QSFP28 cages
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* Looped-back 10GBASE-R or 25GBASE-R MAC via GTH or GTY transceiver
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## Board details
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* FPGA: xcku3p-ffvb676-2-e
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* 25GBASE-R PHY: Soft PCS with GTH or GTY transceiver
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## Licensing
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* Toolchain
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* Vivado Standard (enterprise license not required)
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* IP
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* No licensed vendor IP or 3rd party IP
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## How to build
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Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
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## How to test
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Run `make program` to program the board with Vivado.
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To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems.
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153
example/Nexus_K3P_Q/fpga/common/vivado.mk
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153
example/Nexus_K3P_Q/fpga/common/vivado.mk
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@@ -0,0 +1,153 @@
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# SPDX-License-Identifier: MIT
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###################################################################
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#
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# Xilinx Vivado FPGA Makefile
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#
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# Copyright (c) 2016-2025 Alex Forencich
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#
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###################################################################
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#
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# Parameters:
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# FPGA_TOP - Top module name
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# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
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# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
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# SYN_FILES - list of source files
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# INC_FILES - list of include files
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# XDC_FILES - list of timing constraint files
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# XCI_FILES - list of IP XCI files
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# IP_TCL_FILES - list of IP TCL files (sourced during project creation)
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# CONFIG_TCL_FILES - list of config TCL files (sourced before each build)
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#
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# Note: both SYN_FILES and INC_FILES support file list files. File list
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# files are files with a .f extension that contain a list of additional
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# files to include, one path relative to the .f file location per line.
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# The .f files are processed recursively, and then the complete file list
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# is de-duplicated, with later files in the list taking precedence.
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#
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# Example:
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#
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# FPGA_TOP = fpga
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# FPGA_FAMILY = VirtexUltrascale
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# FPGA_DEVICE = xcvu095-ffva2104-2-e
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# SYN_FILES = rtl/fpga.v
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# XDC_FILES = fpga.xdc
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# XCI_FILES = ip/pcspma.xci
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# include ../common/vivado.mk
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#
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###################################################################
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# phony targets
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.PHONY: fpga vivado tmpclean clean distclean
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# prevent make from deleting intermediate files and reports
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.PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm
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.SECONDARY:
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CONFIG ?= config.mk
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-include $(CONFIG)
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FPGA_TOP ?= fpga
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PROJECT ?= $(FPGA_TOP)
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XDC_FILES ?= $(PROJECT).xdc
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# handle file list files
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process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
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process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
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uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
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SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES)))
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INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES)))
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###################################################################
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# Main Targets
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#
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# all: build everything (fpga)
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# fpga: build FPGA config
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# vivado: open project in Vivado
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# tmpclean: remove intermediate files
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# clean: remove output files and project files
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# distclean: remove archived output files
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###################################################################
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all: fpga
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fpga: $(PROJECT).bit
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vivado: $(PROJECT).xpr
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vivado $(PROJECT).xpr
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tmpclean::
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-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
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-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
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clean:: tmpclean
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-rm -rf *.bit *.bin *.ltx *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
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-rm -rf *_utilization.rpt *_utilization_hierarchical.rpt
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distclean:: clean
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-rm -rf rev
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###################################################################
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# Target implementations
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###################################################################
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# Vivado project file
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# create fresh project if Makefile or IP files have changed
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create_project.tcl: Makefile $(XCI_FILES) $(IP_TCL_FILES)
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rm -rf defines.v
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touch defines.v
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for x in $(DEFS); do echo '`define' $$x >> defines.v; done
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echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@
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echo "add_files -fileset sources_1 defines.v $(SYN_FILES)" >> $@
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echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@
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echo "add_files -fileset constrs_1 $(XDC_FILES)" >> $@
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for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done
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for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done
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for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
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# source config TCL scripts if any source file has changed
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update_config.tcl: $(CONFIG_TCL_FILES) $(SYN_FILES) $(INC_FILES) $(XDC_FILES)
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echo "open_project -quiet $(PROJECT).xpr" > $@
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for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
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$(PROJECT).xpr: create_project.tcl update_config.tcl
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vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
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# synthesis run
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$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES) $(INC_FILES) $(XDC_FILES) | $(PROJECT).xpr
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echo "open_project $(PROJECT).xpr" > run_synth.tcl
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echo "reset_run synth_1" >> run_synth.tcl
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echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
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echo "wait_on_run synth_1" >> run_synth.tcl
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vivado -nojournal -nolog -mode batch -source run_synth.tcl
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# implementation run
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$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp
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echo "open_project $(PROJECT).xpr" > run_impl.tcl
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echo "reset_run impl_1" >> run_impl.tcl
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echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
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echo "wait_on_run impl_1" >> run_impl.tcl
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echo "open_run impl_1" >> run_impl.tcl
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echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl
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echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl
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vivado -nojournal -nolog -mode batch -source run_impl.tcl
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# output files (including potentially bit, bin, ltx, and xsa)
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$(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp
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echo "open_project $(PROJECT).xpr" > generate_bit.tcl
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echo "open_run impl_1" >> generate_bit.tcl
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echo "write_bitstream -force -bin_file $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl
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echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl
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echo "write_hw_platform -fixed -force -include_bit $(PROJECT).xsa" >> generate_bit.tcl
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vivado -nojournal -nolog -mode batch -source generate_bit.tcl
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ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit .
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ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bin .
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if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi
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mkdir -p rev
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COUNT=100; \
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while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \
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do COUNT=$$((COUNT+1)); done; \
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cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \
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cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \
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if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \
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if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi
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336
example/Nexus_K3P_Q/fpga/fpga.xdc
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336
example/Nexus_K3P_Q/fpga/fpga.xdc
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@@ -0,0 +1,336 @@
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# SPDX-License-Identifier: MIT
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#
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# Copyright (c) 2025 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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#
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# XDC constraints for the Cisco Nexus K3P-Q / ExaNIC X100
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# part: xcku3p-ffvb676-2-e
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# General configuration
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set_property CFGBVS GND [current_design]
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set_property CONFIG_VOLTAGE 1.8 [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
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set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
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set_property BITSTREAM.CONFIG.CONFIGRATE 72.9 [current_design]
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set_property CONFIG_MODE SPIx4 [current_design]
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set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
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set_property BITSTREAM.CONFIG.SPI_FALL_EDGE Yes [current_design]
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set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
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# 10 MHz TXCO
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#set_property -dict {LOC E13 IOSTANDARD LVCMOS33} [get_ports clk_10mhz]
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#create_clock -period 100.000 -name clk_10mhz [get_ports clk_10mhz]
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# E13 cannot directly drive MMCM, so need to set CLOCK_DEDICATED_ROUTE to satisfy DRC
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#set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets clk_10mhz_bufg]
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# LEDs
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set_property -dict {LOC AB15 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {qsfp_led_green[0]}]
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set_property -dict {LOC AC14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {qsfp_led_orange[0]}]
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set_property -dict {LOC AA15 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {qsfp_led_green[1]}]
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set_property -dict {LOC AB14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {qsfp_led_orange[1]}]
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set_property -dict {LOC C12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sma_led_green}]
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set_property -dict {LOC C13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sma_led_red}]
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set_false_path -to [get_ports {qsfp_led_green[*] qsfp_led_orange[*] sma_led_green sma_led_red}]
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set_output_delay 0 [get_ports {qsfp_led_green[*] qsfp_led_orange[*] sma_led_green sma_led_red}]
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# GPIO
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#set_property -dict {LOC IOSTANDARD LVCMOS18} [get_ports gpio[0]]
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#set_property -dict {LOC IOSTANDARD LVCMOS18} [get_ports gpio[1]]
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#set_property -dict {LOC IOSTANDARD LVCMOS18} [get_ports gpio[2]]
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#set_property -dict {LOC IOSTANDARD LVCMOS18} [get_ports gpio[3]]
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#set_property -dict {LOC IOSTANDARD LVCMOS18} [get_ports gpio[4]]
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# SMA
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#set_property -dict {LOC AD15 IOSTANDARD LVCMOS33} [get_ports {sma_in}]
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#set_property -dict {LOC AF14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {sma_out}]
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#set_property -dict {LOC AD14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sma_out_en}]
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#set_property -dict {LOC AB16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sma_term_en}]
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#set_false_path -to [get_ports {sma_out sma_out_en sma_term_en}]
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#set_output_delay 0 [get_ports {sma_out sma_out_en sma_term_en}]
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#set_false_path -from [get_ports {sma_in}]
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#set_input_delay 0 [get_ports {sma_in}]
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# Config
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#set_property -dict {LOC C14 IOSTANDARD LVCMOS33} [get_ports ddr_npres]
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# QSFP28 Interfaces
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set_property -dict {LOC M2 } [get_ports {qsfp_0_rx_p[0]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2
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set_property -dict {LOC M1 } [get_ports {qsfp_0_rx_n[0]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2
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set_property -dict {LOC N5 } [get_ports {qsfp_0_tx_p[0]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2
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set_property -dict {LOC N4 } [get_ports {qsfp_0_tx_n[0]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2
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set_property -dict {LOC K2 } [get_ports {qsfp_0_rx_p[1]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2
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set_property -dict {LOC K1 } [get_ports {qsfp_0_rx_n[1]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2
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set_property -dict {LOC L5 } [get_ports {qsfp_0_tx_p[1]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2
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set_property -dict {LOC L4 } [get_ports {qsfp_0_tx_n[1]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2
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set_property -dict {LOC F2 } [get_ports {qsfp_0_rx_p[2]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2
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set_property -dict {LOC F1 } [get_ports {qsfp_0_rx_n[2]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2
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set_property -dict {LOC G5 } [get_ports {qsfp_0_tx_p[2]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2
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set_property -dict {LOC G4 } [get_ports {qsfp_0_tx_n[2]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2
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set_property -dict {LOC H2 } [get_ports {qsfp_0_rx_p[3]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2
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set_property -dict {LOC H1 } [get_ports {qsfp_0_rx_n[3]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2
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set_property -dict {LOC J5 } [get_ports {qsfp_0_tx_p[3]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2
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set_property -dict {LOC J4 } [get_ports {qsfp_0_tx_n[3]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2
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set_property -dict {LOC W16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp_0_modsell]
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set_property -dict {LOC Y15 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp_0_resetl]
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set_property -dict {LOC W14 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp_0_modprsl]
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set_property -dict {LOC W15 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp_0_intl]
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set_property -dict {LOC Y13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp_0_lpmode]
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#set_property -dict {LOC AC13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports qsfp_0_i2c_sda]
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#set_property -dict {LOC Y16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports qsfp_0_i2c_scl]
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set_false_path -to [get_ports {qsfp_0_modsell qsfp_0_resetl qsfp_0_lpmode}]
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set_output_delay 0 [get_ports {qsfp_0_modsell qsfp_0_resetl qsfp_0_lpmode}]
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set_false_path -from [get_ports {qsfp_0_modprsl qsfp_0_intl}]
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set_input_delay 0 [get_ports {qsfp_0_modprsl qsfp_0_intl}]
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#set_false_path -to [get_ports {qsfp_0_i2c_sda qsfp_0_i2c_scl}]
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#set_output_delay 0 [get_ports {qsfp_0_i2c_sda qsfp_0_i2c_scl}]
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#set_false_path -from [get_ports {qsfp_0_i2c_sda qsfp_0_i2c_scl}]
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#set_input_delay 0 [get_ports {qsfp_0_i2c_sda qsfp_0_i2c_scl}]
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set_property -dict {LOC D2 } [get_ports {qsfp_1_rx_p[0]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
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set_property -dict {LOC D1 } [get_ports {qsfp_1_rx_n[0]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC F7 } [get_ports {qsfp_1_tx_p[0]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC F6 } [get_ports {qsfp_1_tx_n[0]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC C4 } [get_ports {qsfp_1_rx_p[1]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC C3 } [get_ports {qsfp_1_rx_n[1]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC E5 } [get_ports {qsfp_1_tx_p[1]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC E4 } [get_ports {qsfp_1_tx_n[1]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC A4 } [get_ports {qsfp_1_rx_p[2]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC A3 } [get_ports {qsfp_1_rx_n[2]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC B7 } [get_ports {qsfp_1_tx_p[2]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC B6 } [get_ports {qsfp_1_tx_n[2]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC B2 } [get_ports {qsfp_1_rx_p[3]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC B1 } [get_ports {qsfp_1_rx_n[3]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC D7 } [get_ports {qsfp_1_tx_p[3]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC D6 } [get_ports {qsfp_1_tx_n[3]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
|
||||
set_property -dict {LOC AA14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp_1_modsell]
|
||||
set_property -dict {LOC AE13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp_1_resetl]
|
||||
set_property -dict {LOC A13 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp_1_modprsl]
|
||||
set_property -dict {LOC A14 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp_1_intl]
|
||||
set_property -dict {LOC B14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp_1_lpmode]
|
||||
#set_property -dict {LOC AD13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports qsfp_1_i2c_sda]
|
||||
#set_property -dict {LOC AF13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports qsfp_1_i2c_scl]
|
||||
|
||||
# 161.1328125 MHz MGT reference clock
|
||||
set_property -dict {LOC K7 } [get_ports qsfp_mgt_refclk_p] ;# MGTREFCLK0P_227 from X2
|
||||
set_property -dict {LOC K6 } [get_ports qsfp_mgt_refclk_n] ;# MGTREFCLK0N_227 from X2
|
||||
create_clock -period 6.206 -name qsfp_mgt_refclk [get_ports qsfp_mgt_refclk_p]
|
||||
|
||||
set_false_path -to [get_ports {qsfp_1_modsell qsfp_1_resetl qsfp_1_lpmode}]
|
||||
set_output_delay 0 [get_ports {qsfp_1_modsell qsfp_1_resetl qsfp_1_lpmode}]
|
||||
set_false_path -from [get_ports {qsfp_1_modprsl qsfp_1_intl}]
|
||||
set_input_delay 0 [get_ports {qsfp_1_modprsl qsfp_1_intl}]
|
||||
|
||||
#set_false_path -to [get_ports {qsfp_1_i2c_sda qsfp_1_i2c_scl}]
|
||||
#set_output_delay 0 [get_ports {qsfp_1_i2c_sda qsfp_1_i2c_scl}]
|
||||
#set_false_path -from [get_ports {qsfp_1_i2c_sda qsfp_1_i2c_scl}]
|
||||
#set_input_delay 0 [get_ports {qsfp_1_i2c_sda qsfp_1_i2c_scl}]
|
||||
|
||||
# I2C interface
|
||||
#set_property -dict {LOC W12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports eeprom_i2c_scl]
|
||||
#set_property -dict {LOC W13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports eeprom_i2c_sda]
|
||||
|
||||
#set_false_path -to [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
|
||||
#set_output_delay 0 [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
|
||||
#set_false_path -from [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
|
||||
#set_input_delay 0 [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
|
||||
|
||||
# PCIe Interface
|
||||
#set_property -dict {LOC P2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC P1 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC R5 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC R4 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC T2 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC T1 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC U5 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC U4 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC V2 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC V1 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC W5 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC W4 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC Y2 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC Y1 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC AA5 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC AA4 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC AB2 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AB1 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AC5 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AC4 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AD2 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AD1 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AD7 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AD6 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AE4 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AE3 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AE9 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AE8 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC V7 } [get_ports pcie_refclk_p] ;# MGTREFCLK0P_225
|
||||
#set_property -dict {LOC V6 } [get_ports pcie_refclk_n] ;# MGTREFCLK0N_225
|
||||
#set_property -dict {LOC T19 IOSTANDARD LVCMOS12 PULLUP true} [get_ports pcie_reset_n]
|
||||
|
||||
#set_false_path -from [get_ports {pcie_reset_n}]
|
||||
#set_input_delay 0 [get_ports {pcie_reset_n}]
|
||||
|
||||
# 100 MHz MGT reference clock
|
||||
#create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_refclk_p]
|
||||
|
||||
# DDR4
|
||||
# 9x MT40A1G8SA-075
|
||||
#set_property -dict {LOC W24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[0]}]
|
||||
#set_property -dict {LOC U24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[1]}]
|
||||
#set_property -dict {LOC AA24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[2]}]
|
||||
#set_property -dict {LOC T24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[3]}]
|
||||
#set_property -dict {LOC Y22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[4]}]
|
||||
#set_property -dict {LOC V23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[5]}]
|
||||
#set_property -dict {LOC Y25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[6]}]
|
||||
#set_property -dict {LOC V24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[7]}]
|
||||
#set_property -dict {LOC W23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[8]}]
|
||||
#set_property -dict {LOC Y26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[9]}]
|
||||
#set_property -dict {LOC V21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[10]}]
|
||||
#set_property -dict {LOC W25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[11]}]
|
||||
#set_property -dict {LOC AA23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[12]}]
|
||||
#set_property -dict {LOC W26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[13]}]
|
||||
#set_property -dict {LOC U21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[14]}]
|
||||
#set_property -dict {LOC T22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[15]}]
|
||||
#set_property -dict {LOC T20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[16]}]
|
||||
#set_property -dict {LOC V22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_ba[0]}]
|
||||
#set_property -dict {LOC T23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_ba[1]}]
|
||||
#set_property -dict {LOC Y23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_bg[0]}]
|
||||
#set_property -dict {LOC P24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_bg[1]}]
|
||||
#set_property -dict {LOC U19 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_ck_t}]
|
||||
#set_property -dict {LOC V19 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_ck_c}]
|
||||
#set_property -dict {LOC W19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_cke}]
|
||||
#set_property -dict {LOC N24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_cs_n}]
|
||||
#set_property -dict {LOC W20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_act_n}]
|
||||
#set_property -dict {LOC U20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_odt}]
|
||||
#set_property -dict {LOC R25 IOSTANDARD LVCMOS12 } [get_ports {ddr4_reset_n}]
|
||||
|
||||
#set_property -dict {LOC L20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[0]}]
|
||||
#set_property -dict {LOC M20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[1]}]
|
||||
#set_property -dict {LOC J21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[2]}]
|
||||
#set_property -dict {LOC M21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[3]}]
|
||||
#set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[4]}]
|
||||
#set_property -dict {LOC J19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[5]}]
|
||||
#set_property -dict {LOC K20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[6]}]
|
||||
#set_property -dict {LOC J20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[7]}]
|
||||
#set_property -dict {LOC K23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[8]}]
|
||||
#set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[9]}]
|
||||
#set_property -dict {LOC M25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[10]}]
|
||||
#set_property -dict {LOC K26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[11]}]
|
||||
#set_property -dict {LOC J23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[12]}]
|
||||
#set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[13]}]
|
||||
#set_property -dict {LOC M26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[14]}]
|
||||
#set_property -dict {LOC K25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[15]}]
|
||||
#set_property -dict {LOC H23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[16]}]
|
||||
#set_property -dict {LOC G26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[17]}]
|
||||
#set_property -dict {LOC J26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[18]}]
|
||||
#set_property -dict {LOC H24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[19]}]
|
||||
#set_property -dict {LOC H21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[20]}]
|
||||
#set_property -dict {LOC H22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[21]}]
|
||||
#set_property -dict {LOC J25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[22]}]
|
||||
#set_property -dict {LOC H26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[23]}]
|
||||
#set_property -dict {LOC E23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[24]}]
|
||||
#set_property -dict {LOC D24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[25]}]
|
||||
#set_property -dict {LOC D25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[26]}]
|
||||
#set_property -dict {LOC B25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[27]}]
|
||||
#set_property -dict {LOC D26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[28]}]
|
||||
#set_property -dict {LOC F23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[29]}]
|
||||
#set_property -dict {LOC C26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[30]}]
|
||||
#set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[31]}]
|
||||
#set_property -dict {LOC AF25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[32]}]
|
||||
#set_property -dict {LOC AC24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[33]}]
|
||||
#set_property -dict {LOC AD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[34]}]
|
||||
#set_property -dict {LOC AD24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[35]}]
|
||||
#set_property -dict {LOC AF24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[36]}]
|
||||
#set_property -dict {LOC AB25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[37]}]
|
||||
#set_property -dict {LOC AB24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[38]}]
|
||||
#set_property -dict {LOC AB26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[39]}]
|
||||
#set_property -dict {LOC AD21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[40]}]
|
||||
#set_property -dict {LOC AD23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[41]}]
|
||||
#set_property -dict {LOC AC21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[42]}]
|
||||
#set_property -dict {LOC AC23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[43]}]
|
||||
#set_property -dict {LOC AE21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[44]}]
|
||||
#set_property -dict {LOC AB21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[45]}]
|
||||
#set_property -dict {LOC AC22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[46]}]
|
||||
#set_property -dict {LOC AE23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[47]}]
|
||||
#set_property -dict {LOC AD16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[48]}]
|
||||
#set_property -dict {LOC AD19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[49]}]
|
||||
#set_property -dict {LOC AF17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[50]}]
|
||||
#set_property -dict {LOC AF19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[51]}]
|
||||
#set_property -dict {LOC AE16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[52]}]
|
||||
#set_property -dict {LOC AC19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[53]}]
|
||||
#set_property -dict {LOC AE17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[54]}]
|
||||
#set_property -dict {LOC AF18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[55]}]
|
||||
#set_property -dict {LOC AA19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[56]}]
|
||||
#set_property -dict {LOC Y17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[57]}]
|
||||
#set_property -dict {LOC AA20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[58]}]
|
||||
#set_property -dict {LOC AA17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[59]}]
|
||||
#set_property -dict {LOC AB19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[60]}]
|
||||
#set_property -dict {LOC Y18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[61]}]
|
||||
#set_property -dict {LOC AB20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[62]}]
|
||||
#set_property -dict {LOC AA18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[63]}]
|
||||
#set_property -dict {LOC H16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[64]}]
|
||||
#set_property -dict {LOC E15 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[65]}]
|
||||
#set_property -dict {LOC C16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[66]}]
|
||||
#set_property -dict {LOC D16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[67]}]
|
||||
#set_property -dict {LOC H17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[68]}]
|
||||
#set_property -dict {LOC G16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[69]}]
|
||||
#set_property -dict {LOC G17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[70]}]
|
||||
#set_property -dict {LOC D15 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[71]}]
|
||||
#set_property -dict {LOC M19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[0]}]
|
||||
#set_property -dict {LOC L19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[0]}]
|
||||
#set_property -dict {LOC L24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[1]}]
|
||||
#set_property -dict {LOC L25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[1]}]
|
||||
#set_property -dict {LOC F24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[2]}]
|
||||
#set_property -dict {LOC F25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[2]}]
|
||||
#set_property -dict {LOC D23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[3]}]
|
||||
#set_property -dict {LOC C24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[3]}]
|
||||
#set_property -dict {LOC AC26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[4]}]
|
||||
#set_property -dict {LOC AD26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[4]}]
|
||||
#set_property -dict {LOC AA22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[5]}]
|
||||
#set_property -dict {LOC AB22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[5]}]
|
||||
#set_property -dict {LOC AC18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[6]}]
|
||||
#set_property -dict {LOC AD18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[6]}]
|
||||
#set_property -dict {LOC AB17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[7]}]
|
||||
#set_property -dict {LOC AC17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[7]}]
|
||||
#set_property -dict {LOC E16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[8]}]
|
||||
#set_property -dict {LOC E17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[8]}]
|
||||
#set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[0]}]
|
||||
#set_property -dict {LOC L22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[1]}]
|
||||
#set_property -dict {LOC G24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[2]}]
|
||||
#set_property -dict {LOC E25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[3]}]
|
||||
#set_property -dict {LOC AE25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[4]}]
|
||||
#set_property -dict {LOC AE22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[5]}]
|
||||
#set_property -dict {LOC AD20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[6]}]
|
||||
#set_property -dict {LOC Y20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[7]}]
|
||||
#set_property -dict {LOC G15 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[8]}]
|
||||
|
||||
# 161.1328125 MHz DDR4 clock
|
||||
#set_property -dict {LOC T25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports clk_ddr4_p]
|
||||
#set_property -dict {LOC U25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports clk_ddr4_n]
|
||||
#create_clock -period 6.206 -name clk_ddr4 [get_ports clk_ddr4_p]
|
||||
|
||||
# QSPI flash
|
||||
#set_property -dict {LOC H11 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_clk}]
|
||||
#set_property -dict {LOC H9 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {qspi_dq[0]}]
|
||||
#set_property -dict {LOC J9 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {qspi_dq[1]}]
|
||||
#set_property -dict {LOC J10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {qspi_dq[2]}]
|
||||
#set_property -dict {LOC J11 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {qspi_dq[3]}]
|
||||
#set_property -dict {LOC K9 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_0_cs}]
|
||||
#set_property -dict {LOC K10 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_cs}]
|
||||
|
||||
#set_false_path -to [get_ports {qspi_clk qspi_dq[*] qspi_0_cs qspi_1_cs}]
|
||||
#set_output_delay 0 [get_ports {qspi_clk qspi_dq[*] qspi_0_cs qspi_1_cs}]
|
||||
#set_false_path -from [get_ports {qspi_dq[*]}]
|
||||
#set_input_delay 0 [get_ports {qspi_dq[*]}]
|
||||
46
example/Nexus_K3P_Q/fpga/fpga/Makefile
Normal file
46
example/Nexus_K3P_Q/fpga/fpga/Makefile
Normal file
@@ -0,0 +1,46 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcku3p-ffvb676-2-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = kintexuplus
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = ../rtl/fpga.sv
|
||||
SYN_FILES += ../rtl/fpga_core.sv
|
||||
SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f
|
||||
SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f
|
||||
SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv
|
||||
SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv
|
||||
SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga.xdc
|
||||
XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_161.tcl
|
||||
|
||||
# Configuration
|
||||
# CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
46
example/Nexus_K3P_Q/fpga/fpga_10g/Makefile
Normal file
46
example/Nexus_K3P_Q/fpga/fpga_10g/Makefile
Normal file
@@ -0,0 +1,46 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcku3p-ffvb676-2-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = kintexuplus
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = ../rtl/fpga.sv
|
||||
SYN_FILES += ../rtl/fpga_core.sv
|
||||
SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f
|
||||
SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f
|
||||
SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv
|
||||
SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv
|
||||
SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga.xdc
|
||||
XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_161.tcl
|
||||
|
||||
# Configuration
|
||||
# CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
1
example/Nexus_K3P_Q/fpga/lib/taxi
Symbolic link
1
example/Nexus_K3P_Q/fpga/lib/taxi
Symbolic link
@@ -0,0 +1 @@
|
||||
../../../../
|
||||
215
example/Nexus_K3P_Q/fpga/rtl/fpga.sv
Normal file
215
example/Nexus_K3P_Q/fpga/rtl/fpga.sv
Normal file
@@ -0,0 +1,215 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA top-level module
|
||||
*/
|
||||
module fpga #
|
||||
(
|
||||
parameter logic SIM = 1'b0,
|
||||
parameter string VENDOR = "XILINX",
|
||||
parameter string FAMILY = "kintexuplus"
|
||||
)
|
||||
(
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
output wire logic [1:0] qsfp_led_green,
|
||||
output wire logic [1:0] qsfp_led_orange,
|
||||
output wire logic sma_led_green,
|
||||
output wire logic sma_led_red,
|
||||
|
||||
/*
|
||||
* Ethernet: SFP+
|
||||
*/
|
||||
output wire logic [3:0] qsfp_0_tx_p,
|
||||
output wire logic [3:0] qsfp_0_tx_n,
|
||||
input wire logic [3:0] qsfp_0_rx_p,
|
||||
input wire logic [3:0] qsfp_0_rx_n,
|
||||
input wire logic qsfp_mgt_refclk_p,
|
||||
input wire logic qsfp_mgt_refclk_n,
|
||||
output wire logic qsfp_0_modsell,
|
||||
output wire logic qsfp_0_resetl,
|
||||
input wire logic qsfp_0_modprsl,
|
||||
input wire logic qsfp_0_intl,
|
||||
output wire logic qsfp_0_lpmode,
|
||||
|
||||
output wire logic [3:0] qsfp_1_tx_p,
|
||||
output wire logic [3:0] qsfp_1_tx_n,
|
||||
input wire logic [3:0] qsfp_1_rx_p,
|
||||
input wire logic [3:0] qsfp_1_rx_n,
|
||||
output wire logic qsfp_1_modsell,
|
||||
output wire logic qsfp_1_resetl,
|
||||
input wire logic qsfp_1_modprsl,
|
||||
input wire logic qsfp_1_intl,
|
||||
output wire logic qsfp_1_lpmode
|
||||
);
|
||||
|
||||
// Clock and reset
|
||||
|
||||
wire qsfp_mgt_refclk_out;
|
||||
|
||||
// Internal 125 MHz clock
|
||||
wire clk_125mhz_mmcm_out;
|
||||
wire clk_125mhz_int;
|
||||
wire rst_125mhz_int;
|
||||
|
||||
wire mmcm_rst = 1'b0;
|
||||
wire mmcm_locked;
|
||||
wire mmcm_clkfb;
|
||||
|
||||
// MMCM instance
|
||||
MMCME4_BASE #(
|
||||
// 161.13 MHz input
|
||||
.CLKIN1_PERIOD(6.206),
|
||||
.REF_JITTER1(0.010),
|
||||
// 161.13 MHz input / 11 = 14.65 MHz PFD (range 10 MHz to 500 MHz)
|
||||
.DIVCLK_DIVIDE(11),
|
||||
// 14.65 MHz PFD * 64 = 937.5 MHz VCO (range 800 MHz to 1600 MHz)
|
||||
.CLKFBOUT_MULT_F(64),
|
||||
.CLKFBOUT_PHASE(0),
|
||||
// 937.5 MHz / 7.5 = 125 MHz, 0 degrees
|
||||
.CLKOUT0_DIVIDE_F(7.5),
|
||||
.CLKOUT0_DUTY_CYCLE(0.5),
|
||||
.CLKOUT0_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT1_DIVIDE(1),
|
||||
.CLKOUT1_DUTY_CYCLE(0.5),
|
||||
.CLKOUT1_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT2_DIVIDE(1),
|
||||
.CLKOUT2_DUTY_CYCLE(0.5),
|
||||
.CLKOUT2_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT3_DIVIDE(1),
|
||||
.CLKOUT3_DUTY_CYCLE(0.5),
|
||||
.CLKOUT3_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.5),
|
||||
.CLKOUT4_PHASE(0),
|
||||
.CLKOUT4_CASCADE("FALSE"),
|
||||
// Not used
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.5),
|
||||
.CLKOUT5_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.5),
|
||||
.CLKOUT6_PHASE(0),
|
||||
|
||||
// optimized bandwidth
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
// don't wait for lock during startup
|
||||
.STARTUP_WAIT("FALSE")
|
||||
)
|
||||
clk_mmcm_inst (
|
||||
// 161.13 MHz input
|
||||
.CLKIN1(qsfp_mgt_refclk_out),
|
||||
// direct clkfb feeback
|
||||
.CLKFBIN(mmcm_clkfb),
|
||||
.CLKFBOUT(mmcm_clkfb),
|
||||
.CLKFBOUTB(),
|
||||
// 125 MHz, 0 degrees
|
||||
.CLKOUT0(clk_125mhz_mmcm_out),
|
||||
.CLKOUT0B(),
|
||||
// Not used
|
||||
.CLKOUT1(),
|
||||
.CLKOUT1B(),
|
||||
// Not used
|
||||
.CLKOUT2(),
|
||||
.CLKOUT2B(),
|
||||
// Not used
|
||||
.CLKOUT3(),
|
||||
.CLKOUT3B(),
|
||||
// Not used
|
||||
.CLKOUT4(),
|
||||
// Not used
|
||||
.CLKOUT5(),
|
||||
// Not used
|
||||
.CLKOUT6(),
|
||||
// reset input
|
||||
.RST(mmcm_rst),
|
||||
// don't power down
|
||||
.PWRDWN(1'b0),
|
||||
// locked output
|
||||
.LOCKED(mmcm_locked)
|
||||
);
|
||||
|
||||
BUFG
|
||||
clk_125mhz_bufg_inst (
|
||||
.I(clk_125mhz_mmcm_out),
|
||||
.O(clk_125mhz_int)
|
||||
);
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_125mhz_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.rst(~mmcm_locked),
|
||||
.out(rst_125mhz_int)
|
||||
);
|
||||
|
||||
fpga_core #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
* Clock: 125 MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
.clk_125mhz(clk_125mhz_int),
|
||||
.rst_125mhz(rst_125mhz_int),
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
.qsfp_led_green(qsfp_led_green),
|
||||
.qsfp_led_orange(qsfp_led_orange),
|
||||
.sma_led_green(sma_led_green),
|
||||
.sma_led_red(sma_led_red),
|
||||
|
||||
/*
|
||||
* Ethernet: SFP+
|
||||
*/
|
||||
.qsfp_0_tx_p(qsfp_0_tx_p),
|
||||
.qsfp_0_tx_n(qsfp_0_tx_n),
|
||||
.qsfp_0_rx_p(qsfp_0_rx_p),
|
||||
.qsfp_0_rx_n(qsfp_0_rx_n),
|
||||
.qsfp_mgt_refclk_p(qsfp_mgt_refclk_p),
|
||||
.qsfp_mgt_refclk_n(qsfp_mgt_refclk_n),
|
||||
.qsfp_mgt_refclk_out(qsfp_mgt_refclk_out),
|
||||
.qsfp_0_modsell(qsfp_0_modsell),
|
||||
.qsfp_0_resetl(qsfp_0_resetl),
|
||||
.qsfp_0_modprsl(qsfp_0_modprsl),
|
||||
.qsfp_0_intl(qsfp_0_intl),
|
||||
.qsfp_0_lpmode(qsfp_0_lpmode),
|
||||
|
||||
.qsfp_1_tx_p(qsfp_1_tx_p),
|
||||
.qsfp_1_tx_n(qsfp_1_tx_n),
|
||||
.qsfp_1_rx_p(qsfp_1_rx_p),
|
||||
.qsfp_1_rx_n(qsfp_1_rx_n),
|
||||
.qsfp_1_modsell(qsfp_1_modsell),
|
||||
.qsfp_1_resetl(qsfp_1_resetl),
|
||||
.qsfp_1_modprsl(qsfp_1_modprsl),
|
||||
.qsfp_1_intl(qsfp_1_intl),
|
||||
.qsfp_1_lpmode(qsfp_1_lpmode)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
549
example/Nexus_K3P_Q/fpga/rtl/fpga_core.sv
Normal file
549
example/Nexus_K3P_Q/fpga/rtl/fpga_core.sv
Normal file
@@ -0,0 +1,549 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA core logic
|
||||
*/
|
||||
module fpga_core #
|
||||
(
|
||||
parameter logic SIM = 1'b0,
|
||||
parameter string VENDOR = "XILINX",
|
||||
parameter string FAMILY = "kintexuplus"
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Clock: 125MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
input wire logic clk_125mhz,
|
||||
input wire logic rst_125mhz,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
output wire logic [1:0] qsfp_led_green,
|
||||
output wire logic [1:0] qsfp_led_orange,
|
||||
output wire logic sma_led_green,
|
||||
output wire logic sma_led_red,
|
||||
|
||||
/*
|
||||
* Ethernet: SFP+
|
||||
*/
|
||||
output wire logic [3:0] qsfp_0_tx_p,
|
||||
output wire logic [3:0] qsfp_0_tx_n,
|
||||
input wire logic [3:0] qsfp_0_rx_p,
|
||||
input wire logic [3:0] qsfp_0_rx_n,
|
||||
input wire logic qsfp_mgt_refclk_p,
|
||||
input wire logic qsfp_mgt_refclk_n,
|
||||
output wire logic qsfp_mgt_refclk_out,
|
||||
output wire logic qsfp_0_modsell,
|
||||
output wire logic qsfp_0_resetl,
|
||||
input wire logic qsfp_0_modprsl,
|
||||
input wire logic qsfp_0_intl,
|
||||
output wire logic qsfp_0_lpmode,
|
||||
|
||||
output wire logic [3:0] qsfp_1_tx_p,
|
||||
output wire logic [3:0] qsfp_1_tx_n,
|
||||
input wire logic [3:0] qsfp_1_rx_p,
|
||||
input wire logic [3:0] qsfp_1_rx_n,
|
||||
output wire logic qsfp_1_modsell,
|
||||
output wire logic qsfp_1_resetl,
|
||||
input wire logic qsfp_1_modprsl,
|
||||
input wire logic qsfp_1_intl,
|
||||
output wire logic qsfp_1_lpmode
|
||||
);
|
||||
|
||||
// QSFP28
|
||||
assign qsfp_0_modsell = 1'b0;
|
||||
assign qsfp_0_resetl = 1'b1;
|
||||
assign qsfp_0_lpmode = 1'b0;
|
||||
|
||||
assign qsfp_1_modsell = 1'b0;
|
||||
assign qsfp_1_resetl = 1'b1;
|
||||
assign qsfp_1_lpmode = 1'b0;
|
||||
|
||||
wire [7:0] qsfp_tx_clk;
|
||||
wire [7:0] qsfp_tx_rst;
|
||||
wire [7:0] qsfp_rx_clk;
|
||||
wire [7:0] qsfp_rx_rst;
|
||||
|
||||
wire [7:0] qsfp_rx_status;
|
||||
|
||||
assign qsfp_led_green[0] = qsfp_rx_status[0];
|
||||
assign qsfp_led_orange[0] = 1'b0;
|
||||
assign qsfp_led_green[1] = qsfp_rx_status[4];
|
||||
assign qsfp_led_orange[1] = 1'b0;
|
||||
assign sma_led_green = 1'b0;
|
||||
assign sma_led_red = 1'b0;
|
||||
|
||||
wire [1:0] qsfp_gtpowergood;
|
||||
|
||||
wire qsfp_mgt_refclk;
|
||||
wire qsfp_mgt_refclk_int;
|
||||
wire qsfp_mgt_refclk_bufg;
|
||||
|
||||
assign qsfp_mgt_refclk_out = qsfp_mgt_refclk_bufg;
|
||||
|
||||
wire qsfp_rst;
|
||||
|
||||
taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_qsfp_tx[7:0]();
|
||||
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_qsfp_tx_cpl[7:0]();
|
||||
taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_qsfp_rx[7:0]();
|
||||
|
||||
if (SIM) begin
|
||||
|
||||
assign qsfp_mgt_refclk = qsfp_mgt_refclk_p;
|
||||
assign qsfp_mgt_refclk_int = qsfp_mgt_refclk_p;
|
||||
assign qsfp_mgt_refclk_bufg = qsfp_mgt_refclk_int;
|
||||
|
||||
end else begin
|
||||
|
||||
IBUFDS_GTE4 ibufds_gte4_qsfp_mgt_refclk_inst (
|
||||
.I (qsfp_mgt_refclk_p),
|
||||
.IB (qsfp_mgt_refclk_n),
|
||||
.CEB (1'b0),
|
||||
.O (qsfp_mgt_refclk),
|
||||
.ODIV2 (qsfp_mgt_refclk_int)
|
||||
);
|
||||
|
||||
BUFG_GT bufg_gt_qsfp_mgt_refclk_inst (
|
||||
.CE (&qsfp_gtpowergood),
|
||||
.CEMASK (1'b1),
|
||||
.CLR (1'b0),
|
||||
.CLRMASK (1'b1),
|
||||
.DIV (3'd0),
|
||||
.I (qsfp_mgt_refclk_int),
|
||||
.O (qsfp_mgt_refclk_bufg)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
qsfp_sync_reset_inst (
|
||||
.clk(qsfp_mgt_refclk_bufg),
|
||||
.rst(rst_125mhz),
|
||||
.out(qsfp_rst)
|
||||
);
|
||||
|
||||
taxi_eth_mac_25g_us #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
|
||||
.CNT(4),
|
||||
|
||||
// GT type
|
||||
.GT_TYPE("GTY"),
|
||||
|
||||
// GT parameters
|
||||
.GT_TX_POLARITY(4'b0000),
|
||||
.GT_RX_POLARITY(4'b0000),
|
||||
|
||||
// MAC/PHY parameters
|
||||
.PADDING_EN(1'b1),
|
||||
.DIC_EN(1'b1),
|
||||
.MIN_FRAME_LEN(64),
|
||||
.PTP_TS_EN(1'b0),
|
||||
.PTP_TS_FMT_TOD(1'b1),
|
||||
.PTP_TS_W(96),
|
||||
.PRBS31_EN(1'b0),
|
||||
.TX_SERDES_PIPELINE(1),
|
||||
.RX_SERDES_PIPELINE(1),
|
||||
.COUNT_125US(125000/6.4)
|
||||
)
|
||||
qsfp_0_mac_inst (
|
||||
.xcvr_ctrl_clk(clk_125mhz),
|
||||
.xcvr_ctrl_rst(qsfp_rst),
|
||||
|
||||
/*
|
||||
* Common
|
||||
*/
|
||||
.xcvr_gtpowergood_out(qsfp_gtpowergood[0]),
|
||||
.xcvr_gtrefclk00_in(qsfp_mgt_refclk),
|
||||
.xcvr_qpll0lock_out(),
|
||||
.xcvr_qpll0clk_out(),
|
||||
.xcvr_qpll0refclk_out(),
|
||||
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp(qsfp_0_tx_p),
|
||||
.xcvr_txn(qsfp_0_tx_n),
|
||||
.xcvr_rxp(qsfp_0_rx_p),
|
||||
.xcvr_rxn(qsfp_0_rx_n),
|
||||
|
||||
/*
|
||||
* MAC clocks
|
||||
*/
|
||||
.rx_clk(qsfp_rx_clk[3:0]),
|
||||
.rx_rst_in('0),
|
||||
.rx_rst_out(qsfp_rx_rst[3:0]),
|
||||
.tx_clk(qsfp_tx_clk[3:0]),
|
||||
.tx_rst_in('0),
|
||||
.tx_rst_out(qsfp_tx_rst[3:0]),
|
||||
.ptp_sample_clk('0),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(axis_qsfp_tx[3:0]),
|
||||
.m_axis_tx_cpl(axis_qsfp_tx_cpl[3:0]),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(axis_qsfp_rx[3:0]),
|
||||
|
||||
/*
|
||||
* PTP clock
|
||||
*/
|
||||
.tx_ptp_ts('0),
|
||||
.tx_ptp_ts_step('0),
|
||||
.rx_ptp_ts('0),
|
||||
.rx_ptp_ts_step('0),
|
||||
|
||||
|
||||
/*
|
||||
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
|
||||
*/
|
||||
.tx_lfc_req('0),
|
||||
.tx_lfc_resend('0),
|
||||
.rx_lfc_en('0),
|
||||
.rx_lfc_req(),
|
||||
.rx_lfc_ack('0),
|
||||
|
||||
/*
|
||||
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
|
||||
*/
|
||||
.tx_pfc_req('0),
|
||||
.tx_pfc_resend('0),
|
||||
.rx_pfc_en('0),
|
||||
.rx_pfc_req(),
|
||||
.rx_pfc_ack('0),
|
||||
|
||||
/*
|
||||
* Pause interface
|
||||
*/
|
||||
.tx_lfc_pause_en('0),
|
||||
.tx_pause_req('0),
|
||||
.tx_pause_ack(),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_start_packet(),
|
||||
.tx_error_underflow(),
|
||||
.rx_start_packet(),
|
||||
.rx_error_count(),
|
||||
.rx_error_bad_frame(),
|
||||
.rx_error_bad_fcs(),
|
||||
.rx_bad_block(),
|
||||
.rx_sequence_error(),
|
||||
.rx_block_lock(),
|
||||
.rx_high_ber(),
|
||||
.rx_status(qsfp_rx_status[3:0]),
|
||||
.stat_tx_mcf(),
|
||||
.stat_rx_mcf(),
|
||||
.stat_tx_lfc_pkt(),
|
||||
.stat_tx_lfc_xon(),
|
||||
.stat_tx_lfc_xoff(),
|
||||
.stat_tx_lfc_paused(),
|
||||
.stat_tx_pfc_pkt(),
|
||||
.stat_tx_pfc_xon(),
|
||||
.stat_tx_pfc_xoff(),
|
||||
.stat_tx_pfc_paused(),
|
||||
.stat_rx_lfc_pkt(),
|
||||
.stat_rx_lfc_xon(),
|
||||
.stat_rx_lfc_xoff(),
|
||||
.stat_rx_lfc_paused(),
|
||||
.stat_rx_pfc_pkt(),
|
||||
.stat_rx_pfc_xon(),
|
||||
.stat_rx_pfc_xoff(),
|
||||
.stat_rx_pfc_paused(),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_ifg('{4{8'd12}}),
|
||||
.cfg_tx_enable('1),
|
||||
.cfg_rx_enable('1),
|
||||
.cfg_tx_prbs31_enable('0),
|
||||
.cfg_rx_prbs31_enable('0),
|
||||
.cfg_mcf_rx_eth_dst_mcast('{4{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_mcf_rx_check_eth_dst_mcast('1),
|
||||
.cfg_mcf_rx_eth_dst_ucast('{4{48'd0}}),
|
||||
.cfg_mcf_rx_check_eth_dst_ucast('0),
|
||||
.cfg_mcf_rx_eth_src('{4{48'd0}}),
|
||||
.cfg_mcf_rx_check_eth_src('0),
|
||||
.cfg_mcf_rx_eth_type('{4{16'h8808}}),
|
||||
.cfg_mcf_rx_opcode_lfc('{4{16'h0001}}),
|
||||
.cfg_mcf_rx_check_opcode_lfc('1),
|
||||
.cfg_mcf_rx_opcode_pfc('{4{16'h0101}}),
|
||||
.cfg_mcf_rx_check_opcode_pfc('1),
|
||||
.cfg_mcf_rx_forward('0),
|
||||
.cfg_mcf_rx_enable('0),
|
||||
.cfg_tx_lfc_eth_dst('{4{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_tx_lfc_eth_src('{4{48'h80_23_31_43_54_4C}}),
|
||||
.cfg_tx_lfc_eth_type('{4{16'h8808}}),
|
||||
.cfg_tx_lfc_opcode('{4{16'h0001}}),
|
||||
.cfg_tx_lfc_en('0),
|
||||
.cfg_tx_lfc_quanta('{4{16'hffff}}),
|
||||
.cfg_tx_lfc_refresh('{4{16'h7fff}}),
|
||||
.cfg_tx_pfc_eth_dst('{4{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_tx_pfc_eth_src('{4{48'h80_23_31_43_54_4C}}),
|
||||
.cfg_tx_pfc_eth_type('{4{16'h8808}}),
|
||||
.cfg_tx_pfc_opcode('{4{16'h0101}}),
|
||||
.cfg_tx_pfc_en('0),
|
||||
.cfg_tx_pfc_quanta('{4{'{8{16'hffff}}}}),
|
||||
.cfg_tx_pfc_refresh('{4{'{8{16'h7fff}}}}),
|
||||
.cfg_rx_lfc_opcode('{4{16'h0001}}),
|
||||
.cfg_rx_lfc_en('0),
|
||||
.cfg_rx_pfc_opcode('{4{16'h0101}}),
|
||||
.cfg_rx_pfc_en('0)
|
||||
);
|
||||
|
||||
taxi_eth_mac_25g_us #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
|
||||
.CNT(4),
|
||||
|
||||
// GT type
|
||||
.GT_TYPE("GTY"),
|
||||
|
||||
// GT parameters
|
||||
.GT_TX_POLARITY(4'b1001),
|
||||
.GT_RX_POLARITY(4'b0000),
|
||||
|
||||
// MAC/PHY parameters
|
||||
.PADDING_EN(1'b1),
|
||||
.DIC_EN(1'b1),
|
||||
.MIN_FRAME_LEN(64),
|
||||
.PTP_TS_EN(1'b0),
|
||||
.PTP_TS_FMT_TOD(1'b1),
|
||||
.PTP_TS_W(96),
|
||||
.PRBS31_EN(1'b0),
|
||||
.TX_SERDES_PIPELINE(1),
|
||||
.RX_SERDES_PIPELINE(1),
|
||||
.COUNT_125US(125000/6.4)
|
||||
)
|
||||
qsfp_1_mac_inst (
|
||||
.xcvr_ctrl_clk(clk_125mhz),
|
||||
.xcvr_ctrl_rst(qsfp_rst),
|
||||
|
||||
/*
|
||||
* Common
|
||||
*/
|
||||
.xcvr_gtpowergood_out(qsfp_gtpowergood[1]),
|
||||
.xcvr_gtrefclk00_in(qsfp_mgt_refclk),
|
||||
.xcvr_qpll0lock_out(),
|
||||
.xcvr_qpll0clk_out(),
|
||||
.xcvr_qpll0refclk_out(),
|
||||
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp(qsfp_1_tx_p),
|
||||
.xcvr_txn(qsfp_1_tx_n),
|
||||
.xcvr_rxp(qsfp_1_rx_p),
|
||||
.xcvr_rxn(qsfp_1_rx_n),
|
||||
|
||||
/*
|
||||
* MAC clocks
|
||||
*/
|
||||
.rx_clk(qsfp_rx_clk[7:4]),
|
||||
.rx_rst_in('0),
|
||||
.rx_rst_out(qsfp_rx_rst[7:4]),
|
||||
.tx_clk(qsfp_tx_clk[7:4]),
|
||||
.tx_rst_in('0),
|
||||
.tx_rst_out(qsfp_tx_rst[7:4]),
|
||||
.ptp_sample_clk('0),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(axis_qsfp_tx[7:4]),
|
||||
.m_axis_tx_cpl(axis_qsfp_tx_cpl[7:4]),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(axis_qsfp_rx[7:4]),
|
||||
|
||||
/*
|
||||
* PTP clock
|
||||
*/
|
||||
.tx_ptp_ts('0),
|
||||
.tx_ptp_ts_step('0),
|
||||
.rx_ptp_ts('0),
|
||||
.rx_ptp_ts_step('0),
|
||||
|
||||
|
||||
/*
|
||||
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
|
||||
*/
|
||||
.tx_lfc_req('0),
|
||||
.tx_lfc_resend('0),
|
||||
.rx_lfc_en('0),
|
||||
.rx_lfc_req(),
|
||||
.rx_lfc_ack('0),
|
||||
|
||||
/*
|
||||
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
|
||||
*/
|
||||
.tx_pfc_req('0),
|
||||
.tx_pfc_resend('0),
|
||||
.rx_pfc_en('0),
|
||||
.rx_pfc_req(),
|
||||
.rx_pfc_ack('0),
|
||||
|
||||
/*
|
||||
* Pause interface
|
||||
*/
|
||||
.tx_lfc_pause_en('0),
|
||||
.tx_pause_req('0),
|
||||
.tx_pause_ack(),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_start_packet(),
|
||||
.tx_error_underflow(),
|
||||
.rx_start_packet(),
|
||||
.rx_error_count(),
|
||||
.rx_error_bad_frame(),
|
||||
.rx_error_bad_fcs(),
|
||||
.rx_bad_block(),
|
||||
.rx_sequence_error(),
|
||||
.rx_block_lock(),
|
||||
.rx_high_ber(),
|
||||
.rx_status(qsfp_rx_status[7:4]),
|
||||
.stat_tx_mcf(),
|
||||
.stat_rx_mcf(),
|
||||
.stat_tx_lfc_pkt(),
|
||||
.stat_tx_lfc_xon(),
|
||||
.stat_tx_lfc_xoff(),
|
||||
.stat_tx_lfc_paused(),
|
||||
.stat_tx_pfc_pkt(),
|
||||
.stat_tx_pfc_xon(),
|
||||
.stat_tx_pfc_xoff(),
|
||||
.stat_tx_pfc_paused(),
|
||||
.stat_rx_lfc_pkt(),
|
||||
.stat_rx_lfc_xon(),
|
||||
.stat_rx_lfc_xoff(),
|
||||
.stat_rx_lfc_paused(),
|
||||
.stat_rx_pfc_pkt(),
|
||||
.stat_rx_pfc_xon(),
|
||||
.stat_rx_pfc_xoff(),
|
||||
.stat_rx_pfc_paused(),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_ifg('{4{8'd12}}),
|
||||
.cfg_tx_enable('1),
|
||||
.cfg_rx_enable('1),
|
||||
.cfg_tx_prbs31_enable('0),
|
||||
.cfg_rx_prbs31_enable('0),
|
||||
.cfg_mcf_rx_eth_dst_mcast('{4{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_mcf_rx_check_eth_dst_mcast('1),
|
||||
.cfg_mcf_rx_eth_dst_ucast('{4{48'd0}}),
|
||||
.cfg_mcf_rx_check_eth_dst_ucast('0),
|
||||
.cfg_mcf_rx_eth_src('{4{48'd0}}),
|
||||
.cfg_mcf_rx_check_eth_src('0),
|
||||
.cfg_mcf_rx_eth_type('{4{16'h8808}}),
|
||||
.cfg_mcf_rx_opcode_lfc('{4{16'h0001}}),
|
||||
.cfg_mcf_rx_check_opcode_lfc('1),
|
||||
.cfg_mcf_rx_opcode_pfc('{4{16'h0101}}),
|
||||
.cfg_mcf_rx_check_opcode_pfc('1),
|
||||
.cfg_mcf_rx_forward('0),
|
||||
.cfg_mcf_rx_enable('0),
|
||||
.cfg_tx_lfc_eth_dst('{4{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_tx_lfc_eth_src('{4{48'h80_23_31_43_54_4C}}),
|
||||
.cfg_tx_lfc_eth_type('{4{16'h8808}}),
|
||||
.cfg_tx_lfc_opcode('{4{16'h0001}}),
|
||||
.cfg_tx_lfc_en('0),
|
||||
.cfg_tx_lfc_quanta('{4{16'hffff}}),
|
||||
.cfg_tx_lfc_refresh('{4{16'h7fff}}),
|
||||
.cfg_tx_pfc_eth_dst('{4{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_tx_pfc_eth_src('{4{48'h80_23_31_43_54_4C}}),
|
||||
.cfg_tx_pfc_eth_type('{4{16'h8808}}),
|
||||
.cfg_tx_pfc_opcode('{4{16'h0101}}),
|
||||
.cfg_tx_pfc_en('0),
|
||||
.cfg_tx_pfc_quanta('{4{'{8{16'hffff}}}}),
|
||||
.cfg_tx_pfc_refresh('{4{'{8{16'h7fff}}}}),
|
||||
.cfg_rx_lfc_opcode('{4{16'h0001}}),
|
||||
.cfg_rx_lfc_en('0),
|
||||
.cfg_rx_pfc_opcode('{4{16'h0101}}),
|
||||
.cfg_rx_pfc_en('0)
|
||||
);
|
||||
|
||||
for (genvar n = 0; n < 8; n = n + 1) begin : qsfp_ch
|
||||
|
||||
taxi_axis_async_fifo #(
|
||||
.DEPTH(16384),
|
||||
.RAM_PIPELINE(2),
|
||||
.FRAME_FIFO(1),
|
||||
.USER_BAD_FRAME_VALUE(1'b1),
|
||||
.USER_BAD_FRAME_MASK(1'b1),
|
||||
.DROP_OVERSIZE_FRAME(1),
|
||||
.DROP_BAD_FRAME(1),
|
||||
.DROP_WHEN_FULL(1)
|
||||
)
|
||||
ch_fifo (
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_clk(qsfp_rx_clk[n]),
|
||||
.s_rst(qsfp_rx_rst[n]),
|
||||
.s_axis(axis_qsfp_rx[n]),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_clk(qsfp_tx_clk[n]),
|
||||
.m_rst(qsfp_tx_rst[n]),
|
||||
.m_axis(axis_qsfp_tx[n]),
|
||||
|
||||
/*
|
||||
* Pause
|
||||
*/
|
||||
.s_pause_req(1'b0),
|
||||
.s_pause_ack(),
|
||||
.m_pause_req(1'b0),
|
||||
.m_pause_ack(),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.s_status_depth(),
|
||||
.s_status_depth_commit(),
|
||||
.s_status_overflow(),
|
||||
.s_status_bad_frame(),
|
||||
.s_status_good_frame(),
|
||||
.m_status_depth(),
|
||||
.m_status_depth_commit(),
|
||||
.m_status_overflow(),
|
||||
.m_status_bad_frame(),
|
||||
.m_status_good_frame()
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
51
example/Nexus_K3P_Q/fpga/tb/fpga_core/Makefile
Normal file
51
example/Nexus_K3P_Q/fpga/tb/fpga_core/Makefile
Normal file
@@ -0,0 +1,51 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
DUT = fpga_core
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = $(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += ../../rtl/$(DUT).sv
|
||||
VERILOG_SOURCES += ../../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f
|
||||
VERILOG_SOURCES += ../../lib/taxi/rtl/axis/taxi_axis_async_fifo.f
|
||||
VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_reset.sv
|
||||
VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_signal.sv
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_SIM := "1'b1"
|
||||
export PARAM_VENDOR := "\"XILINX\""
|
||||
export PARAM_FAMILY := "\"kintexuplus\""
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
1
example/Nexus_K3P_Q/fpga/tb/fpga_core/baser.py
Symbolic link
1
example/Nexus_K3P_Q/fpga/tb/fpga_core/baser.py
Symbolic link
@@ -0,0 +1 @@
|
||||
../../lib/taxi/tb/eth/baser.py
|
||||
195
example/Nexus_K3P_Q/fpga/tb/fpga_core/test_fpga_core.py
Normal file
195
example/Nexus_K3P_Q/fpga/tb/fpga_core/test_fpga_core.py
Normal file
@@ -0,0 +1,195 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: MIT
|
||||
"""
|
||||
|
||||
Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import logging
|
||||
import os
|
||||
import sys
|
||||
|
||||
import cocotb_test.simulator
|
||||
|
||||
import cocotb
|
||||
from cocotb.log import SimLog
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge, Combine
|
||||
|
||||
from cocotbext.eth import XgmiiFrame
|
||||
|
||||
try:
|
||||
from baser import BaseRSerdesSource, BaseRSerdesSink
|
||||
except ImportError:
|
||||
# attempt import from current directory
|
||||
sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
|
||||
try:
|
||||
from baser import BaseRSerdesSource, BaseRSerdesSink
|
||||
finally:
|
||||
del sys.path[0]
|
||||
|
||||
|
||||
class TB:
|
||||
def __init__(self, dut, speed=1000e6):
|
||||
self.dut = dut
|
||||
|
||||
self.log = SimLog("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start())
|
||||
cocotb.start_soon(Clock(dut.qsfp_mgt_refclk_p, 6.206, units="ns").start())
|
||||
|
||||
self.qsfp_sources = []
|
||||
self.qsfp_sinks = []
|
||||
|
||||
for inst in [dut.qsfp_0_mac_inst, dut.qsfp_1_mac_inst]:
|
||||
for ch in inst.ch:
|
||||
cocotb.start_soon(Clock(ch.ch_inst.tx_clk, 2.56, units="ns").start())
|
||||
cocotb.start_soon(Clock(ch.ch_inst.rx_clk, 2.56, units="ns").start())
|
||||
|
||||
self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
|
||||
self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True))
|
||||
|
||||
dut.qsfp_0_modprsl.setimmediatevalue(0)
|
||||
dut.qsfp_0_intl.setimmediatevalue(0)
|
||||
dut.qsfp_1_modprsl.setimmediatevalue(0)
|
||||
dut.qsfp_1_intl.setimmediatevalue(0)
|
||||
|
||||
async def init(self):
|
||||
|
||||
self.dut.rst_125mhz.setimmediatevalue(0)
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.clk_125mhz)
|
||||
|
||||
self.dut.rst_125mhz.value = 1
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.clk_125mhz)
|
||||
|
||||
self.dut.rst_125mhz.value = 0
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.clk_125mhz)
|
||||
|
||||
|
||||
async def mac_test(tb, source, sink):
|
||||
tb.log.info("Test MAC")
|
||||
|
||||
tb.log.info("Multiple small packets")
|
||||
|
||||
count = 64
|
||||
|
||||
pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
|
||||
|
||||
for p in pkts:
|
||||
await source.send(XgmiiFrame.from_payload(p))
|
||||
|
||||
for k in range(count):
|
||||
rx_frame = await sink.recv()
|
||||
|
||||
tb.log.info("RX frame: %s", rx_frame)
|
||||
|
||||
assert rx_frame.get_payload() == pkts[k]
|
||||
assert rx_frame.check_fcs()
|
||||
|
||||
tb.log.info("Multiple large packets")
|
||||
|
||||
count = 32
|
||||
|
||||
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
|
||||
|
||||
for p in pkts:
|
||||
await source.send(XgmiiFrame.from_payload(p))
|
||||
|
||||
for k in range(count):
|
||||
rx_frame = await sink.recv()
|
||||
|
||||
tb.log.info("RX frame: %s", rx_frame)
|
||||
|
||||
assert rx_frame.get_payload() == pkts[k]
|
||||
assert rx_frame.check_fcs()
|
||||
|
||||
tb.log.info("MAC test done")
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def run_test(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.init()
|
||||
|
||||
tests = []
|
||||
|
||||
for k in range(len(tb.qsfp_sources)):
|
||||
tb.log.info("Start QSFP %d MAC loopback test", k)
|
||||
|
||||
tests.append(cocotb.start_soon(mac_test(tb, tb.qsfp_sources[k], tb.qsfp_sinks[k])))
|
||||
|
||||
await Combine(*tests)
|
||||
|
||||
await RisingEdge(dut.clk_125mhz)
|
||||
await RisingEdge(dut.clk_125mhz)
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
def test_fpga_core(request):
|
||||
dut = "fpga_core"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = dut
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
os.path.join(lib_dir, "taxi", "rtl", "eth", "us", "taxi_eth_mac_25g_us.f"),
|
||||
os.path.join(lib_dir, "taxi", "rtl", "axis", "taxi_axis_async_fifo.f"),
|
||||
os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_reset.sv"),
|
||||
os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_signal.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['SIM'] = "1'b1"
|
||||
parameters['VENDOR'] = "\"XILINX\""
|
||||
parameters['FAMILY'] = "\"kintexuplus\""
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
Reference in New Issue
Block a user