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eth: Add 1000BASE-X MAC/PHY combination modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
12
src/eth/rtl/taxi_eth_mac_phy_1g_basex.f
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12
src/eth/rtl/taxi_eth_mac_phy_1g_basex.f
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@@ -0,0 +1,12 @@
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taxi_eth_mac_phy_1g_basex.sv
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taxi_eth_mac_phy_1g_basex_rx.f
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taxi_eth_mac_phy_1g_basex_tx.f
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taxi_eth_mac_stats.f
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taxi_mac_ctrl_tx.sv
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taxi_mac_ctrl_rx.sv
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taxi_mac_pause_ctrl_tx.sv
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taxi_mac_pause_ctrl_rx.sv
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../lib/taxi/src/axis/rtl/taxi_axis_null_src.sv
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../lib/taxi/src/axis/rtl/taxi_axis_tie.sv
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../lib/taxi/src/ptp/rtl/taxi_ptp_td_leaf.sv
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../lib/taxi/src/sync/rtl/taxi_sync_signal.sv
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888
src/eth/rtl/taxi_eth_mac_phy_1g_basex.sv
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888
src/eth/rtl/taxi_eth_mac_phy_1g_basex.sv
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@@ -0,0 +1,888 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2026 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* 1000BASE-X Ethernet MAC/PHY combination
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*/
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module taxi_eth_mac_phy_1g_basex #
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(
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parameter DATA_W = 16,
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parameter CTRL_W = (DATA_W/8),
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parameter logic TX_GBX_IF_EN = 1'b0,
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parameter logic RX_GBX_IF_EN = TX_GBX_IF_EN,
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parameter logic DIC_EN = 1'b1,
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parameter logic PTP_TS_EN = 1'b0,
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parameter logic PTP_TD_EN = PTP_TS_EN,
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parameter logic PTP_TS_FMT_TOD = 1'b1,
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parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64,
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parameter PTP_TD_SDI_PIPELINE = 2,
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parameter logic BIT_REVERSE = 1'b0,
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parameter logic ENC_8B10B_EN = 1'b0,
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parameter logic DEC_8B10B_EN = ENC_8B10B_EN,
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parameter logic PRBS31_EN = 1'b0,
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parameter TX_SERDES_PIPELINE = 0,
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parameter RX_SERDES_PIPELINE = 0,
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parameter logic PFC_EN = 1'b0,
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parameter logic PAUSE_EN = PFC_EN,
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parameter logic STAT_EN = 1'b0,
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parameter STAT_TX_LEVEL = 1,
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parameter STAT_RX_LEVEL = 1,
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parameter STAT_ID_BASE = 0,
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parameter STAT_UPDATE_PERIOD = 1024,
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parameter logic STAT_STR_EN = 1'b0,
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parameter logic [8*8-1:0] STAT_PREFIX_STR = "MAC"
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)
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(
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input wire logic rx_clk,
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input wire logic rx_rst,
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input wire logic tx_clk,
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input wire logic tx_rst,
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/*
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* Transmit interface (AXI stream)
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*/
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taxi_axis_if.snk s_axis_tx,
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taxi_axis_if.src m_axis_tx_cpl,
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/*
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* Receive interface (AXI stream)
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*/
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taxi_axis_if.src m_axis_rx,
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/*
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* SERDES interface
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*/
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output wire logic [DATA_W-1:0] serdes_tx_data,
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output wire logic [CTRL_W-1:0] serdes_tx_data_k,
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output wire logic [CTRL_W-1:0] serdes_tx_data_dm,
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output wire logic [CTRL_W-1:0] serdes_tx_data_dv,
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output wire logic serdes_tx_data_valid,
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input wire logic serdes_tx_gbx_req_sync = 1'b0,
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input wire logic serdes_tx_gbx_req_stall = 1'b0,
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output wire logic serdes_tx_gbx_sync,
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input wire logic [DATA_W-1:0] serdes_rx_data,
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input wire logic [CTRL_W-1:0] serdes_rx_data_k,
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input wire logic serdes_rx_data_valid = 1'b1,
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output wire logic serdes_rx_reset_req,
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/*
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* PTP
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*/
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input wire logic ptp_clk = 1'b0,
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input wire logic ptp_rst = 1'b0,
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input wire logic ptp_sample_clk = 1'b0,
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input wire logic ptp_td_sdi = 1'b0,
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input wire logic [PTP_TS_W-1:0] tx_ptp_ts_in = '0,
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output wire logic [PTP_TS_W-1:0] tx_ptp_ts_out,
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output wire logic tx_ptp_ts_step_out,
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output wire logic tx_ptp_locked,
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input wire logic [PTP_TS_W-1:0] rx_ptp_ts_in = '0,
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output wire logic [PTP_TS_W-1:0] rx_ptp_ts_out,
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output wire logic rx_ptp_ts_step_out,
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output wire logic rx_ptp_locked,
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/*
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* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
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*/
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input wire logic tx_lfc_req = 1'b0,
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input wire logic tx_lfc_resend = 1'b0,
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input wire logic rx_lfc_en = 1'b0,
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output wire logic rx_lfc_req,
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input wire logic rx_lfc_ack = 1'b0,
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/*
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* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
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*/
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input wire logic [7:0] tx_pfc_req = '0,
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input wire logic tx_pfc_resend = 1'b0,
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input wire logic [7:0] rx_pfc_en = '0,
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output wire logic [7:0] rx_pfc_req,
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input wire logic [7:0] rx_pfc_ack = '0,
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/*
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* Pause interface
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*/
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input wire logic tx_lfc_pause_en = 1'b0,
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input wire logic tx_pause_req = 1'b0,
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output wire logic tx_pause_ack,
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/*
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* Statistics
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*/
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input wire logic stat_clk,
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input wire logic stat_rst,
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taxi_axis_if.src m_axis_stat,
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/*
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* Status
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*/
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output wire logic [1:0] tx_start_packet,
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output wire logic [1:0] stat_tx_byte,
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output wire logic [15:0] stat_tx_pkt_len,
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output wire logic stat_tx_pkt_ucast,
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output wire logic stat_tx_pkt_mcast,
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output wire logic stat_tx_pkt_bcast,
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output wire logic stat_tx_pkt_vlan,
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output wire logic stat_tx_pkt_good,
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output wire logic stat_tx_pkt_bad,
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output wire logic stat_tx_pad_frame,
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output wire logic stat_tx_err_oversize,
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output wire logic stat_tx_err_user,
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output wire logic stat_tx_err_underflow,
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output wire logic [1:0] rx_start_packet,
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output wire logic [4:0] rx_error_count,
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output wire logic rx_block_lock,
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output wire logic rx_high_ber,
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output wire logic rx_status,
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output wire logic [1:0] stat_rx_byte,
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output wire logic [15:0] stat_rx_pkt_len,
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output wire logic stat_rx_pkt_fragment,
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output wire logic stat_rx_pkt_jabber,
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output wire logic stat_rx_pkt_ucast,
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output wire logic stat_rx_pkt_mcast,
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output wire logic stat_rx_pkt_bcast,
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output wire logic stat_rx_pkt_vlan,
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output wire logic stat_rx_pkt_good,
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output wire logic stat_rx_pkt_bad,
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output wire logic stat_rx_err_oversize,
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output wire logic stat_rx_err_bad_fcs,
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output wire logic stat_rx_err_bad_block,
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output wire logic stat_rx_err_framing,
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output wire logic stat_rx_err_preamble,
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input wire logic stat_rx_fifo_drop = 1'b0,
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output wire logic stat_tx_mcf,
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output wire logic stat_rx_mcf,
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output wire logic stat_tx_lfc_pkt,
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output wire logic stat_tx_lfc_xon,
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output wire logic stat_tx_lfc_xoff,
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output wire logic stat_tx_lfc_paused,
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output wire logic stat_tx_pfc_pkt,
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output wire logic [7:0] stat_tx_pfc_xon,
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output wire logic [7:0] stat_tx_pfc_xoff,
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output wire logic [7:0] stat_tx_pfc_paused,
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output wire logic stat_rx_lfc_pkt,
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output wire logic stat_rx_lfc_xon,
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output wire logic stat_rx_lfc_xoff,
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output wire logic stat_rx_lfc_paused,
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output wire logic stat_rx_pfc_pkt,
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output wire logic [7:0] stat_rx_pfc_xon,
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output wire logic [7:0] stat_rx_pfc_xoff,
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output wire logic [7:0] stat_rx_pfc_paused,
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/*
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* Configuration
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*/
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input wire logic cfg_tx_pad_en = 1'b1,
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input wire logic [7:0] cfg_tx_min_pkt_len = 8'd60-1,
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input wire logic [15:0] cfg_tx_max_pkt_len = 16'd1518-1,
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input wire logic [7:0] cfg_tx_ifg = 8'd12,
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input wire logic cfg_tx_enable = 1'b1,
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input wire logic [15:0] cfg_rx_max_pkt_len = 16'd1518-1,
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input wire logic cfg_rx_enable = 1'b1,
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input wire logic cfg_tx_prbs31_enable = 1'b0,
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input wire logic cfg_rx_prbs31_enable = 1'b0,
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input wire logic [47:0] cfg_mcf_rx_eth_dst_mcast = 48'h01_80_C2_00_00_01,
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input wire logic cfg_mcf_rx_check_eth_dst_mcast = 1'b1,
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input wire logic [47:0] cfg_mcf_rx_eth_dst_ucast = 48'd0,
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input wire logic cfg_mcf_rx_check_eth_dst_ucast = 1'b0,
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input wire logic [47:0] cfg_mcf_rx_eth_src = 48'd0,
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input wire logic cfg_mcf_rx_check_eth_src = 1'b0,
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input wire logic [15:0] cfg_mcf_rx_eth_type = 16'h8808,
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input wire logic [15:0] cfg_mcf_rx_opcode_lfc = 16'h0001,
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input wire logic cfg_mcf_rx_check_opcode_lfc = 1'b1,
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input wire logic [15:0] cfg_mcf_rx_opcode_pfc = 16'h0101,
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input wire logic cfg_mcf_rx_check_opcode_pfc = 1'b1,
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input wire logic cfg_mcf_rx_forward = 1'b0,
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input wire logic cfg_mcf_rx_enable = 1'b0,
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input wire logic [47:0] cfg_tx_lfc_eth_dst = 48'h01_80_C2_00_00_01,
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input wire logic [47:0] cfg_tx_lfc_eth_src = 48'h80_23_31_43_54_4C,
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input wire logic [15:0] cfg_tx_lfc_eth_type = 16'h8808,
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input wire logic [15:0] cfg_tx_lfc_opcode = 16'h0001,
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input wire logic cfg_tx_lfc_en = 1'b0,
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input wire logic [15:0] cfg_tx_lfc_quanta = 16'hffff,
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input wire logic [15:0] cfg_tx_lfc_refresh = 16'h7fff,
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input wire logic [47:0] cfg_tx_pfc_eth_dst = 48'h01_80_C2_00_00_01,
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input wire logic [47:0] cfg_tx_pfc_eth_src = 48'h80_23_31_43_54_4C,
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input wire logic [15:0] cfg_tx_pfc_eth_type = 16'h8808,
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input wire logic [15:0] cfg_tx_pfc_opcode = 16'h0101,
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input wire logic cfg_tx_pfc_en = 1'b0,
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input wire logic [15:0] cfg_tx_pfc_quanta[8] = '{8{16'hffff}},
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input wire logic [15:0] cfg_tx_pfc_refresh[8] = '{8{16'h7fff}},
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input wire logic [15:0] cfg_rx_lfc_opcode = 16'h0001,
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input wire logic cfg_rx_lfc_en = 1'b0,
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input wire logic [15:0] cfg_rx_pfc_opcode = 16'h0101,
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input wire logic cfg_rx_pfc_en = 1'b0
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);
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localparam KEEP_W = s_axis_tx.KEEP_W;
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localparam TX_USER_W = 1;
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localparam RX_USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1;
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localparam TX_TAG_W = s_axis_tx.ID_W;
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localparam MAC_CTRL_EN = PAUSE_EN || PFC_EN;
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localparam TX_USER_W_INT = (MAC_CTRL_EN ? 1 : 0) + TX_USER_W;
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taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(TX_USER_W_INT), .ID_EN(1), .ID_W(TX_TAG_W)) axis_tx_int();
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taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(RX_USER_W)) axis_rx_int();
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// PTP timestamping
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if (PTP_TS_EN && PTP_TD_EN) begin : ptp
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// TX
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wire [PTP_TS_W-1:0] tx_ptp_ts_rel;
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wire tx_ptp_ts_rel_step;
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wire [PTP_TS_W-1:0] tx_ptp_ts_tod;
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wire tx_ptp_ts_tod_step;
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taxi_ptp_td_leaf #(
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.TS_REL_EN(!PTP_TS_FMT_TOD),
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.TS_TOD_EN(PTP_TS_FMT_TOD),
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.TS_FNS_W(16),
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.TS_REL_NS_W(PTP_TS_FMT_TOD ? 48 : PTP_TS_W-16),
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.TS_TOD_S_W(PTP_TS_FMT_TOD ? PTP_TS_W-32-16 : 48),
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.TS_REL_W(PTP_TS_W),
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.TS_TOD_W(PTP_TS_W),
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.TD_SDI_PIPELINE(PTP_TD_SDI_PIPELINE)
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)
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tx_leaf_inst (
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.clk(tx_clk),
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.rst(tx_rst),
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.sample_clk(ptp_sample_clk),
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/*
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* PTP clock interface
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*/
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.ptp_clk(ptp_clk),
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.ptp_rst(ptp_rst),
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.ptp_td_sdi(ptp_td_sdi),
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/*
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* Timestamp output
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*/
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.output_ts_rel(tx_ptp_ts_rel),
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.output_ts_rel_step(tx_ptp_ts_rel_step),
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.output_ts_tod(tx_ptp_ts_tod),
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.output_ts_tod_step(tx_ptp_ts_tod_step),
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/*
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* PPS output (ToD format only)
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*/
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.output_pps(),
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.output_pps_str(),
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/*
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* Status
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*/
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.locked(tx_ptp_locked)
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);
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assign tx_ptp_ts_out = PTP_TS_FMT_TOD ? tx_ptp_ts_tod : tx_ptp_ts_rel;
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assign tx_ptp_ts_step_out = PTP_TS_FMT_TOD ? tx_ptp_ts_tod_step : tx_ptp_ts_rel_step;
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// RX
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wire [PTP_TS_W-1:0] rx_ptp_ts_rel;
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wire rx_ptp_ts_rel_step;
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wire [PTP_TS_W-1:0] rx_ptp_ts_tod;
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wire rx_ptp_ts_tod_step;
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taxi_ptp_td_leaf #(
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.TS_REL_EN(!PTP_TS_FMT_TOD),
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.TS_TOD_EN(PTP_TS_FMT_TOD),
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.TS_FNS_W(16),
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.TS_REL_NS_W(PTP_TS_FMT_TOD ? 48 : PTP_TS_W-16),
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.TS_TOD_S_W(PTP_TS_FMT_TOD ? PTP_TS_W-32-16 : 48),
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.TS_REL_W(PTP_TS_W),
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.TS_TOD_W(PTP_TS_W),
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.TD_SDI_PIPELINE(PTP_TD_SDI_PIPELINE)
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)
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rx_leaf_inst (
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.clk(rx_clk),
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.rst(rx_rst),
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.sample_clk(ptp_sample_clk),
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/*
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* PTP clock interface
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*/
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.ptp_clk(ptp_clk),
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.ptp_rst(ptp_rst),
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.ptp_td_sdi(ptp_td_sdi),
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/*
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* Timestamp output
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*/
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.output_ts_rel(rx_ptp_ts_rel),
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.output_ts_rel_step(rx_ptp_ts_rel_step),
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.output_ts_tod(rx_ptp_ts_tod),
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.output_ts_tod_step(rx_ptp_ts_tod_step),
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/*
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* PPS output (ToD format only)
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*/
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.output_pps(),
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.output_pps_str(),
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/*
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* Status
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*/
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.locked(rx_ptp_locked)
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);
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assign rx_ptp_ts_out = PTP_TS_FMT_TOD ? rx_ptp_ts_tod : rx_ptp_ts_rel;
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assign rx_ptp_ts_step_out = PTP_TS_FMT_TOD ? rx_ptp_ts_tod_step : rx_ptp_ts_rel_step;
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end else begin
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assign tx_ptp_ts_out = tx_ptp_ts_in;
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assign tx_ptp_ts_step_out = 1'b0;
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assign rx_ptp_ts_out = rx_ptp_ts_in;
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assign rx_ptp_ts_step_out = 1'b0;
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assign tx_ptp_locked = 1'b0;
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assign rx_ptp_locked = 1'b0;
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end
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taxi_eth_mac_phy_1g_basex_rx #(
|
||||
.DATA_W(DATA_W),
|
||||
.CTRL_W(CTRL_W),
|
||||
.GBX_IF_EN(RX_GBX_IF_EN),
|
||||
.PTP_TS_EN(PTP_TS_EN),
|
||||
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
|
||||
.PTP_TS_W(PTP_TS_W),
|
||||
.BIT_REVERSE(BIT_REVERSE),
|
||||
.DEC_8B10B_EN(DEC_8B10B_EN),
|
||||
.PRBS31_EN(PRBS31_EN),
|
||||
.SERDES_PIPELINE(RX_SERDES_PIPELINE)
|
||||
)
|
||||
rx_inst (
|
||||
.clk(rx_clk),
|
||||
.rst(rx_rst),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(axis_rx_int),
|
||||
|
||||
/*
|
||||
* SERDES interface
|
||||
*/
|
||||
.serdes_rx_data(serdes_rx_data),
|
||||
.serdes_rx_data_k(serdes_rx_data_k),
|
||||
.serdes_rx_data_valid(serdes_rx_data_valid),
|
||||
.serdes_rx_reset_req(serdes_rx_reset_req),
|
||||
|
||||
/*
|
||||
* PTP
|
||||
*/
|
||||
.ptp_ts(rx_ptp_ts_out),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.rx_start_packet(rx_start_packet),
|
||||
.rx_error_count(rx_error_count),
|
||||
.rx_block_lock(rx_block_lock),
|
||||
.rx_high_ber(rx_high_ber),
|
||||
.rx_status(rx_status),
|
||||
.stat_rx_byte(stat_rx_byte),
|
||||
.stat_rx_pkt_len(stat_rx_pkt_len),
|
||||
.stat_rx_pkt_fragment(stat_rx_pkt_fragment),
|
||||
.stat_rx_pkt_jabber(stat_rx_pkt_jabber),
|
||||
.stat_rx_pkt_ucast(stat_rx_pkt_ucast),
|
||||
.stat_rx_pkt_mcast(stat_rx_pkt_mcast),
|
||||
.stat_rx_pkt_bcast(stat_rx_pkt_bcast),
|
||||
.stat_rx_pkt_vlan(stat_rx_pkt_vlan),
|
||||
.stat_rx_pkt_good(stat_rx_pkt_good),
|
||||
.stat_rx_pkt_bad(stat_rx_pkt_bad),
|
||||
.stat_rx_err_oversize(stat_rx_err_oversize),
|
||||
.stat_rx_err_bad_fcs(stat_rx_err_bad_fcs),
|
||||
.stat_rx_err_bad_block(stat_rx_err_bad_block),
|
||||
.stat_rx_err_framing(stat_rx_err_framing),
|
||||
.stat_rx_err_preamble(stat_rx_err_preamble),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
|
||||
.cfg_rx_enable(cfg_rx_enable),
|
||||
.cfg_rx_prbs31_enable(cfg_rx_prbs31_enable)
|
||||
);
|
||||
|
||||
taxi_eth_mac_phy_1g_basex_tx #(
|
||||
.DATA_W(DATA_W),
|
||||
.CTRL_W(CTRL_W),
|
||||
.GBX_IF_EN(TX_GBX_IF_EN),
|
||||
.DIC_EN(DIC_EN),
|
||||
.PTP_TS_EN(PTP_TS_EN),
|
||||
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
|
||||
.PTP_TS_W(PTP_TS_W),
|
||||
.TX_CPL_CTRL_IN_TUSER(MAC_CTRL_EN),
|
||||
.BIT_REVERSE(BIT_REVERSE),
|
||||
.ENC_8B10B_EN(ENC_8B10B_EN),
|
||||
.PRBS31_EN(PRBS31_EN),
|
||||
.SERDES_PIPELINE(TX_SERDES_PIPELINE)
|
||||
)
|
||||
tx_inst (
|
||||
.clk(tx_clk),
|
||||
.rst(tx_rst),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(axis_tx_int),
|
||||
.m_axis_tx_cpl(m_axis_tx_cpl),
|
||||
|
||||
/*
|
||||
* SERDES interface
|
||||
*/
|
||||
.serdes_tx_data(serdes_tx_data),
|
||||
.serdes_tx_data_k(serdes_tx_data_k),
|
||||
.serdes_tx_data_dm(serdes_tx_data_dm),
|
||||
.serdes_tx_data_dv(serdes_tx_data_dv),
|
||||
.serdes_tx_data_valid(serdes_tx_data_valid),
|
||||
.serdes_tx_gbx_req_sync(serdes_tx_gbx_req_sync),
|
||||
.serdes_tx_gbx_req_stall(serdes_tx_gbx_req_stall),
|
||||
.serdes_tx_gbx_sync(serdes_tx_gbx_sync),
|
||||
|
||||
/*
|
||||
* PTP
|
||||
*/
|
||||
.ptp_ts(tx_ptp_ts_out),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_start_packet(tx_start_packet),
|
||||
.stat_tx_byte(stat_tx_byte),
|
||||
.stat_tx_pkt_len(stat_tx_pkt_len),
|
||||
.stat_tx_pkt_ucast(stat_tx_pkt_ucast),
|
||||
.stat_tx_pkt_mcast(stat_tx_pkt_mcast),
|
||||
.stat_tx_pkt_bcast(stat_tx_pkt_bcast),
|
||||
.stat_tx_pkt_vlan(stat_tx_pkt_vlan),
|
||||
.stat_tx_pkt_good(stat_tx_pkt_good),
|
||||
.stat_tx_pkt_bad(stat_tx_pkt_bad),
|
||||
.stat_tx_pad_frame(stat_tx_pad_frame),
|
||||
.stat_tx_err_oversize(stat_tx_err_oversize),
|
||||
.stat_tx_err_user(stat_tx_err_user),
|
||||
.stat_tx_err_underflow(stat_tx_err_underflow),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_tx_pad_en(cfg_tx_pad_en),
|
||||
.cfg_tx_min_pkt_len(cfg_tx_min_pkt_len),
|
||||
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
|
||||
.cfg_tx_ifg(cfg_tx_ifg),
|
||||
.cfg_tx_enable(cfg_tx_enable),
|
||||
.cfg_tx_prbs31_enable(cfg_tx_prbs31_enable)
|
||||
);
|
||||
|
||||
if (STAT_EN) begin : stats
|
||||
|
||||
taxi_eth_mac_stats #(
|
||||
.STAT_TX_LEVEL(STAT_TX_LEVEL),
|
||||
.STAT_RX_LEVEL(STAT_RX_LEVEL),
|
||||
.STAT_ID_BASE(STAT_ID_BASE),
|
||||
.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD),
|
||||
.STAT_STR_EN(STAT_STR_EN),
|
||||
.STAT_PREFIX_STR(STAT_PREFIX_STR),
|
||||
.INC_W(2)
|
||||
)
|
||||
mac_stats_inst (
|
||||
.rx_clk(rx_clk),
|
||||
.rx_rst(rx_rst),
|
||||
.tx_clk(tx_clk),
|
||||
.tx_rst(tx_rst),
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
.stat_clk(stat_clk),
|
||||
.stat_rst(stat_rst),
|
||||
.m_axis_stat(m_axis_stat),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_start_packet(|tx_start_packet),
|
||||
.stat_tx_byte(stat_tx_byte),
|
||||
.stat_tx_pkt_len(stat_tx_pkt_len),
|
||||
.stat_tx_pkt_ucast(stat_tx_pkt_ucast),
|
||||
.stat_tx_pkt_mcast(stat_tx_pkt_mcast),
|
||||
.stat_tx_pkt_bcast(stat_tx_pkt_bcast),
|
||||
.stat_tx_pkt_vlan(stat_tx_pkt_vlan),
|
||||
.stat_tx_pkt_good(stat_tx_pkt_good),
|
||||
.stat_tx_pkt_bad(stat_tx_pkt_bad),
|
||||
.stat_tx_err_oversize(stat_tx_err_oversize),
|
||||
.stat_tx_err_user(stat_tx_err_user),
|
||||
.stat_tx_err_underflow(stat_tx_err_underflow),
|
||||
.rx_start_packet(|rx_start_packet),
|
||||
.stat_rx_byte(stat_rx_byte),
|
||||
.stat_rx_pkt_len(stat_rx_pkt_len),
|
||||
.stat_rx_pkt_fragment(stat_rx_pkt_fragment),
|
||||
.stat_rx_pkt_jabber(stat_rx_pkt_jabber),
|
||||
.stat_rx_pkt_ucast(stat_rx_pkt_ucast),
|
||||
.stat_rx_pkt_mcast(stat_rx_pkt_mcast),
|
||||
.stat_rx_pkt_bcast(stat_rx_pkt_bcast),
|
||||
.stat_rx_pkt_vlan(stat_rx_pkt_vlan),
|
||||
.stat_rx_pkt_good(stat_rx_pkt_good),
|
||||
.stat_rx_pkt_bad(stat_rx_pkt_bad),
|
||||
.stat_rx_err_oversize(stat_rx_err_oversize),
|
||||
.stat_rx_err_bad_fcs(stat_rx_err_bad_fcs),
|
||||
.stat_rx_err_bad_block(stat_rx_err_bad_block),
|
||||
.stat_rx_err_framing(stat_rx_err_framing),
|
||||
.stat_rx_err_preamble(stat_rx_err_preamble),
|
||||
.stat_rx_fifo_drop(stat_rx_fifo_drop),
|
||||
.stat_tx_mcf(stat_tx_mcf),
|
||||
.stat_rx_mcf(stat_rx_mcf),
|
||||
.stat_tx_lfc_pkt(stat_tx_lfc_pkt),
|
||||
.stat_tx_lfc_xon(stat_tx_lfc_xon),
|
||||
.stat_tx_lfc_xoff(stat_tx_lfc_xoff),
|
||||
.stat_tx_lfc_paused(stat_tx_lfc_paused),
|
||||
.stat_tx_pfc_pkt(stat_tx_pfc_pkt),
|
||||
.stat_tx_pfc_xon(stat_tx_pfc_xon),
|
||||
.stat_tx_pfc_xoff(stat_tx_pfc_xoff),
|
||||
.stat_tx_pfc_paused(stat_tx_pfc_paused),
|
||||
.stat_rx_lfc_pkt(stat_rx_lfc_pkt),
|
||||
.stat_rx_lfc_xon(stat_rx_lfc_xon),
|
||||
.stat_rx_lfc_xoff(stat_rx_lfc_xoff),
|
||||
.stat_rx_lfc_paused(stat_rx_lfc_paused),
|
||||
.stat_rx_pfc_pkt(stat_rx_pfc_pkt),
|
||||
.stat_rx_pfc_xon(stat_rx_pfc_xon),
|
||||
.stat_rx_pfc_xoff(stat_rx_pfc_xoff),
|
||||
.stat_rx_pfc_paused(stat_rx_pfc_paused)
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
taxi_axis_null_src
|
||||
null_src_inst (
|
||||
.m_axis(m_axis_stat)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
if (MAC_CTRL_EN) begin : mac_ctrl
|
||||
|
||||
localparam MCF_PARAMS_SIZE = PFC_EN ? 18 : 2;
|
||||
|
||||
wire tx_mcf_valid;
|
||||
wire tx_mcf_ready;
|
||||
wire [47:0] tx_mcf_eth_dst;
|
||||
wire [47:0] tx_mcf_eth_src;
|
||||
wire [15:0] tx_mcf_eth_type;
|
||||
wire [15:0] tx_mcf_opcode;
|
||||
wire [MCF_PARAMS_SIZE*8-1:0] tx_mcf_params;
|
||||
|
||||
wire rx_mcf_valid;
|
||||
wire [47:0] rx_mcf_eth_dst;
|
||||
wire [47:0] rx_mcf_eth_src;
|
||||
wire [15:0] rx_mcf_eth_type;
|
||||
wire [15:0] rx_mcf_opcode;
|
||||
wire [MCF_PARAMS_SIZE*8-1:0] rx_mcf_params;
|
||||
|
||||
// terminate LFC pause requests from RX internally on TX side
|
||||
wire tx_pause_req_int;
|
||||
wire rx_lfc_ack_int;
|
||||
|
||||
wire rx_lfc_req_sync;
|
||||
|
||||
taxi_sync_signal #(
|
||||
.WIDTH(1),
|
||||
.N(2)
|
||||
)
|
||||
rx_lfc_req_sync_inst (
|
||||
.clk(tx_clk),
|
||||
.in(rx_lfc_req),
|
||||
.out(rx_lfc_req_sync)
|
||||
);
|
||||
|
||||
wire tx_pause_ack_sync;
|
||||
|
||||
taxi_sync_signal #(
|
||||
.WIDTH(1),
|
||||
.N(2)
|
||||
)
|
||||
tx_pause_ack_sync_inst (
|
||||
.clk(rx_clk),
|
||||
.in(tx_lfc_pause_en && tx_pause_ack),
|
||||
.out(tx_pause_ack_sync)
|
||||
);
|
||||
|
||||
assign tx_pause_req_int = tx_pause_req || (tx_lfc_pause_en && rx_lfc_req_sync);
|
||||
|
||||
assign rx_lfc_ack_int = rx_lfc_ack || tx_pause_ack_sync;
|
||||
|
||||
taxi_mac_ctrl_tx #(
|
||||
.ID_W(s_axis_tx.ID_W),
|
||||
.DEST_W(s_axis_tx.DEST_W),
|
||||
.USER_W(TX_USER_W_INT),
|
||||
.MCF_PARAMS_SIZE(MCF_PARAMS_SIZE)
|
||||
)
|
||||
mac_ctrl_tx_inst (
|
||||
.clk(tx_clk),
|
||||
.rst(tx_rst),
|
||||
|
||||
/*
|
||||
* AXI stream input
|
||||
*/
|
||||
.s_axis(s_axis_tx),
|
||||
|
||||
/*
|
||||
* AXI stream output
|
||||
*/
|
||||
.m_axis(axis_tx_int),
|
||||
|
||||
/*
|
||||
* MAC control frame interface
|
||||
*/
|
||||
.mcf_valid(tx_mcf_valid),
|
||||
.mcf_ready(tx_mcf_ready),
|
||||
.mcf_eth_dst(tx_mcf_eth_dst),
|
||||
.mcf_eth_src(tx_mcf_eth_src),
|
||||
.mcf_eth_type(tx_mcf_eth_type),
|
||||
.mcf_opcode(tx_mcf_opcode),
|
||||
.mcf_params(tx_mcf_params),
|
||||
.mcf_id('0),
|
||||
.mcf_dest('0),
|
||||
.mcf_user(2'b10),
|
||||
|
||||
/*
|
||||
* Pause interface
|
||||
*/
|
||||
.tx_pause_req(tx_pause_req_int),
|
||||
.tx_pause_ack(tx_pause_ack),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.stat_tx_mcf(stat_tx_mcf)
|
||||
);
|
||||
|
||||
taxi_mac_ctrl_rx #(
|
||||
.USER_W(RX_USER_W),
|
||||
.USE_READY(0),
|
||||
.MCF_PARAMS_SIZE(MCF_PARAMS_SIZE)
|
||||
)
|
||||
mac_ctrl_rx_inst (
|
||||
.clk(rx_clk),
|
||||
.rst(rx_rst),
|
||||
|
||||
/*
|
||||
* AXI stream input
|
||||
*/
|
||||
.s_axis(axis_rx_int),
|
||||
|
||||
/*
|
||||
* AXI stream output
|
||||
*/
|
||||
.m_axis(m_axis_rx),
|
||||
|
||||
/*
|
||||
* MAC control frame interface
|
||||
*/
|
||||
.mcf_valid(rx_mcf_valid),
|
||||
.mcf_eth_dst(rx_mcf_eth_dst),
|
||||
.mcf_eth_src(rx_mcf_eth_src),
|
||||
.mcf_eth_type(rx_mcf_eth_type),
|
||||
.mcf_opcode(rx_mcf_opcode),
|
||||
.mcf_params(rx_mcf_params),
|
||||
.mcf_id(),
|
||||
.mcf_dest(),
|
||||
.mcf_user(),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_mcf_rx_eth_dst_mcast(cfg_mcf_rx_eth_dst_mcast),
|
||||
.cfg_mcf_rx_check_eth_dst_mcast(cfg_mcf_rx_check_eth_dst_mcast),
|
||||
.cfg_mcf_rx_eth_dst_ucast(cfg_mcf_rx_eth_dst_ucast),
|
||||
.cfg_mcf_rx_check_eth_dst_ucast(cfg_mcf_rx_check_eth_dst_ucast),
|
||||
.cfg_mcf_rx_eth_src(cfg_mcf_rx_eth_src),
|
||||
.cfg_mcf_rx_check_eth_src(cfg_mcf_rx_check_eth_src),
|
||||
.cfg_mcf_rx_eth_type(cfg_mcf_rx_eth_type),
|
||||
.cfg_mcf_rx_opcode_lfc(cfg_mcf_rx_opcode_lfc),
|
||||
.cfg_mcf_rx_check_opcode_lfc(cfg_mcf_rx_check_opcode_lfc),
|
||||
.cfg_mcf_rx_opcode_pfc(cfg_mcf_rx_opcode_pfc),
|
||||
.cfg_mcf_rx_check_opcode_pfc(cfg_mcf_rx_check_opcode_pfc && PFC_EN),
|
||||
.cfg_mcf_rx_forward(cfg_mcf_rx_forward),
|
||||
.cfg_mcf_rx_enable(cfg_mcf_rx_enable),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.stat_rx_mcf(stat_rx_mcf)
|
||||
);
|
||||
|
||||
taxi_mac_pause_ctrl_tx #(
|
||||
.MCF_PARAMS_SIZE(MCF_PARAMS_SIZE),
|
||||
.PFC_EN(PFC_EN)
|
||||
)
|
||||
mac_pause_ctrl_tx_inst (
|
||||
.clk(tx_clk),
|
||||
.rst(tx_rst),
|
||||
|
||||
/*
|
||||
* MAC control frame interface
|
||||
*/
|
||||
.mcf_valid(tx_mcf_valid),
|
||||
.mcf_ready(tx_mcf_ready),
|
||||
.mcf_eth_dst(tx_mcf_eth_dst),
|
||||
.mcf_eth_src(tx_mcf_eth_src),
|
||||
.mcf_eth_type(tx_mcf_eth_type),
|
||||
.mcf_opcode(tx_mcf_opcode),
|
||||
.mcf_params(tx_mcf_params),
|
||||
|
||||
/*
|
||||
* Pause (IEEE 802.3 annex 31B)
|
||||
*/
|
||||
.tx_lfc_req(tx_lfc_req),
|
||||
.tx_lfc_resend(tx_lfc_resend),
|
||||
|
||||
/*
|
||||
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D)
|
||||
*/
|
||||
.tx_pfc_req(tx_pfc_req),
|
||||
.tx_pfc_resend(tx_pfc_resend),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_tx_lfc_eth_dst(cfg_tx_lfc_eth_dst),
|
||||
.cfg_tx_lfc_eth_src(cfg_tx_lfc_eth_src),
|
||||
.cfg_tx_lfc_eth_type(cfg_tx_lfc_eth_type),
|
||||
.cfg_tx_lfc_opcode(cfg_tx_lfc_opcode),
|
||||
.cfg_tx_lfc_en(cfg_tx_lfc_en),
|
||||
.cfg_tx_lfc_quanta(cfg_tx_lfc_quanta),
|
||||
.cfg_tx_lfc_refresh(cfg_tx_lfc_refresh),
|
||||
.cfg_tx_pfc_eth_dst(cfg_tx_pfc_eth_dst),
|
||||
.cfg_tx_pfc_eth_src(cfg_tx_pfc_eth_src),
|
||||
.cfg_tx_pfc_eth_type(cfg_tx_pfc_eth_type),
|
||||
.cfg_tx_pfc_opcode(cfg_tx_pfc_opcode),
|
||||
.cfg_tx_pfc_en(cfg_tx_pfc_en),
|
||||
.cfg_tx_pfc_quanta(cfg_tx_pfc_quanta),
|
||||
.cfg_tx_pfc_refresh(cfg_tx_pfc_refresh),
|
||||
.cfg_quanta_step(10'((DATA_W*256)/512)),
|
||||
.cfg_quanta_clk_en(!TX_GBX_IF_EN || serdes_tx_data_valid),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.stat_tx_lfc_pkt(stat_tx_lfc_pkt),
|
||||
.stat_tx_lfc_xon(stat_tx_lfc_xon),
|
||||
.stat_tx_lfc_xoff(stat_tx_lfc_xoff),
|
||||
.stat_tx_lfc_paused(stat_tx_lfc_paused),
|
||||
.stat_tx_pfc_pkt(stat_tx_pfc_pkt),
|
||||
.stat_tx_pfc_xon(stat_tx_pfc_xon),
|
||||
.stat_tx_pfc_xoff(stat_tx_pfc_xoff),
|
||||
.stat_tx_pfc_paused(stat_tx_pfc_paused)
|
||||
);
|
||||
|
||||
taxi_mac_pause_ctrl_rx #(
|
||||
.MCF_PARAMS_SIZE(18),
|
||||
.PFC_EN(PFC_EN)
|
||||
)
|
||||
mac_pause_ctrl_rx_inst (
|
||||
.clk(rx_clk),
|
||||
.rst(rx_rst),
|
||||
|
||||
/*
|
||||
* MAC control frame interface
|
||||
*/
|
||||
.mcf_valid(rx_mcf_valid),
|
||||
.mcf_eth_dst(rx_mcf_eth_dst),
|
||||
.mcf_eth_src(rx_mcf_eth_src),
|
||||
.mcf_eth_type(rx_mcf_eth_type),
|
||||
.mcf_opcode(rx_mcf_opcode),
|
||||
.mcf_params(rx_mcf_params),
|
||||
|
||||
/*
|
||||
* Pause (IEEE 802.3 annex 31B)
|
||||
*/
|
||||
.rx_lfc_en(rx_lfc_en),
|
||||
.rx_lfc_req(rx_lfc_req),
|
||||
.rx_lfc_ack(rx_lfc_ack_int),
|
||||
|
||||
/*
|
||||
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D)
|
||||
*/
|
||||
.rx_pfc_en(rx_pfc_en),
|
||||
.rx_pfc_req(rx_pfc_req),
|
||||
.rx_pfc_ack(rx_pfc_ack),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_rx_lfc_opcode(cfg_rx_lfc_opcode),
|
||||
.cfg_rx_lfc_en(cfg_rx_lfc_en),
|
||||
.cfg_rx_pfc_opcode(cfg_rx_pfc_opcode),
|
||||
.cfg_rx_pfc_en(cfg_rx_pfc_en),
|
||||
.cfg_quanta_step(10'((DATA_W*256)/512)),
|
||||
.cfg_quanta_clk_en(!RX_GBX_IF_EN || serdes_rx_data_valid),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.stat_rx_lfc_pkt(stat_rx_lfc_pkt),
|
||||
.stat_rx_lfc_xon(stat_rx_lfc_xon),
|
||||
.stat_rx_lfc_xoff(stat_rx_lfc_xoff),
|
||||
.stat_rx_lfc_paused(stat_rx_lfc_paused),
|
||||
.stat_rx_pfc_pkt(stat_rx_pfc_pkt),
|
||||
.stat_rx_pfc_xon(stat_rx_pfc_xon),
|
||||
.stat_rx_pfc_xoff(stat_rx_pfc_xoff),
|
||||
.stat_rx_pfc_paused(stat_rx_pfc_paused)
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
taxi_axis_tie
|
||||
tx_tie_inst (
|
||||
.s_axis(s_axis_tx),
|
||||
.m_axis(axis_tx_int)
|
||||
);
|
||||
|
||||
taxi_axis_tie
|
||||
rx_tie_inst (
|
||||
.s_axis(axis_rx_int),
|
||||
.m_axis(m_axis_rx)
|
||||
);
|
||||
|
||||
assign rx_lfc_req = '0;
|
||||
assign rx_pfc_req = '0;
|
||||
assign tx_pause_ack = '0;
|
||||
|
||||
assign stat_tx_mcf = '0;
|
||||
assign stat_rx_mcf = '0;
|
||||
assign stat_tx_lfc_pkt = '0;
|
||||
assign stat_tx_lfc_xon = '0;
|
||||
assign stat_tx_lfc_xoff = '0;
|
||||
assign stat_tx_lfc_paused = '0;
|
||||
assign stat_tx_pfc_pkt = '0;
|
||||
assign stat_tx_pfc_xon = '0;
|
||||
assign stat_tx_pfc_xoff = '0;
|
||||
assign stat_tx_pfc_paused = '0;
|
||||
assign stat_rx_lfc_pkt = '0;
|
||||
assign stat_rx_lfc_xon = '0;
|
||||
assign stat_rx_lfc_xoff = '0;
|
||||
assign stat_rx_lfc_paused = '0;
|
||||
assign stat_rx_pfc_pkt = '0;
|
||||
assign stat_rx_pfc_xon = '0;
|
||||
assign stat_rx_pfc_xoff = '0;
|
||||
assign stat_rx_pfc_paused = '0;
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
4
src/eth/rtl/taxi_eth_mac_phy_1g_basex_fifo.f
Normal file
4
src/eth/rtl/taxi_eth_mac_phy_1g_basex_fifo.f
Normal file
@@ -0,0 +1,4 @@
|
||||
taxi_eth_mac_phy_1g_basex_fifo.sv
|
||||
taxi_eth_mac_phy_1g_basex.f
|
||||
../lib/taxi/src/ptp/rtl/taxi_ptp_clock_cdc.sv
|
||||
../lib/taxi/src/axis/rtl/taxi_axis_async_fifo_adapter.f
|
||||
642
src/eth/rtl/taxi_eth_mac_phy_1g_basex_fifo.sv
Normal file
642
src/eth/rtl/taxi_eth_mac_phy_1g_basex_fifo.sv
Normal file
@@ -0,0 +1,642 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2026 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* 1000BASE-X Ethernet MAC/PHY combination with TX and RX FIFOs
|
||||
*/
|
||||
module taxi_eth_mac_phy_1g_basex_fifo #
|
||||
(
|
||||
parameter DATA_W = 16,
|
||||
parameter CTRL_W = (DATA_W/8),
|
||||
parameter logic TX_GBX_IF_EN = 1'b0,
|
||||
parameter logic RX_GBX_IF_EN = TX_GBX_IF_EN,
|
||||
parameter logic DIC_EN = 1'b1,
|
||||
parameter logic PTP_TS_EN = 1'b0,
|
||||
parameter logic PTP_TD_EN = PTP_TS_EN,
|
||||
parameter logic PTP_TS_FMT_TOD = 1'b1,
|
||||
parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64,
|
||||
parameter PTP_TD_SDI_PIPELINE = 2,
|
||||
parameter logic BIT_REVERSE = 1'b0,
|
||||
parameter logic ENC_8B10B_EN = 1'b0,
|
||||
parameter logic DEC_8B10B_EN = ENC_8B10B_EN,
|
||||
parameter logic PRBS31_EN = 1'b0,
|
||||
parameter TX_SERDES_PIPELINE = 0,
|
||||
parameter RX_SERDES_PIPELINE = 0,
|
||||
parameter logic STAT_EN = 1'b0,
|
||||
parameter STAT_TX_LEVEL = 1,
|
||||
parameter STAT_RX_LEVEL = 1,
|
||||
parameter STAT_ID_BASE = 0,
|
||||
parameter STAT_UPDATE_PERIOD = 1024,
|
||||
parameter logic STAT_STR_EN = 1'b0,
|
||||
parameter logic [8*8-1:0] STAT_PREFIX_STR = "MAC",
|
||||
parameter TX_FIFO_DEPTH = 4096,
|
||||
parameter TX_FIFO_RAM_PIPELINE = 1,
|
||||
parameter logic TX_FRAME_FIFO = 1'b1,
|
||||
parameter logic TX_DROP_OVERSIZE_FRAME = TX_FRAME_FIFO,
|
||||
parameter logic TX_DROP_BAD_FRAME = TX_DROP_OVERSIZE_FRAME,
|
||||
parameter logic TX_DROP_WHEN_FULL = 1'b0,
|
||||
parameter TX_CPL_FIFO_DEPTH = 64,
|
||||
parameter RX_FIFO_DEPTH = 4096,
|
||||
parameter RX_FIFO_RAM_PIPELINE = 1,
|
||||
parameter logic RX_FRAME_FIFO = 1'b1,
|
||||
parameter logic RX_DROP_OVERSIZE_FRAME = RX_FRAME_FIFO,
|
||||
parameter logic RX_DROP_BAD_FRAME = RX_DROP_OVERSIZE_FRAME,
|
||||
parameter logic RX_DROP_WHEN_FULL = RX_DROP_OVERSIZE_FRAME
|
||||
)
|
||||
(
|
||||
input wire logic rx_clk,
|
||||
input wire logic rx_rst,
|
||||
input wire logic tx_clk,
|
||||
input wire logic tx_rst,
|
||||
input wire logic logic_clk,
|
||||
input wire logic logic_rst,
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
taxi_axis_if.snk s_axis_tx,
|
||||
taxi_axis_if.src m_axis_tx_cpl,
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
taxi_axis_if.src m_axis_rx,
|
||||
|
||||
/*
|
||||
* SERDES interface
|
||||
*/
|
||||
output wire logic [DATA_W-1:0] serdes_tx_data,
|
||||
output wire logic [CTRL_W-1:0] serdes_tx_data_k,
|
||||
output wire logic [CTRL_W-1:0] serdes_tx_data_dm,
|
||||
output wire logic [CTRL_W-1:0] serdes_tx_data_dv,
|
||||
output wire logic serdes_tx_data_valid,
|
||||
input wire logic serdes_tx_gbx_req_sync = 1'b0,
|
||||
input wire logic serdes_tx_gbx_req_stall = 1'b0,
|
||||
output wire logic serdes_tx_gbx_sync,
|
||||
input wire logic [DATA_W-1:0] serdes_rx_data,
|
||||
input wire logic [CTRL_W-1:0] serdes_rx_data_k,
|
||||
input wire logic serdes_rx_data_valid = 1'b1,
|
||||
output wire logic serdes_rx_reset_req,
|
||||
|
||||
/*
|
||||
* PTP clock
|
||||
*/
|
||||
input wire logic ptp_clk = 1'b0,
|
||||
input wire logic ptp_rst = 1'b0,
|
||||
input wire logic ptp_sample_clk = 1'b0,
|
||||
input wire logic ptp_td_sdi = 1'b0,
|
||||
input wire logic [PTP_TS_W-1:0] ptp_ts_in = '0,
|
||||
input wire logic ptp_ts_step_in = 1'b0,
|
||||
output wire logic [PTP_TS_W-1:0] tx_ptp_ts_out,
|
||||
output wire logic tx_ptp_ts_step_out,
|
||||
output wire logic tx_ptp_locked,
|
||||
output wire logic [PTP_TS_W-1:0] rx_ptp_ts_out,
|
||||
output wire logic rx_ptp_ts_step_out,
|
||||
output wire logic rx_ptp_locked,
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
input wire logic stat_clk,
|
||||
input wire logic stat_rst,
|
||||
taxi_axis_if.src m_axis_stat,
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
output wire logic tx_error_underflow,
|
||||
output wire logic tx_fifo_overflow,
|
||||
output wire logic tx_fifo_bad_frame,
|
||||
output wire logic tx_fifo_good_frame,
|
||||
output wire logic rx_error_bad_frame,
|
||||
output wire logic rx_error_bad_fcs,
|
||||
output wire logic rx_bad_block,
|
||||
output wire logic rx_sequence_error,
|
||||
output wire logic rx_block_lock,
|
||||
output wire logic rx_high_ber,
|
||||
output wire logic rx_status,
|
||||
output wire logic rx_fifo_overflow,
|
||||
output wire logic rx_fifo_bad_frame,
|
||||
output wire logic rx_fifo_good_frame,
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
input wire logic cfg_tx_pad_en = 1'b1,
|
||||
input wire logic [7:0] cfg_tx_min_pkt_len = 8'd60-1,
|
||||
input wire logic [15:0] cfg_tx_max_pkt_len = 16'd1518-1,
|
||||
input wire logic [7:0] cfg_tx_ifg = 8'd12,
|
||||
input wire logic cfg_tx_enable = 1'b1,
|
||||
input wire logic [15:0] cfg_rx_max_pkt_len = 16'd1518-1,
|
||||
input wire logic cfg_rx_enable = 1'b1,
|
||||
input wire logic cfg_tx_prbs31_enable = 1'b0,
|
||||
input wire logic cfg_rx_prbs31_enable = 1'b0
|
||||
);
|
||||
|
||||
localparam KEEP_W = DATA_W/8;
|
||||
localparam TX_USER_W = 1;
|
||||
localparam RX_USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1;
|
||||
localparam TX_TAG_W = s_axis_tx.ID_W;
|
||||
|
||||
taxi_axis_if #(.DATA_W(DATA_W), .KEEP_W(KEEP_W), .USER_EN(1), .USER_W(TX_USER_W), .ID_EN(1), .ID_W(TX_TAG_W)) axis_tx_int();
|
||||
taxi_axis_if #(.DATA_W(PTP_TS_W), .KEEP_W(1), .ID_EN(1), .ID_W(TX_TAG_W)) axis_tx_cpl_int();
|
||||
taxi_axis_if #(.DATA_W(DATA_W), .KEEP_W(KEEP_W), .USER_EN(1), .USER_W(RX_USER_W)) axis_rx_int();
|
||||
|
||||
// synchronize MAC status signals into logic clock domain
|
||||
wire tx_error_underflow_int;
|
||||
|
||||
logic [0:0] tx_sync_reg_1 = '0;
|
||||
logic [0:0] tx_sync_reg_2 = '0;
|
||||
logic [0:0] tx_sync_reg_3 = '0;
|
||||
logic [0:0] tx_sync_reg_4 = '0;
|
||||
|
||||
assign tx_error_underflow = tx_sync_reg_3[0] ^ tx_sync_reg_4[0];
|
||||
|
||||
always_ff @(posedge tx_clk or posedge tx_rst) begin
|
||||
if (tx_rst) begin
|
||||
tx_sync_reg_1 <= '0;
|
||||
end else begin
|
||||
tx_sync_reg_1 <= tx_sync_reg_1 ^ {tx_error_underflow_int};
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge logic_clk or posedge logic_rst) begin
|
||||
if (logic_rst) begin
|
||||
tx_sync_reg_2 <= '0;
|
||||
tx_sync_reg_3 <= '0;
|
||||
tx_sync_reg_4 <= '0;
|
||||
end else begin
|
||||
tx_sync_reg_2 <= tx_sync_reg_1;
|
||||
tx_sync_reg_3 <= tx_sync_reg_2;
|
||||
tx_sync_reg_4 <= tx_sync_reg_3;
|
||||
end
|
||||
end
|
||||
|
||||
wire rx_error_bad_frame_int;
|
||||
wire rx_error_bad_fcs_int;
|
||||
wire rx_bad_block_int;
|
||||
wire rx_sequence_error_int;
|
||||
wire rx_block_lock_int;
|
||||
wire rx_high_ber_int;
|
||||
wire rx_status_int;
|
||||
|
||||
logic [6:0] rx_sync_reg_1 = '0;
|
||||
logic [6:0] rx_sync_reg_2 = '0;
|
||||
logic [6:0] rx_sync_reg_3 = '0;
|
||||
logic [6:0] rx_sync_reg_4 = '0;
|
||||
|
||||
assign rx_error_bad_frame = rx_sync_reg_3[0] ^ rx_sync_reg_4[0];
|
||||
assign rx_error_bad_fcs = rx_sync_reg_3[1] ^ rx_sync_reg_4[1];
|
||||
assign rx_bad_block = rx_sync_reg_3[2] ^ rx_sync_reg_4[2];
|
||||
assign rx_sequence_error = rx_sync_reg_3[3] ^ rx_sync_reg_4[3];
|
||||
assign rx_block_lock = rx_sync_reg_4[4];
|
||||
assign rx_high_ber = rx_sync_reg_4[5];
|
||||
assign rx_status = rx_sync_reg_4[6];
|
||||
|
||||
always_ff @(posedge rx_clk or posedge rx_rst) begin
|
||||
if (rx_rst) begin
|
||||
rx_sync_reg_1 <= '0;
|
||||
end else begin
|
||||
rx_sync_reg_1[0] <= rx_sync_reg_1[0] ^ rx_error_bad_frame_int;
|
||||
rx_sync_reg_1[1] <= rx_sync_reg_1[1] ^ rx_error_bad_fcs_int;
|
||||
rx_sync_reg_1[2] <= rx_sync_reg_1[2] ^ rx_bad_block_int;
|
||||
rx_sync_reg_1[3] <= rx_sync_reg_1[3] ^ rx_sequence_error_int;
|
||||
rx_sync_reg_1[4] <= rx_block_lock_int;
|
||||
rx_sync_reg_1[5] <= rx_high_ber_int;
|
||||
rx_sync_reg_1[6] <= rx_status_int;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge logic_clk or posedge logic_rst) begin
|
||||
if (logic_rst) begin
|
||||
rx_sync_reg_2 <= '0;
|
||||
rx_sync_reg_3 <= '0;
|
||||
rx_sync_reg_4 <= '0;
|
||||
end else begin
|
||||
rx_sync_reg_2 <= rx_sync_reg_1;
|
||||
rx_sync_reg_3 <= rx_sync_reg_2;
|
||||
rx_sync_reg_4 <= rx_sync_reg_3;
|
||||
end
|
||||
end
|
||||
|
||||
// PTP timestamping
|
||||
wire [PTP_TS_W-1:0] tx_ptp_ts_int;
|
||||
wire tx_ptp_ts_step_int;
|
||||
wire tx_ptp_locked_int;
|
||||
wire [PTP_TS_W-1:0] rx_ptp_ts_int;
|
||||
wire rx_ptp_ts_step_int;
|
||||
wire rx_ptp_locked_int;
|
||||
|
||||
if (PTP_TS_EN && !PTP_TD_EN) begin : ptp
|
||||
|
||||
taxi_ptp_clock_cdc #(
|
||||
.TS_W(PTP_TS_W),
|
||||
.NS_W(6)
|
||||
)
|
||||
tx_ptp_cdc (
|
||||
.input_clk(logic_clk),
|
||||
.input_rst(logic_rst),
|
||||
.output_clk(tx_clk),
|
||||
.output_rst(tx_rst),
|
||||
.sample_clk(ptp_sample_clk),
|
||||
.input_ts(ptp_ts_in),
|
||||
.input_ts_step(ptp_ts_step_in),
|
||||
.output_ts(tx_ptp_ts_int),
|
||||
.output_ts_step(tx_ptp_ts_step_out),
|
||||
.output_pps(),
|
||||
.output_pps_str(),
|
||||
.locked(tx_ptp_locked)
|
||||
);
|
||||
|
||||
taxi_ptp_clock_cdc #(
|
||||
.TS_W(PTP_TS_W),
|
||||
.NS_W(6)
|
||||
)
|
||||
rx_ptp_cdc (
|
||||
.input_clk(logic_clk),
|
||||
.input_rst(logic_rst),
|
||||
.output_clk(rx_clk),
|
||||
.output_rst(rx_rst),
|
||||
.sample_clk(ptp_sample_clk),
|
||||
.input_ts(ptp_ts_in),
|
||||
.input_ts_step(ptp_ts_step_in),
|
||||
.output_ts(rx_ptp_ts_int),
|
||||
.output_ts_step(rx_ptp_ts_step_out),
|
||||
.output_pps(),
|
||||
.output_pps_str(),
|
||||
.locked(rx_ptp_locked)
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign tx_ptp_ts_int = '0;
|
||||
assign tx_ptp_ts_step_out = tx_ptp_ts_step_int;
|
||||
assign rx_ptp_ts_int = '0;
|
||||
assign rx_ptp_ts_step_out = rx_ptp_ts_step_int;
|
||||
|
||||
assign tx_ptp_locked = tx_ptp_locked_int;
|
||||
assign rx_ptp_locked = rx_ptp_locked_int;
|
||||
|
||||
end
|
||||
|
||||
wire stat_rx_fifo_drop;
|
||||
|
||||
taxi_eth_mac_phy_1g_basex #(
|
||||
.DATA_W(DATA_W),
|
||||
.CTRL_W(CTRL_W),
|
||||
.TX_GBX_IF_EN(TX_GBX_IF_EN),
|
||||
.RX_GBX_IF_EN(RX_GBX_IF_EN),
|
||||
.DIC_EN(DIC_EN),
|
||||
.PTP_TS_EN(PTP_TS_EN),
|
||||
.PTP_TD_EN(PTP_TD_EN),
|
||||
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
|
||||
.PTP_TS_W(PTP_TS_W),
|
||||
.PTP_TD_SDI_PIPELINE(PTP_TD_SDI_PIPELINE),
|
||||
.BIT_REVERSE(BIT_REVERSE),
|
||||
.ENC_8B10B_EN(ENC_8B10B_EN),
|
||||
.DEC_8B10B_EN(DEC_8B10B_EN),
|
||||
.PRBS31_EN(PRBS31_EN),
|
||||
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
|
||||
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
|
||||
.STAT_EN(STAT_EN),
|
||||
.STAT_TX_LEVEL(STAT_TX_LEVEL),
|
||||
.STAT_RX_LEVEL(STAT_RX_LEVEL),
|
||||
.STAT_ID_BASE(STAT_ID_BASE),
|
||||
.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD),
|
||||
.STAT_STR_EN(STAT_STR_EN),
|
||||
.STAT_PREFIX_STR(STAT_PREFIX_STR)
|
||||
)
|
||||
mac_phy_inst (
|
||||
.tx_clk(tx_clk),
|
||||
.tx_rst(tx_rst),
|
||||
.rx_clk(rx_clk),
|
||||
.rx_rst(rx_rst),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(axis_tx_int),
|
||||
.m_axis_tx_cpl(axis_tx_cpl_int),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(axis_rx_int),
|
||||
|
||||
/*
|
||||
* Serdes interface
|
||||
*/
|
||||
.serdes_tx_data(serdes_tx_data),
|
||||
.serdes_tx_data_k(serdes_tx_data_k),
|
||||
.serdes_tx_data_dm(serdes_tx_data_dm),
|
||||
.serdes_tx_data_dv(serdes_tx_data_dv),
|
||||
.serdes_tx_data_valid(serdes_tx_data_valid),
|
||||
.serdes_tx_gbx_req_sync(serdes_tx_gbx_req_sync),
|
||||
.serdes_tx_gbx_req_stall(serdes_tx_gbx_req_stall),
|
||||
.serdes_tx_gbx_sync(serdes_tx_gbx_sync),
|
||||
.serdes_rx_data(serdes_rx_data),
|
||||
.serdes_rx_data_k(serdes_rx_data_k),
|
||||
.serdes_rx_data_valid(serdes_rx_data_valid),
|
||||
.serdes_rx_reset_req(serdes_rx_reset_req),
|
||||
|
||||
/*
|
||||
* PTP
|
||||
*/
|
||||
.ptp_clk(ptp_clk),
|
||||
.ptp_rst(ptp_rst),
|
||||
.ptp_sample_clk(ptp_sample_clk),
|
||||
.ptp_td_sdi(ptp_td_sdi),
|
||||
.tx_ptp_ts_in(tx_ptp_ts_int),
|
||||
.tx_ptp_ts_out(tx_ptp_ts_out),
|
||||
.tx_ptp_ts_step_out(tx_ptp_ts_step_int),
|
||||
.tx_ptp_locked(tx_ptp_locked_int),
|
||||
.rx_ptp_ts_in(rx_ptp_ts_int),
|
||||
.rx_ptp_ts_out(rx_ptp_ts_out),
|
||||
.rx_ptp_ts_step_out(rx_ptp_ts_step_int),
|
||||
.rx_ptp_locked(rx_ptp_locked_int),
|
||||
|
||||
/*
|
||||
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
|
||||
*/
|
||||
.tx_lfc_req(0),
|
||||
.tx_lfc_resend(0),
|
||||
.rx_lfc_en(0),
|
||||
.rx_lfc_req(),
|
||||
.rx_lfc_ack(0),
|
||||
|
||||
/*
|
||||
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
|
||||
*/
|
||||
.tx_pfc_req(0),
|
||||
.tx_pfc_resend(0),
|
||||
.rx_pfc_en(0),
|
||||
.rx_pfc_req(),
|
||||
.rx_pfc_ack(0),
|
||||
|
||||
/*
|
||||
* Pause interface
|
||||
*/
|
||||
.tx_lfc_pause_en(0),
|
||||
.tx_pause_req(0),
|
||||
.tx_pause_ack(),
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
.stat_clk(stat_clk),
|
||||
.stat_rst(stat_rst),
|
||||
.m_axis_stat(m_axis_stat),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_start_packet(),
|
||||
.stat_tx_byte(),
|
||||
.stat_tx_pkt_len(),
|
||||
.stat_tx_pkt_ucast(),
|
||||
.stat_tx_pkt_mcast(),
|
||||
.stat_tx_pkt_bcast(),
|
||||
.stat_tx_pkt_vlan(),
|
||||
.stat_tx_pkt_good(),
|
||||
.stat_tx_pkt_bad(),
|
||||
.stat_tx_pad_frame(),
|
||||
.stat_tx_err_oversize(),
|
||||
.stat_tx_err_user(),
|
||||
.stat_tx_err_underflow(tx_error_underflow_int),
|
||||
.rx_start_packet(),
|
||||
.rx_error_count(),
|
||||
.rx_block_lock(rx_block_lock_int),
|
||||
.rx_high_ber(rx_high_ber_int),
|
||||
.rx_status(rx_status_int),
|
||||
.stat_rx_byte(),
|
||||
.stat_rx_pkt_len(),
|
||||
.stat_rx_pkt_fragment(),
|
||||
.stat_rx_pkt_jabber(),
|
||||
.stat_rx_pkt_ucast(),
|
||||
.stat_rx_pkt_mcast(),
|
||||
.stat_rx_pkt_bcast(),
|
||||
.stat_rx_pkt_vlan(),
|
||||
.stat_rx_pkt_good(),
|
||||
.stat_rx_pkt_bad(rx_error_bad_frame_int),
|
||||
.stat_rx_err_oversize(),
|
||||
.stat_rx_err_bad_fcs(rx_error_bad_fcs_int),
|
||||
.stat_rx_err_bad_block(rx_bad_block_int),
|
||||
.stat_rx_err_framing(rx_sequence_error_int),
|
||||
.stat_rx_err_preamble(),
|
||||
.stat_rx_fifo_drop(stat_rx_fifo_drop),
|
||||
.stat_tx_mcf(),
|
||||
.stat_rx_mcf(),
|
||||
.stat_tx_lfc_pkt(),
|
||||
.stat_tx_lfc_xon(),
|
||||
.stat_tx_lfc_xoff(),
|
||||
.stat_tx_lfc_paused(),
|
||||
.stat_tx_pfc_pkt(),
|
||||
.stat_tx_pfc_xon(),
|
||||
.stat_tx_pfc_xoff(),
|
||||
.stat_tx_pfc_paused(),
|
||||
.stat_rx_lfc_pkt(),
|
||||
.stat_rx_lfc_xon(),
|
||||
.stat_rx_lfc_xoff(),
|
||||
.stat_rx_lfc_paused(),
|
||||
.stat_rx_pfc_pkt(),
|
||||
.stat_rx_pfc_xon(),
|
||||
.stat_rx_pfc_xoff(),
|
||||
.stat_rx_pfc_paused(),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_tx_pad_en(cfg_tx_pad_en),
|
||||
.cfg_tx_min_pkt_len(cfg_tx_min_pkt_len),
|
||||
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
|
||||
.cfg_tx_ifg(cfg_tx_ifg),
|
||||
.cfg_tx_enable(cfg_tx_enable),
|
||||
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
|
||||
.cfg_rx_enable(cfg_rx_enable),
|
||||
.cfg_tx_prbs31_enable(cfg_tx_prbs31_enable),
|
||||
.cfg_rx_prbs31_enable(cfg_rx_prbs31_enable),
|
||||
.cfg_mcf_rx_eth_dst_mcast('0),
|
||||
.cfg_mcf_rx_check_eth_dst_mcast('0),
|
||||
.cfg_mcf_rx_eth_dst_ucast('0),
|
||||
.cfg_mcf_rx_check_eth_dst_ucast('0),
|
||||
.cfg_mcf_rx_eth_src('0),
|
||||
.cfg_mcf_rx_check_eth_src('0),
|
||||
.cfg_mcf_rx_eth_type('0),
|
||||
.cfg_mcf_rx_opcode_lfc('0),
|
||||
.cfg_mcf_rx_check_opcode_lfc('0),
|
||||
.cfg_mcf_rx_opcode_pfc('0),
|
||||
.cfg_mcf_rx_check_opcode_pfc('0),
|
||||
.cfg_mcf_rx_forward('0),
|
||||
.cfg_mcf_rx_enable('0),
|
||||
.cfg_tx_lfc_eth_dst('0),
|
||||
.cfg_tx_lfc_eth_src('0),
|
||||
.cfg_tx_lfc_eth_type('0),
|
||||
.cfg_tx_lfc_opcode('0),
|
||||
.cfg_tx_lfc_en('0),
|
||||
.cfg_tx_lfc_quanta('0),
|
||||
.cfg_tx_lfc_refresh('0),
|
||||
.cfg_tx_pfc_eth_dst('0),
|
||||
.cfg_tx_pfc_eth_src('0),
|
||||
.cfg_tx_pfc_eth_type('0),
|
||||
.cfg_tx_pfc_opcode('0),
|
||||
.cfg_tx_pfc_en('0),
|
||||
.cfg_tx_pfc_quanta('{8{'0}}),
|
||||
.cfg_tx_pfc_refresh('{8{'0}}),
|
||||
.cfg_rx_lfc_opcode('0),
|
||||
.cfg_rx_lfc_en('0),
|
||||
.cfg_rx_pfc_opcode('0),
|
||||
.cfg_rx_pfc_en('0)
|
||||
);
|
||||
|
||||
taxi_axis_async_fifo_adapter #(
|
||||
.DEPTH(TX_FIFO_DEPTH),
|
||||
.RAM_PIPELINE(TX_FIFO_RAM_PIPELINE),
|
||||
.FRAME_FIFO(TX_FRAME_FIFO),
|
||||
.USER_BAD_FRAME_VALUE(1'b1),
|
||||
.USER_BAD_FRAME_MASK(1'b1),
|
||||
.DROP_OVERSIZE_FRAME(TX_DROP_OVERSIZE_FRAME),
|
||||
.DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
|
||||
.DROP_WHEN_FULL(TX_DROP_WHEN_FULL)
|
||||
)
|
||||
tx_fifo (
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_clk(logic_clk),
|
||||
.s_rst(logic_rst),
|
||||
.s_axis(s_axis_tx),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_clk(tx_clk),
|
||||
.m_rst(tx_rst),
|
||||
.m_axis(axis_tx_int),
|
||||
|
||||
/*
|
||||
* Pause
|
||||
*/
|
||||
.s_pause_req(1'b0),
|
||||
.s_pause_ack(),
|
||||
.m_pause_req(1'b0),
|
||||
.m_pause_ack(),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.s_status_depth(),
|
||||
.s_status_depth_commit(),
|
||||
.s_status_overflow(tx_fifo_overflow),
|
||||
.s_status_bad_frame(tx_fifo_bad_frame),
|
||||
.s_status_good_frame(tx_fifo_good_frame),
|
||||
.m_status_depth(),
|
||||
.m_status_depth_commit(),
|
||||
.m_status_overflow(),
|
||||
.m_status_bad_frame(),
|
||||
.m_status_good_frame()
|
||||
);
|
||||
|
||||
taxi_axis_async_fifo #(
|
||||
.DEPTH(TX_CPL_FIFO_DEPTH),
|
||||
.FRAME_FIFO(1'b0)
|
||||
)
|
||||
tx_cpl_fifo (
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_clk(tx_clk),
|
||||
.s_rst(tx_rst),
|
||||
.s_axis(axis_tx_cpl_int),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_clk(logic_clk),
|
||||
.m_rst(logic_rst),
|
||||
.m_axis(m_axis_tx_cpl),
|
||||
|
||||
/*
|
||||
* Pause
|
||||
*/
|
||||
.s_pause_req(1'b0),
|
||||
.s_pause_ack(),
|
||||
.m_pause_req(1'b0),
|
||||
.m_pause_ack(),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.s_status_depth(),
|
||||
.s_status_depth_commit(),
|
||||
.s_status_overflow(),
|
||||
.s_status_bad_frame(),
|
||||
.s_status_good_frame(),
|
||||
.m_status_depth(),
|
||||
.m_status_depth_commit(),
|
||||
.m_status_overflow(),
|
||||
.m_status_bad_frame(),
|
||||
.m_status_good_frame()
|
||||
);
|
||||
|
||||
taxi_axis_async_fifo_adapter #(
|
||||
.DEPTH(RX_FIFO_DEPTH),
|
||||
.RAM_PIPELINE(RX_FIFO_RAM_PIPELINE),
|
||||
.FRAME_FIFO(RX_FRAME_FIFO),
|
||||
.USER_BAD_FRAME_VALUE(1'b1),
|
||||
.USER_BAD_FRAME_MASK(1'b1),
|
||||
.DROP_OVERSIZE_FRAME(RX_DROP_OVERSIZE_FRAME),
|
||||
.DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
|
||||
.DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
|
||||
)
|
||||
rx_fifo (
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_clk(rx_clk),
|
||||
.s_rst(rx_rst),
|
||||
.s_axis(axis_rx_int),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_clk(logic_clk),
|
||||
.m_rst(logic_rst),
|
||||
.m_axis(m_axis_rx),
|
||||
|
||||
/*
|
||||
* Pause
|
||||
*/
|
||||
.s_pause_req(1'b0),
|
||||
.s_pause_ack(),
|
||||
.m_pause_req(1'b0),
|
||||
.m_pause_ack(),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.s_status_depth(),
|
||||
.s_status_depth_commit(),
|
||||
.s_status_overflow(stat_rx_fifo_drop),
|
||||
.s_status_bad_frame(),
|
||||
.s_status_good_frame(),
|
||||
.m_status_depth(),
|
||||
.m_status_depth_commit(),
|
||||
.m_status_overflow(rx_fifo_overflow),
|
||||
.m_status_bad_frame(rx_fifo_bad_frame),
|
||||
.m_status_good_frame(rx_fifo_good_frame)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
6
src/eth/rtl/taxi_eth_mac_phy_1g_basex_rx.f
Normal file
6
src/eth/rtl/taxi_eth_mac_phy_1g_basex_rx.f
Normal file
@@ -0,0 +1,6 @@
|
||||
taxi_eth_mac_phy_1g_basex_rx.sv
|
||||
taxi_eth_phy_1g_basex_rx_if.f
|
||||
taxi_axis_basex_rx_8.sv
|
||||
taxi_axis_basex_rx_16.sv
|
||||
../lib/taxi/src/lfsr/rtl/taxi_lfsr.sv
|
||||
../lib/taxi/src/axis/rtl/taxi_axis_if.sv
|
||||
255
src/eth/rtl/taxi_eth_mac_phy_1g_basex_rx.sv
Normal file
255
src/eth/rtl/taxi_eth_mac_phy_1g_basex_rx.sv
Normal file
@@ -0,0 +1,255 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2026 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* 1000BASE-X Ethernet MAC/PHY combination
|
||||
*/
|
||||
module taxi_eth_mac_phy_1g_basex_rx #
|
||||
(
|
||||
parameter DATA_W = 16,
|
||||
parameter CTRL_W = (DATA_W/8),
|
||||
parameter logic GBX_IF_EN = 1'b0,
|
||||
parameter logic PTP_TS_EN = 1'b0,
|
||||
parameter logic PTP_TS_FMT_TOD = 1'b1,
|
||||
parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64,
|
||||
parameter logic BIT_REVERSE = 1'b0,
|
||||
parameter logic DEC_8B10B_EN = 1'b0,
|
||||
parameter logic PRBS31_EN = 1'b0,
|
||||
parameter SERDES_PIPELINE = 0
|
||||
)
|
||||
(
|
||||
input wire logic clk,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
taxi_axis_if.src m_axis_rx,
|
||||
|
||||
/*
|
||||
* SERDES interface
|
||||
*/
|
||||
input wire logic [DATA_W-1:0] serdes_rx_data,
|
||||
input wire logic [CTRL_W-1:0] serdes_rx_data_k,
|
||||
input wire logic serdes_rx_data_valid = 1'b1,
|
||||
output wire logic serdes_rx_reset_req,
|
||||
|
||||
/*
|
||||
* PTP
|
||||
*/
|
||||
input wire logic [PTP_TS_W-1:0] ptp_ts,
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
output wire logic [1:0] rx_start_packet,
|
||||
output wire logic [4:0] rx_error_count,
|
||||
output wire logic rx_block_lock,
|
||||
output wire logic rx_high_ber,
|
||||
output wire logic rx_status,
|
||||
output wire logic [1:0] stat_rx_byte,
|
||||
output wire logic [15:0] stat_rx_pkt_len,
|
||||
output wire logic stat_rx_pkt_fragment,
|
||||
output wire logic stat_rx_pkt_jabber,
|
||||
output wire logic stat_rx_pkt_ucast,
|
||||
output wire logic stat_rx_pkt_mcast,
|
||||
output wire logic stat_rx_pkt_bcast,
|
||||
output wire logic stat_rx_pkt_vlan,
|
||||
output wire logic stat_rx_pkt_good,
|
||||
output wire logic stat_rx_pkt_bad,
|
||||
output wire logic stat_rx_err_oversize,
|
||||
output wire logic stat_rx_err_bad_fcs,
|
||||
output wire logic stat_rx_err_bad_block,
|
||||
output wire logic stat_rx_err_framing,
|
||||
output wire logic stat_rx_err_preamble,
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
input wire logic [15:0] cfg_rx_max_pkt_len = 16'd1518-1,
|
||||
input wire logic cfg_rx_enable,
|
||||
input wire logic cfg_rx_prbs31_enable
|
||||
);
|
||||
|
||||
wire [DATA_W-1:0] encoded_rx_data;
|
||||
wire [CTRL_W-1:0] encoded_rx_data_k;
|
||||
wire encoded_rx_data_valid;
|
||||
|
||||
taxi_eth_phy_1g_basex_rx_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.CTRL_W(CTRL_W),
|
||||
.GBX_IF_EN(GBX_IF_EN),
|
||||
.BIT_REVERSE(BIT_REVERSE),
|
||||
.DEC_8B10B_EN(DEC_8B10B_EN),
|
||||
.PRBS31_EN(PRBS31_EN),
|
||||
.SERDES_PIPELINE(SERDES_PIPELINE)
|
||||
)
|
||||
rx_if_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* 1000BASE-X encoded interface
|
||||
*/
|
||||
.encoded_rx_data(encoded_rx_data),
|
||||
.encoded_rx_data_k(encoded_rx_data_k),
|
||||
.encoded_rx_data_valid(encoded_rx_data_valid),
|
||||
|
||||
/*
|
||||
* SERDES interface
|
||||
*/
|
||||
.serdes_rx_data(serdes_rx_data),
|
||||
.serdes_rx_data_k(serdes_rx_data_k),
|
||||
.serdes_rx_data_valid(serdes_rx_data_valid),
|
||||
.serdes_rx_reset_req(serdes_rx_reset_req),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.rx_bad_block(stat_rx_err_bad_block),
|
||||
.rx_sequence_error(stat_rx_err_framing),
|
||||
.rx_error_count(rx_error_count),
|
||||
.rx_block_lock(rx_block_lock),
|
||||
.rx_high_ber(rx_high_ber),
|
||||
.rx_status(rx_status),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_rx_prbs31_enable(cfg_rx_prbs31_enable)
|
||||
);
|
||||
|
||||
if (DATA_W == 16) begin
|
||||
|
||||
taxi_axis_basex_rx_16 #(
|
||||
.DATA_W(DATA_W),
|
||||
.CTRL_W(CTRL_W),
|
||||
.GBX_IF_EN(GBX_IF_EN),
|
||||
.PTP_TS_EN(PTP_TS_EN),
|
||||
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
|
||||
.PTP_TS_W(PTP_TS_W)
|
||||
)
|
||||
rx_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* 1000BASE-X encoded input
|
||||
*/
|
||||
.encoded_rx_data(encoded_rx_data),
|
||||
.encoded_rx_data_k(encoded_rx_data_k),
|
||||
.encoded_rx_data_valid(encoded_rx_data_valid),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(m_axis_rx),
|
||||
|
||||
/*
|
||||
* PTP
|
||||
*/
|
||||
.ptp_ts(ptp_ts),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
|
||||
.cfg_rx_enable(cfg_rx_enable),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.rx_start_packet(rx_start_packet),
|
||||
.stat_rx_byte(stat_rx_byte),
|
||||
.stat_rx_pkt_len(stat_rx_pkt_len),
|
||||
.stat_rx_pkt_fragment(stat_rx_pkt_fragment),
|
||||
.stat_rx_pkt_jabber(stat_rx_pkt_jabber),
|
||||
.stat_rx_pkt_ucast(stat_rx_pkt_ucast),
|
||||
.stat_rx_pkt_mcast(stat_rx_pkt_mcast),
|
||||
.stat_rx_pkt_bcast(stat_rx_pkt_bcast),
|
||||
.stat_rx_pkt_vlan(stat_rx_pkt_vlan),
|
||||
.stat_rx_pkt_good(stat_rx_pkt_good),
|
||||
.stat_rx_pkt_bad(stat_rx_pkt_bad),
|
||||
.stat_rx_err_oversize(stat_rx_err_oversize),
|
||||
.stat_rx_err_bad_fcs(stat_rx_err_bad_fcs),
|
||||
.stat_rx_err_bad_block(stat_rx_err_bad_block),
|
||||
.stat_rx_err_framing(stat_rx_err_framing),
|
||||
.stat_rx_err_preamble(stat_rx_err_preamble)
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
taxi_axis_basex_rx_8 #(
|
||||
.DATA_W(DATA_W),
|
||||
.CTRL_W(CTRL_W),
|
||||
.GBX_IF_EN(GBX_IF_EN),
|
||||
.PTP_TS_EN(PTP_TS_EN),
|
||||
.PTP_TS_W(PTP_TS_W)
|
||||
)
|
||||
rx_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* 1000BASE-X encoded input
|
||||
*/
|
||||
.encoded_rx_data(encoded_rx_data),
|
||||
.encoded_rx_data_k(encoded_rx_data_k),
|
||||
.encoded_rx_data_valid(encoded_rx_data_valid),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(m_axis_rx),
|
||||
|
||||
/*
|
||||
* PTP
|
||||
*/
|
||||
.ptp_ts(ptp_ts),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
|
||||
.cfg_rx_enable(cfg_rx_enable),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.rx_start_packet(rx_start_packet[0]),
|
||||
.stat_rx_byte(stat_rx_byte[0]),
|
||||
.stat_rx_pkt_len(stat_rx_pkt_len),
|
||||
.stat_rx_pkt_fragment(stat_rx_pkt_fragment),
|
||||
.stat_rx_pkt_jabber(stat_rx_pkt_jabber),
|
||||
.stat_rx_pkt_ucast(stat_rx_pkt_ucast),
|
||||
.stat_rx_pkt_mcast(stat_rx_pkt_mcast),
|
||||
.stat_rx_pkt_bcast(stat_rx_pkt_bcast),
|
||||
.stat_rx_pkt_vlan(stat_rx_pkt_vlan),
|
||||
.stat_rx_pkt_good(stat_rx_pkt_good),
|
||||
.stat_rx_pkt_bad(stat_rx_pkt_bad),
|
||||
.stat_rx_err_oversize(stat_rx_err_oversize),
|
||||
.stat_rx_err_bad_fcs(stat_rx_err_bad_fcs),
|
||||
.stat_rx_err_bad_block(stat_rx_err_bad_block),
|
||||
.stat_rx_err_framing(stat_rx_err_framing),
|
||||
.stat_rx_err_preamble(stat_rx_err_preamble)
|
||||
);
|
||||
|
||||
assign rx_start_packet[1] = 1'b0;
|
||||
assign stat_rx_byte[1] = 1'b0;
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
7
src/eth/rtl/taxi_eth_mac_phy_1g_basex_tx.f
Normal file
7
src/eth/rtl/taxi_eth_mac_phy_1g_basex_tx.f
Normal file
@@ -0,0 +1,7 @@
|
||||
taxi_eth_mac_phy_1g_basex_tx.sv
|
||||
taxi_eth_phy_1g_basex_tx_if.f
|
||||
taxi_axis_basex_tx_8.sv
|
||||
taxi_axis_basex_tx_16.sv
|
||||
../lib/taxi/src/lfsr/rtl/taxi_lfsr.sv
|
||||
../lib/taxi/src/axis/rtl/taxi_axis_if.sv
|
||||
../lib/taxi/src/axis/rtl/taxi_axis_pad.sv
|
||||
314
src/eth/rtl/taxi_eth_mac_phy_1g_basex_tx.sv
Normal file
314
src/eth/rtl/taxi_eth_mac_phy_1g_basex_tx.sv
Normal file
@@ -0,0 +1,314 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2026 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* 1000BASE-X Ethernet MAC/PHY combination
|
||||
*/
|
||||
module taxi_eth_mac_phy_1g_basex_tx #
|
||||
(
|
||||
parameter DATA_W = 16,
|
||||
parameter CTRL_W = (DATA_W/8),
|
||||
parameter logic GBX_IF_EN = 1'b0,
|
||||
parameter logic DIC_EN = 1'b1,
|
||||
parameter logic PTP_TS_EN = 1'b0,
|
||||
parameter logic PTP_TS_FMT_TOD = 1'b1,
|
||||
parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64,
|
||||
parameter logic TX_CPL_CTRL_IN_TUSER = 1'b0,
|
||||
parameter logic BIT_REVERSE = 1'b0,
|
||||
parameter logic ENC_8B10B_EN = 1'b0,
|
||||
parameter logic PRBS31_EN = 1'b0,
|
||||
parameter SERDES_PIPELINE = 0
|
||||
)
|
||||
(
|
||||
input wire logic clk,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
taxi_axis_if.snk s_axis_tx,
|
||||
taxi_axis_if.src m_axis_tx_cpl,
|
||||
|
||||
/*
|
||||
* SERDES interface
|
||||
*/
|
||||
output wire logic [DATA_W-1:0] serdes_tx_data,
|
||||
output wire logic [CTRL_W-1:0] serdes_tx_data_k,
|
||||
output wire logic [CTRL_W-1:0] serdes_tx_data_dm,
|
||||
output wire logic [CTRL_W-1:0] serdes_tx_data_dv,
|
||||
output wire logic serdes_tx_data_valid,
|
||||
input wire logic serdes_tx_gbx_req_sync = 1'b0,
|
||||
input wire logic serdes_tx_gbx_req_stall = 1'b0,
|
||||
output wire logic serdes_tx_gbx_sync,
|
||||
|
||||
/*
|
||||
* PTP
|
||||
*/
|
||||
input wire logic [PTP_TS_W-1:0] ptp_ts,
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
output wire logic [1:0] tx_start_packet,
|
||||
output wire logic [1:0] stat_tx_byte,
|
||||
output wire logic [15:0] stat_tx_pkt_len,
|
||||
output wire logic stat_tx_pkt_ucast,
|
||||
output wire logic stat_tx_pkt_mcast,
|
||||
output wire logic stat_tx_pkt_bcast,
|
||||
output wire logic stat_tx_pkt_vlan,
|
||||
output wire logic stat_tx_pkt_good,
|
||||
output wire logic stat_tx_pkt_bad,
|
||||
output wire logic stat_tx_pad_frame,
|
||||
output wire logic stat_tx_err_oversize,
|
||||
output wire logic stat_tx_err_user,
|
||||
output wire logic stat_tx_err_underflow,
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
input wire logic cfg_tx_pad_en = 1'b1,
|
||||
input wire logic [7:0] cfg_tx_min_pkt_len = 8'd60-1,
|
||||
input wire logic [15:0] cfg_tx_max_pkt_len = 16'd1518-1,
|
||||
input wire logic [7:0] cfg_tx_ifg = 8'd12,
|
||||
input wire logic cfg_tx_enable,
|
||||
input wire logic cfg_tx_prbs31_enable
|
||||
);
|
||||
|
||||
localparam TX_USER_W = s_axis_tx.USER_W;
|
||||
localparam TX_TAG_W = s_axis_tx.ID_W;
|
||||
|
||||
wire [DATA_W-1:0] encoded_tx_data;
|
||||
wire [CTRL_W-1:0] encoded_tx_data_k;
|
||||
wire [CTRL_W-1:0] encoded_tx_data_dm;
|
||||
wire [CTRL_W-1:0] encoded_tx_data_dv;
|
||||
wire encoded_tx_data_valid;
|
||||
|
||||
wire tx_gbx_req_sync;
|
||||
wire tx_gbx_req_stall;
|
||||
wire tx_gbx_sync;
|
||||
|
||||
taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(TX_USER_W), .ID_EN(1), .ID_W(TX_TAG_W)) axis_tx_pad();
|
||||
|
||||
taxi_axis_pad #(
|
||||
.ID_PAD_REG_EN(1'b0),
|
||||
.DEST_PAD_REG_EN(1'b0),
|
||||
.USER_PAD_REG_EN(1'b1),
|
||||
.MIN_LEN_W(8),
|
||||
.UNDERFLOW_DROP_EN(1'b1)
|
||||
)
|
||||
tx_pad_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_axis(s_axis_tx),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(axis_tx_pad),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_pad_en(cfg_tx_pad_en),
|
||||
.cfg_min_pkt_len(cfg_tx_min_pkt_len),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.stat_pad_frame(stat_tx_pad_frame),
|
||||
.stat_err_user(),
|
||||
.stat_err_underflow(stat_tx_err_underflow)
|
||||
);
|
||||
|
||||
if (DATA_W == 16) begin
|
||||
|
||||
taxi_axis_basex_tx_16 #(
|
||||
.DATA_W(DATA_W),
|
||||
.CTRL_W(CTRL_W),
|
||||
.GBX_IF_EN(GBX_IF_EN),
|
||||
.GBX_CNT(1),
|
||||
.DIC_EN(DIC_EN),
|
||||
.PTP_TS_EN(PTP_TS_EN),
|
||||
.PTP_TS_W(PTP_TS_W),
|
||||
.TX_CPL_CTRL_IN_TUSER(TX_CPL_CTRL_IN_TUSER)
|
||||
)
|
||||
tx_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(axis_tx_pad),
|
||||
.m_axis_tx_cpl(m_axis_tx_cpl),
|
||||
|
||||
/*
|
||||
* 1000BASE-X encoded interface
|
||||
*/
|
||||
.encoded_tx_data(encoded_tx_data),
|
||||
.encoded_tx_data_k(encoded_tx_data_k),
|
||||
.encoded_tx_data_dm(encoded_tx_data_dm),
|
||||
.encoded_tx_data_dv(encoded_tx_data_dv),
|
||||
.encoded_tx_data_valid(encoded_tx_data_valid),
|
||||
.tx_gbx_req_sync(tx_gbx_req_sync),
|
||||
.tx_gbx_req_stall(tx_gbx_req_stall),
|
||||
.tx_gbx_sync(tx_gbx_sync),
|
||||
|
||||
/*
|
||||
* PTP
|
||||
*/
|
||||
.ptp_ts(ptp_ts),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
|
||||
.cfg_tx_ifg(cfg_tx_ifg),
|
||||
.cfg_tx_enable(cfg_tx_enable),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_start_packet(tx_start_packet),
|
||||
.stat_tx_byte(stat_tx_byte),
|
||||
.stat_tx_pkt_len(stat_tx_pkt_len),
|
||||
.stat_tx_pkt_ucast(stat_tx_pkt_ucast),
|
||||
.stat_tx_pkt_mcast(stat_tx_pkt_mcast),
|
||||
.stat_tx_pkt_bcast(stat_tx_pkt_bcast),
|
||||
.stat_tx_pkt_vlan(stat_tx_pkt_vlan),
|
||||
.stat_tx_pkt_good(stat_tx_pkt_good),
|
||||
.stat_tx_pkt_bad(stat_tx_pkt_bad),
|
||||
.stat_tx_err_oversize(stat_tx_err_oversize),
|
||||
.stat_tx_err_user(stat_tx_err_user),
|
||||
.stat_tx_err_underflow()
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
taxi_axis_basex_tx_8 #(
|
||||
.DATA_W(DATA_W),
|
||||
.CTRL_W(CTRL_W),
|
||||
.GBX_IF_EN(GBX_IF_EN),
|
||||
.GBX_CNT(1),
|
||||
.DIC_EN(DIC_EN),
|
||||
.PTP_TS_EN(PTP_TS_EN),
|
||||
.PTP_TS_W(PTP_TS_W),
|
||||
.TX_CPL_CTRL_IN_TUSER(TX_CPL_CTRL_IN_TUSER)
|
||||
)
|
||||
tx_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(axis_tx_pad),
|
||||
.m_axis_tx_cpl(m_axis_tx_cpl),
|
||||
|
||||
/*
|
||||
* 1000BASE-X encoded interface
|
||||
*/
|
||||
.encoded_tx_data(encoded_tx_data),
|
||||
.encoded_tx_data_k(encoded_tx_data_k),
|
||||
.encoded_tx_data_dm(encoded_tx_data_dm),
|
||||
.encoded_tx_data_dv(encoded_tx_data_dv),
|
||||
.encoded_tx_data_valid(encoded_tx_data_valid),
|
||||
.tx_gbx_req_sync(tx_gbx_req_sync),
|
||||
.tx_gbx_req_stall(tx_gbx_req_stall),
|
||||
.tx_gbx_sync(tx_gbx_sync),
|
||||
|
||||
/*
|
||||
* PTP
|
||||
*/
|
||||
.ptp_ts(ptp_ts),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
|
||||
.cfg_tx_ifg(cfg_tx_ifg),
|
||||
.cfg_tx_enable(cfg_tx_enable),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_start_packet(tx_start_packet[0]),
|
||||
.stat_tx_byte(stat_tx_byte[0]),
|
||||
.stat_tx_pkt_len(stat_tx_pkt_len),
|
||||
.stat_tx_pkt_ucast(stat_tx_pkt_ucast),
|
||||
.stat_tx_pkt_mcast(stat_tx_pkt_mcast),
|
||||
.stat_tx_pkt_bcast(stat_tx_pkt_bcast),
|
||||
.stat_tx_pkt_vlan(stat_tx_pkt_vlan),
|
||||
.stat_tx_pkt_good(stat_tx_pkt_good),
|
||||
.stat_tx_pkt_bad(stat_tx_pkt_bad),
|
||||
.stat_tx_err_oversize(stat_tx_err_oversize),
|
||||
.stat_tx_err_user(stat_tx_err_user),
|
||||
.stat_tx_err_underflow()
|
||||
);
|
||||
|
||||
assign tx_start_packet[1] = 1'b0;
|
||||
assign stat_tx_byte[1] = 1'b0;
|
||||
|
||||
end
|
||||
|
||||
taxi_eth_phy_1g_basex_tx_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.CTRL_W(CTRL_W),
|
||||
.GBX_IF_EN(GBX_IF_EN),
|
||||
.BIT_REVERSE(BIT_REVERSE),
|
||||
.ENC_8B10B_EN(ENC_8B10B_EN),
|
||||
.PRBS31_EN(PRBS31_EN),
|
||||
.SERDES_PIPELINE(SERDES_PIPELINE)
|
||||
)
|
||||
tx_if_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* 1000BASE-X encoded interface
|
||||
*/
|
||||
.encoded_tx_data(encoded_tx_data),
|
||||
.encoded_tx_data_k(encoded_tx_data_k),
|
||||
.encoded_tx_data_dm(encoded_tx_data_dm),
|
||||
.encoded_tx_data_dv(encoded_tx_data_dv),
|
||||
.encoded_tx_data_valid(encoded_tx_data_valid),
|
||||
.tx_gbx_req_sync(tx_gbx_req_sync),
|
||||
.tx_gbx_req_stall(tx_gbx_req_stall),
|
||||
.tx_gbx_sync(tx_gbx_sync),
|
||||
|
||||
/*
|
||||
* SERDES interface
|
||||
*/
|
||||
.serdes_tx_data(serdes_tx_data),
|
||||
.serdes_tx_data_k(serdes_tx_data_k),
|
||||
.serdes_tx_data_dm(serdes_tx_data_dm),
|
||||
.serdes_tx_data_dv(serdes_tx_data_dv),
|
||||
.serdes_tx_data_valid(serdes_tx_data_valid),
|
||||
.serdes_tx_gbx_req_sync(serdes_tx_gbx_req_sync),
|
||||
.serdes_tx_gbx_req_stall(serdes_tx_gbx_req_stall),
|
||||
.serdes_tx_gbx_sync(serdes_tx_gbx_sync),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_tx_prbs31_enable(cfg_tx_prbs31_enable)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
2
src/eth/rtl/taxi_eth_phy_1g_basex_rx_if.f
Normal file
2
src/eth/rtl/taxi_eth_phy_1g_basex_rx_if.f
Normal file
@@ -0,0 +1,2 @@
|
||||
taxi_eth_phy_1g_basex_rx_if.sv
|
||||
../lib/taxi/src/lfsr/rtl/taxi_lfsr.sv
|
||||
194
src/eth/rtl/taxi_eth_phy_1g_basex_rx_if.sv
Normal file
194
src/eth/rtl/taxi_eth_phy_1g_basex_rx_if.sv
Normal file
@@ -0,0 +1,194 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2026 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* 1000BASE-X Ethernet PHY RX IF
|
||||
*/
|
||||
module taxi_eth_phy_1g_basex_rx_if #
|
||||
(
|
||||
parameter DATA_W = 16,
|
||||
parameter CTRL_W = (DATA_W/8),
|
||||
parameter logic GBX_IF_EN = 1'b0,
|
||||
parameter logic BIT_REVERSE = 1'b0,
|
||||
parameter logic DEC_8B10B_EN = 1'b0,
|
||||
parameter logic PRBS31_EN = 1'b0,
|
||||
parameter SERDES_PIPELINE = 0,
|
||||
parameter COUNT_125US = 125000/6.4
|
||||
)
|
||||
(
|
||||
input wire logic clk,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* 10GBASE-R encoded interface
|
||||
*/
|
||||
output wire logic [DATA_W-1:0] encoded_rx_data,
|
||||
output wire logic [CTRL_W-1:0] encoded_rx_data_k,
|
||||
output wire logic encoded_rx_data_valid,
|
||||
|
||||
/*
|
||||
* SERDES interface
|
||||
*/
|
||||
input wire logic [DATA_W-1:0] serdes_rx_data,
|
||||
input wire logic [CTRL_W-1:0] serdes_rx_data_k,
|
||||
input wire logic serdes_rx_data_valid,
|
||||
output wire logic serdes_rx_reset_req,
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
input wire logic rx_bad_block,
|
||||
input wire logic rx_sequence_error,
|
||||
output wire logic [4:0] rx_error_count,
|
||||
output wire logic rx_block_lock,
|
||||
output wire logic rx_high_ber,
|
||||
output wire logic rx_status,
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
input wire logic cfg_rx_prbs31_enable
|
||||
);
|
||||
|
||||
// check configuration
|
||||
if (DATA_W != 8 && DATA_W != 16)
|
||||
$fatal(0, "Error: Interface width must be 8 or 16");
|
||||
|
||||
if (CTRL_W != DATA_W/8)
|
||||
$fatal(0, "Error: CTRL_W must be DATA_W/8");
|
||||
|
||||
wire [DATA_W-1:0] serdes_rx_data_rev, serdes_rx_data_int;
|
||||
wire [CTRL_W-1:0] serdes_rx_data_k_rev, serdes_rx_data_k_int;
|
||||
wire serdes_rx_data_valid_int;
|
||||
|
||||
if (BIT_REVERSE) begin
|
||||
for (genvar n = 0; n < DATA_W; n = n + 1) begin
|
||||
assign serdes_rx_data_rev[n] = serdes_rx_data[DATA_W-n-1];
|
||||
end
|
||||
for (genvar n = 0; n < CTRL_W; n = n + 1) begin
|
||||
assign serdes_rx_data_k_rev[n] = serdes_rx_data_k[CTRL_W-n-1];
|
||||
end
|
||||
end else begin
|
||||
assign serdes_rx_data_rev = serdes_rx_data;
|
||||
assign serdes_rx_data_k_rev = serdes_rx_data_k;
|
||||
end
|
||||
|
||||
if (SERDES_PIPELINE > 0) begin
|
||||
(* srl_style = "register" *)
|
||||
logic [DATA_W-1:0] serdes_rx_data_pipe_reg[SERDES_PIPELINE-1:0] = '{default: '0};
|
||||
(* srl_style = "register" *)
|
||||
logic [CTRL_W-1:0] serdes_rx_data_k_pipe_reg[SERDES_PIPELINE-1:0] = '{default: '0};
|
||||
(* srl_style = "register" *)
|
||||
logic serdes_rx_data_valid_pipe_reg[SERDES_PIPELINE-1:0] = '{default: '0};
|
||||
|
||||
for (genvar n = 0; n < SERDES_PIPELINE; n = n + 1) begin
|
||||
always_ff @(posedge clk) begin
|
||||
serdes_rx_data_pipe_reg[n] <= n == 0 ? serdes_rx_data_rev : serdes_rx_data_pipe_reg[n-1];
|
||||
serdes_rx_data_k_pipe_reg[n] <= n == 0 ? serdes_rx_data_k_rev : serdes_rx_data_k_pipe_reg[n-1];
|
||||
serdes_rx_data_valid_pipe_reg[n] <= n == 0 ? serdes_rx_data_valid : serdes_rx_data_valid_pipe_reg[n-1];
|
||||
end
|
||||
end
|
||||
|
||||
assign serdes_rx_data_int = serdes_rx_data_pipe_reg[SERDES_PIPELINE-1];
|
||||
assign serdes_rx_data_k_int = serdes_rx_data_k_pipe_reg[SERDES_PIPELINE-1];
|
||||
assign serdes_rx_data_valid_int = GBX_IF_EN ? serdes_rx_data_valid_pipe_reg[SERDES_PIPELINE-1] : 1'b1;
|
||||
end else begin
|
||||
assign serdes_rx_data_int = serdes_rx_data_rev;
|
||||
assign serdes_rx_data_k_int = serdes_rx_data_k_rev;
|
||||
assign serdes_rx_data_valid_int = GBX_IF_EN ? serdes_rx_data_valid : 1'b1;
|
||||
end
|
||||
|
||||
logic [DATA_W-1:0] encoded_rx_data_reg = '0;
|
||||
logic [CTRL_W-1:0] encoded_rx_data_k_reg = '0;
|
||||
logic encoded_rx_data_valid_reg = 1'b0;
|
||||
|
||||
logic [30:0] prbs31_state_reg = '1;
|
||||
wire [30:0] prbs31_state;
|
||||
wire [DATA_W-1:0] prbs31_data;
|
||||
logic [DATA_W-1:0] prbs31_data_reg = '0;
|
||||
|
||||
logic [4:0] rx_error_count_reg = '0;
|
||||
logic [3:0] rx_error_count_1_reg = '0;
|
||||
logic [3:0] rx_error_count_2_reg = '0;
|
||||
logic [3:0] rx_error_count_1_temp;
|
||||
logic [3:0] rx_error_count_2_temp;
|
||||
|
||||
taxi_lfsr #(
|
||||
.LFSR_W(31),
|
||||
.LFSR_POLY(31'h10000001),
|
||||
.LFSR_GALOIS(0),
|
||||
.LFSR_FEED_FORWARD(1),
|
||||
.REVERSE(1),
|
||||
.DATA_W(DATA_W),
|
||||
.DATA_IN_EN(1'b1),
|
||||
.DATA_OUT_EN(1'b1)
|
||||
)
|
||||
prbs31_check_inst (
|
||||
.data_in(~serdes_rx_data_int),
|
||||
.state_in(prbs31_state_reg),
|
||||
.data_out(prbs31_data),
|
||||
.state_out(prbs31_state)
|
||||
);
|
||||
|
||||
always_comb begin
|
||||
rx_error_count_1_temp = '0;
|
||||
rx_error_count_2_temp = '0;
|
||||
for (integer i = 0; i < DATA_W; i = i + 1) begin
|
||||
if (i[0]) begin
|
||||
rx_error_count_1_temp = rx_error_count_1_temp + 4'(prbs31_data_reg[i]);
|
||||
end else begin
|
||||
rx_error_count_2_temp = rx_error_count_2_temp + 4'(prbs31_data_reg[i]);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
encoded_rx_data_reg <= serdes_rx_data_int;
|
||||
encoded_rx_data_k_reg <= serdes_rx_data_k_int;
|
||||
encoded_rx_data_valid_reg <= serdes_rx_data_valid_int;
|
||||
|
||||
if (PRBS31_EN) begin
|
||||
if (cfg_rx_prbs31_enable && (!GBX_IF_EN || serdes_rx_data_valid_int)) begin
|
||||
prbs31_state_reg <= prbs31_state;
|
||||
prbs31_data_reg <= prbs31_data;
|
||||
end else begin
|
||||
prbs31_data_reg <= '0;
|
||||
end
|
||||
|
||||
rx_error_count_1_reg <= rx_error_count_1_temp;
|
||||
rx_error_count_2_reg <= rx_error_count_2_temp;
|
||||
rx_error_count_reg <= rx_error_count_1_reg + rx_error_count_2_reg;
|
||||
end else begin
|
||||
rx_error_count_reg <= '0;
|
||||
end
|
||||
end
|
||||
|
||||
assign encoded_rx_data = encoded_rx_data_reg;
|
||||
assign encoded_rx_data_k = encoded_rx_data_k_reg;
|
||||
assign encoded_rx_data_valid = GBX_IF_EN ? encoded_rx_data_valid_reg : 1'b1;
|
||||
|
||||
assign rx_error_count = rx_error_count_reg;
|
||||
|
||||
wire serdes_rx_reset_req_int;
|
||||
assign serdes_rx_reset_req = serdes_rx_reset_req_int && !(PRBS31_EN && cfg_rx_prbs31_enable);
|
||||
|
||||
assign serdes_rx_reset_req_int = 1'b0;
|
||||
|
||||
assign rx_block_lock = 1'b1;
|
||||
assign rx_high_ber = 1'b1;
|
||||
assign rx_status = 1'b1;
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
2
src/eth/rtl/taxi_eth_phy_1g_basex_tx_if.f
Normal file
2
src/eth/rtl/taxi_eth_phy_1g_basex_tx_if.f
Normal file
@@ -0,0 +1,2 @@
|
||||
taxi_eth_phy_1g_basex_tx_if.sv
|
||||
../lib/taxi/src/lfsr/rtl/taxi_lfsr.sv
|
||||
184
src/eth/rtl/taxi_eth_phy_1g_basex_tx_if.sv
Normal file
184
src/eth/rtl/taxi_eth_phy_1g_basex_tx_if.sv
Normal file
@@ -0,0 +1,184 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2026 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* 1000BASE-X Ethernet PHY TX IF
|
||||
*/
|
||||
module taxi_eth_phy_1g_basex_tx_if #
|
||||
(
|
||||
parameter DATA_W = 16,
|
||||
parameter CTRL_W = (DATA_W/8),
|
||||
parameter logic GBX_IF_EN = 1'b0,
|
||||
parameter logic BIT_REVERSE = 1'b0,
|
||||
parameter logic ENC_8B10B_EN = 1'b0,
|
||||
parameter logic PRBS31_EN = 1'b0,
|
||||
parameter SERDES_PIPELINE = 0
|
||||
)
|
||||
(
|
||||
input wire logic clk,
|
||||
input wire logic rst,
|
||||
|
||||
/*
|
||||
* 10GBASE-R encoded interface
|
||||
*/
|
||||
input wire logic [DATA_W-1:0] encoded_tx_data,
|
||||
input wire logic [CTRL_W-1:0] encoded_tx_data_k,
|
||||
input wire logic [CTRL_W-1:0] encoded_tx_data_dm,
|
||||
input wire logic [CTRL_W-1:0] encoded_tx_data_dv,
|
||||
input wire logic encoded_tx_data_valid = 1'b1,
|
||||
output wire logic tx_gbx_req_sync,
|
||||
output wire logic tx_gbx_req_stall,
|
||||
input wire logic tx_gbx_sync = 1'b0,
|
||||
|
||||
/*
|
||||
* SERDES interface
|
||||
*/
|
||||
output wire logic [DATA_W-1:0] serdes_tx_data,
|
||||
output wire logic [CTRL_W-1:0] serdes_tx_data_k,
|
||||
output wire logic [CTRL_W-1:0] serdes_tx_data_dm,
|
||||
output wire logic [CTRL_W-1:0] serdes_tx_data_dv,
|
||||
output wire logic serdes_tx_data_valid,
|
||||
input wire logic serdes_tx_gbx_req_sync = 1'b0,
|
||||
input wire logic serdes_tx_gbx_req_stall = 1'b0,
|
||||
output wire logic serdes_tx_gbx_sync,
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
input wire logic cfg_tx_prbs31_enable
|
||||
);
|
||||
|
||||
// check configuration
|
||||
if (DATA_W != 8 && DATA_W != 16)
|
||||
$fatal(0, "Error: Interface width must be 8 or 16");
|
||||
|
||||
if (CTRL_W != DATA_W/8)
|
||||
$fatal(0, "Error: CTRL_W must be DATA_W/8");
|
||||
|
||||
assign tx_gbx_req_sync = GBX_IF_EN ? serdes_tx_gbx_req_sync : '0;
|
||||
assign tx_gbx_req_stall = GBX_IF_EN ? serdes_tx_gbx_req_stall : '0;
|
||||
|
||||
logic [30:0] prbs31_state_reg = '1;
|
||||
wire [30:0] prbs31_state;
|
||||
wire [DATA_W-1:0] prbs31_data;
|
||||
|
||||
logic [DATA_W-1:0] serdes_tx_data_reg = '0;
|
||||
logic [CTRL_W-1:0] serdes_tx_data_k_reg = '0;
|
||||
logic [CTRL_W-1:0] serdes_tx_data_dm_reg = '0;
|
||||
logic [CTRL_W-1:0] serdes_tx_data_dv_reg = '0;
|
||||
logic serdes_tx_data_valid_reg = 1'b0;
|
||||
logic serdes_tx_gbx_sync_reg = 1'b0;
|
||||
|
||||
wire [DATA_W-1:0] serdes_tx_data_int;
|
||||
wire [CTRL_W-1:0] serdes_tx_data_k_int;
|
||||
wire [CTRL_W-1:0] serdes_tx_data_dm_int;
|
||||
wire [CTRL_W-1:0] serdes_tx_data_dv_int;
|
||||
|
||||
if (BIT_REVERSE) begin
|
||||
for (genvar n = 0; n < DATA_W; n = n + 1) begin
|
||||
assign serdes_tx_data_int[n] = serdes_tx_data_reg[DATA_W-n-1];
|
||||
end
|
||||
for (genvar n = 0; n < CTRL_W; n = n + 1) begin
|
||||
assign serdes_tx_data_k_int[n] = serdes_tx_data_k_reg[CTRL_W-n-1];
|
||||
assign serdes_tx_data_dm_int[n] = serdes_tx_data_dm_reg[CTRL_W-n-1];
|
||||
assign serdes_tx_data_dv_int[n] = serdes_tx_data_dv_reg[CTRL_W-n-1];
|
||||
end
|
||||
end else begin
|
||||
assign serdes_tx_data_int = serdes_tx_data_reg;
|
||||
assign serdes_tx_data_k_int = serdes_tx_data_k_reg;
|
||||
assign serdes_tx_data_dm_int = serdes_tx_data_dm_reg;
|
||||
assign serdes_tx_data_dv_int = serdes_tx_data_dv_reg;
|
||||
end
|
||||
|
||||
if (SERDES_PIPELINE > 0) begin
|
||||
(* srl_style = "register" *)
|
||||
logic [DATA_W-1:0] serdes_tx_data_pipe_reg[SERDES_PIPELINE-1:0] = '{default: '0};
|
||||
(* srl_style = "register" *)
|
||||
logic [CTRL_W-1:0] serdes_tx_data_k_pipe_reg[SERDES_PIPELINE-1:0] = '{default: '0};
|
||||
(* srl_style = "register" *)
|
||||
logic [CTRL_W-1:0] serdes_tx_data_dm_pipe_reg[SERDES_PIPELINE-1:0] = '{default: '0};
|
||||
(* srl_style = "register" *)
|
||||
logic [CTRL_W-1:0] serdes_tx_data_dv_pipe_reg[SERDES_PIPELINE-1:0] = '{default: '0};
|
||||
(* srl_style = "register" *)
|
||||
logic serdes_tx_data_valid_pipe_reg[SERDES_PIPELINE-1:0] = '{default: '0};
|
||||
(* srl_style = "register" *)
|
||||
logic serdes_tx_gbx_sync_pipe_reg[SERDES_PIPELINE-1:0] = '{default: '0};
|
||||
|
||||
for (genvar n = 0; n < SERDES_PIPELINE; n = n + 1) begin
|
||||
always_ff @(posedge clk) begin
|
||||
serdes_tx_data_pipe_reg[n] <= n == 0 ? serdes_tx_data_int : serdes_tx_data_pipe_reg[n-1];
|
||||
serdes_tx_data_k_pipe_reg[n] <= n == 0 ? serdes_tx_data_k_int : serdes_tx_data_k_pipe_reg[n-1];
|
||||
serdes_tx_data_dm_pipe_reg[n] <= n == 0 ? serdes_tx_data_dm_int : serdes_tx_data_dm_pipe_reg[n-1];
|
||||
serdes_tx_data_dv_pipe_reg[n] <= n == 0 ? serdes_tx_data_dv_int : serdes_tx_data_dv_pipe_reg[n-1];
|
||||
serdes_tx_data_valid_pipe_reg[n] <= n == 0 ? serdes_tx_data_valid_reg : serdes_tx_data_valid_pipe_reg[n-1];
|
||||
serdes_tx_gbx_sync_pipe_reg[n] <= n == 0 ? serdes_tx_gbx_sync_reg : serdes_tx_gbx_sync_pipe_reg[n-1];
|
||||
end
|
||||
end
|
||||
|
||||
assign serdes_tx_data = serdes_tx_data_pipe_reg[SERDES_PIPELINE-1];
|
||||
assign serdes_tx_data_k = serdes_tx_data_k_pipe_reg[SERDES_PIPELINE-1];
|
||||
assign serdes_tx_data_dm = serdes_tx_data_dm_pipe_reg[SERDES_PIPELINE-1];
|
||||
assign serdes_tx_data_dv = serdes_tx_data_dv_pipe_reg[SERDES_PIPELINE-1];
|
||||
assign serdes_tx_data_valid = GBX_IF_EN ? serdes_tx_data_valid_pipe_reg[SERDES_PIPELINE-1] : 1'b1;
|
||||
assign serdes_tx_gbx_sync = GBX_IF_EN ? serdes_tx_gbx_sync_pipe_reg[SERDES_PIPELINE-1] : 1'b0;
|
||||
end else begin
|
||||
assign serdes_tx_data = serdes_tx_data_int;
|
||||
assign serdes_tx_data_k = serdes_tx_data_k_int;
|
||||
assign serdes_tx_data_dm = serdes_tx_data_dm_int;
|
||||
assign serdes_tx_data_dv = serdes_tx_data_dv_int;
|
||||
assign serdes_tx_data_valid = GBX_IF_EN ? serdes_tx_data_valid_reg : 1'b1;
|
||||
assign serdes_tx_gbx_sync = GBX_IF_EN ? serdes_tx_gbx_sync_reg : 1'b0;
|
||||
end
|
||||
|
||||
taxi_lfsr #(
|
||||
.LFSR_W(31),
|
||||
.LFSR_POLY(31'h10000001),
|
||||
.LFSR_GALOIS(0),
|
||||
.LFSR_FEED_FORWARD(0),
|
||||
.REVERSE(1),
|
||||
.DATA_W(DATA_W),
|
||||
.DATA_IN_EN(1'b0),
|
||||
.DATA_OUT_EN(1'b1)
|
||||
)
|
||||
prbs31_gen_inst (
|
||||
.data_in('0),
|
||||
.state_in(prbs31_state_reg),
|
||||
.data_out(prbs31_data),
|
||||
.state_out(prbs31_state)
|
||||
);
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (PRBS31_EN && cfg_tx_prbs31_enable) begin
|
||||
if (!GBX_IF_EN || encoded_tx_data_valid) begin
|
||||
prbs31_state_reg <= prbs31_state;
|
||||
end
|
||||
|
||||
serdes_tx_data_reg <= ~prbs31_data;
|
||||
serdes_tx_data_k_reg <= '0;
|
||||
serdes_tx_data_dm_reg <= '0;
|
||||
serdes_tx_data_dv_reg <= '0;
|
||||
end else begin
|
||||
serdes_tx_data_reg <= encoded_tx_data;
|
||||
serdes_tx_data_k_reg <= encoded_tx_data_k;
|
||||
serdes_tx_data_dm_reg <= encoded_tx_data_dm;
|
||||
serdes_tx_data_dv_reg <= encoded_tx_data_dv;
|
||||
end
|
||||
|
||||
serdes_tx_data_valid_reg <= encoded_tx_data_valid;
|
||||
serdes_tx_gbx_sync_reg <= tx_gbx_sync;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
74
src/eth/tb/taxi_eth_mac_phy_1g_basex/Makefile
Normal file
74
src/eth/tb/taxi_eth_mac_phy_1g_basex/Makefile
Normal file
@@ -0,0 +1,74 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2021-2026 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_eth_mac_phy_1g_basex
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_DATA_W := 16
|
||||
export PARAM_TX_GBX_IF_EN := 1
|
||||
export PARAM_RX_GBX_IF_EN := $(PARAM_TX_GBX_IF_EN)
|
||||
export PARAM_DIC_EN := 1
|
||||
export PARAM_PTP_TS_EN := 1
|
||||
export PARAM_PTP_TD_EN := $(PARAM_PTP_TS_EN)
|
||||
export PARAM_PTP_TS_FMT_TOD := 1
|
||||
export PARAM_PTP_TS_W := $(if $(filter-out 1,$(PARAM_PTP_TS_FMT_TOD)),64,96)
|
||||
export PARAM_PTP_TD_SDI_PIPELINE := 2
|
||||
export PARAM_TX_TAG_W := 16
|
||||
export PARAM_BIT_REVERSE := 0
|
||||
export PARAM_ENC_8B10B_EN := 0
|
||||
export PARAM_DEC_8B10B_EN := $(PARAM_ENC_8B10B_EN)
|
||||
export PARAM_PRBS31_EN := 1
|
||||
export PARAM_TX_SERDES_PIPELINE := 2
|
||||
export PARAM_RX_SERDES_PIPELINE := 2
|
||||
export PARAM_PFC_EN := 1
|
||||
export PARAM_PAUSE_EN := $(PARAM_PFC_EN)
|
||||
export PARAM_STAT_EN := 1
|
||||
export PARAM_STAT_TX_LEVEL := 2
|
||||
export PARAM_STAT_RX_LEVEL := $(PARAM_STAT_TX_LEVEL)
|
||||
export PARAM_STAT_ID_BASE := 0
|
||||
export PARAM_STAT_UPDATE_PERIOD := 1024
|
||||
export PARAM_STAT_STR_EN := 1
|
||||
export PARAM_STAT_PREFIX_STR := "\"MAC\""
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
1
src/eth/tb/taxi_eth_mac_phy_1g_basex/basex.py
Symbolic link
1
src/eth/tb/taxi_eth_mac_phy_1g_basex/basex.py
Symbolic link
@@ -0,0 +1 @@
|
||||
../basex.py
|
||||
1
src/eth/tb/taxi_eth_mac_phy_1g_basex/ptp_td.py
Symbolic link
1
src/eth/tb/taxi_eth_mac_phy_1g_basex/ptp_td.py
Symbolic link
@@ -0,0 +1 @@
|
||||
../../lib/taxi/src/ptp/tb/ptp_td.py
|
||||
@@ -0,0 +1,828 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2021-2026 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import struct
|
||||
import sys
|
||||
|
||||
from scapy.layers.l2 import Ether
|
||||
|
||||
import pytest
|
||||
import cocotb_test.simulator
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge
|
||||
from cocotb.utils import get_time_from_sim_steps
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.eth import GmiiFrame, PtpClockSimTime
|
||||
from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame
|
||||
|
||||
try:
|
||||
from basex import BaseXSerdesSource, BaseXSerdesSink
|
||||
from ptp_td import PtpTdSource
|
||||
except ImportError:
|
||||
# attempt import from current directory
|
||||
sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
|
||||
try:
|
||||
from basex import BaseXSerdesSource, BaseXSerdesSink
|
||||
from ptp_td import PtpTdSource
|
||||
finally:
|
||||
del sys.path[0]
|
||||
|
||||
|
||||
class TB:
|
||||
def __init__(self, dut, gbx_cfg=None):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
if len(dut.serdes_tx_data) == 16:
|
||||
if gbx_cfg:
|
||||
self.clk_period = 16
|
||||
else:
|
||||
self.clk_period = 16
|
||||
else:
|
||||
if gbx_cfg:
|
||||
self.clk_period = 8
|
||||
else:
|
||||
self.clk_period = 8
|
||||
|
||||
cocotb.start_soon(Clock(dut.rx_clk, self.clk_period, units="ns").start())
|
||||
cocotb.start_soon(Clock(dut.tx_clk, self.clk_period, units="ns").start())
|
||||
cocotb.start_soon(Clock(dut.stat_clk, self.clk_period, units="ns").start())
|
||||
|
||||
self.serdes_source = BaseXSerdesSource(
|
||||
data=dut.serdes_rx_data,
|
||||
data_k=dut.serdes_rx_data_k,
|
||||
data_valid=dut.serdes_rx_data_valid,
|
||||
clock=dut.rx_clk,
|
||||
enc_8b10b=False,
|
||||
gbx_cfg=gbx_cfg
|
||||
)
|
||||
self.serdes_sink = BaseXSerdesSink(
|
||||
data=dut.serdes_tx_data,
|
||||
data_k=dut.serdes_tx_data_k,
|
||||
data_valid=dut.serdes_tx_data_valid,
|
||||
gbx_req_sync=dut.serdes_tx_gbx_req_sync,
|
||||
gbx_req_stall=dut.serdes_tx_gbx_req_stall,
|
||||
gbx_sync=dut.serdes_tx_gbx_sync,
|
||||
clock=dut.tx_clk,
|
||||
dec_8b10b=False,
|
||||
gbx_cfg=gbx_cfg
|
||||
)
|
||||
|
||||
self.axis_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_tx), dut.tx_clk, dut.tx_rst)
|
||||
self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.tx_clk, dut.tx_rst)
|
||||
self.axis_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.rx_clk, dut.rx_rst)
|
||||
|
||||
self.stat_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_stat), dut.stat_clk, dut.stat_rst)
|
||||
|
||||
self.rx_ptp_clock = PtpClockSimTime(ts_tod=dut.rx_ptp_ts_in, clock=dut.rx_clk)
|
||||
self.tx_ptp_clock = PtpClockSimTime(ts_tod=dut.tx_ptp_ts_in, clock=dut.tx_clk)
|
||||
|
||||
self.ptp_clk_period = self.clk_period
|
||||
|
||||
cocotb.start_soon(Clock(dut.ptp_clk, self.ptp_clk_period, units="ns").start())
|
||||
cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start())
|
||||
|
||||
self.ptp_td_source = PtpTdSource(
|
||||
data=dut.ptp_td_sdi,
|
||||
clock=dut.ptp_clk,
|
||||
reset=dut.ptp_rst,
|
||||
period_ns=self.ptp_clk_period
|
||||
)
|
||||
|
||||
dut.stat_rx_fifo_drop.setimmediatevalue(0)
|
||||
|
||||
dut.cfg_tx_pad_en.setimmediatevalue(0)
|
||||
dut.cfg_tx_min_pkt_len.setimmediatevalue(0)
|
||||
dut.cfg_tx_max_pkt_len.setimmediatevalue(0)
|
||||
dut.cfg_tx_ifg.setimmediatevalue(0)
|
||||
dut.cfg_tx_enable.setimmediatevalue(0)
|
||||
dut.cfg_rx_max_pkt_len.setimmediatevalue(0)
|
||||
dut.cfg_rx_enable.setimmediatevalue(0)
|
||||
dut.cfg_tx_prbs31_enable.setimmediatevalue(0)
|
||||
dut.cfg_rx_prbs31_enable.setimmediatevalue(0)
|
||||
dut.cfg_mcf_rx_eth_dst_mcast.setimmediatevalue(0)
|
||||
dut.cfg_mcf_rx_check_eth_dst_mcast.setimmediatevalue(0)
|
||||
dut.cfg_mcf_rx_eth_dst_ucast.setimmediatevalue(0)
|
||||
dut.cfg_mcf_rx_check_eth_dst_ucast.setimmediatevalue(0)
|
||||
dut.cfg_mcf_rx_eth_src.setimmediatevalue(0)
|
||||
dut.cfg_mcf_rx_check_eth_src.setimmediatevalue(0)
|
||||
dut.cfg_mcf_rx_eth_type.setimmediatevalue(0)
|
||||
dut.cfg_mcf_rx_opcode_lfc.setimmediatevalue(0)
|
||||
dut.cfg_mcf_rx_check_opcode_lfc.setimmediatevalue(0)
|
||||
dut.cfg_mcf_rx_opcode_pfc.setimmediatevalue(0)
|
||||
dut.cfg_mcf_rx_check_opcode_pfc.setimmediatevalue(0)
|
||||
dut.cfg_mcf_rx_forward.setimmediatevalue(0)
|
||||
dut.cfg_mcf_rx_enable.setimmediatevalue(0)
|
||||
dut.cfg_tx_lfc_eth_dst.setimmediatevalue(0)
|
||||
dut.cfg_tx_lfc_eth_src.setimmediatevalue(0)
|
||||
dut.cfg_tx_lfc_eth_type.setimmediatevalue(0)
|
||||
dut.cfg_tx_lfc_opcode.setimmediatevalue(0)
|
||||
dut.cfg_tx_lfc_en.setimmediatevalue(0)
|
||||
dut.cfg_tx_lfc_quanta.setimmediatevalue(0)
|
||||
dut.cfg_tx_lfc_refresh.setimmediatevalue(0)
|
||||
dut.cfg_tx_pfc_eth_dst.setimmediatevalue(0)
|
||||
dut.cfg_tx_pfc_eth_src.setimmediatevalue(0)
|
||||
dut.cfg_tx_pfc_eth_type.setimmediatevalue(0)
|
||||
dut.cfg_tx_pfc_opcode.setimmediatevalue(0)
|
||||
dut.cfg_tx_pfc_en.setimmediatevalue(0)
|
||||
dut.cfg_tx_pfc_quanta.setimmediatevalue([0]*8)
|
||||
dut.cfg_tx_pfc_refresh.setimmediatevalue([0]*8)
|
||||
dut.cfg_rx_lfc_opcode.setimmediatevalue(0)
|
||||
dut.cfg_rx_lfc_en.setimmediatevalue(0)
|
||||
dut.cfg_rx_pfc_opcode.setimmediatevalue(0)
|
||||
dut.cfg_rx_pfc_en.setimmediatevalue(0)
|
||||
|
||||
async def reset(self):
|
||||
self.dut.rx_rst.setimmediatevalue(0)
|
||||
self.dut.tx_rst.setimmediatevalue(0)
|
||||
self.dut.ptp_rst.setimmediatevalue(0)
|
||||
self.dut.stat_rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.rx_clk)
|
||||
await RisingEdge(self.dut.rx_clk)
|
||||
self.dut.rx_rst.value = 1
|
||||
self.dut.tx_rst.value = 1
|
||||
self.dut.ptp_rst.value = 1
|
||||
self.dut.stat_rst.value = 1
|
||||
await RisingEdge(self.dut.rx_clk)
|
||||
await RisingEdge(self.dut.rx_clk)
|
||||
self.dut.rx_rst.value = 0
|
||||
self.dut.tx_rst.value = 0
|
||||
self.dut.ptp_rst.value = 0
|
||||
self.dut.stat_rst.value = 0
|
||||
await RisingEdge(self.dut.rx_clk)
|
||||
await RisingEdge(self.dut.rx_clk)
|
||||
|
||||
self.ptp_td_source.set_ts_tod_sim_time()
|
||||
self.ptp_td_source.set_ts_rel_sim_time()
|
||||
|
||||
|
||||
async def run_test_rx(dut, gbx_cfg=None, payload_lengths=None, payload_data=None, ifg=12):
|
||||
|
||||
if len(dut.serdes_tx_data) == 16:
|
||||
pipe_delay = 3
|
||||
else:
|
||||
pipe_delay = 3
|
||||
|
||||
tb = TB(dut, gbx_cfg)
|
||||
|
||||
tb.serdes_source.ifg = ifg
|
||||
tb.dut.cfg_tx_ifg.value = ifg
|
||||
tb.dut.cfg_rx_max_pkt_len.value = 9218-1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.dut.cfg_rx_enable.value = 0
|
||||
|
||||
tb.log.info("Wait for block lock")
|
||||
while not int(dut.rx_block_lock.value):
|
||||
await RisingEdge(dut.rx_clk)
|
||||
|
||||
if dut.PTP_TD_EN.value:
|
||||
tb.log.info("Wait for PTP CDC lock")
|
||||
while not int(dut.rx_ptp_locked.value):
|
||||
await RisingEdge(dut.rx_clk)
|
||||
for k in range(2000):
|
||||
await RisingEdge(dut.rx_clk)
|
||||
|
||||
tb.dut.cfg_rx_enable.value = 1
|
||||
|
||||
test_frames = [payload_data(x) for x in payload_lengths()]
|
||||
tx_frames = []
|
||||
|
||||
for test_data in test_frames:
|
||||
test_frame = GmiiFrame.from_payload(test_data, tx_complete=tx_frames.append)
|
||||
await tb.serdes_source.send(test_frame)
|
||||
|
||||
for test_data in test_frames:
|
||||
rx_frame = await tb.axis_sink.recv()
|
||||
tx_frame = tx_frames.pop(0)
|
||||
|
||||
frame_error = rx_frame.tuser & 1
|
||||
ptp_ts = rx_frame.tuser >> 1
|
||||
ptp_ts_ns = ptp_ts / 2**16
|
||||
|
||||
print(tx_frame)
|
||||
|
||||
tx_frame_sfd_ns = get_time_from_sim_steps(tx_frame.sim_time_sfd, "ns")
|
||||
|
||||
tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns)
|
||||
tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns)
|
||||
tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns))
|
||||
tb.log.info("Error: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns - tb.clk_period*pipe_delay))
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert frame_error == 0
|
||||
if gbx_cfg is None:
|
||||
if dut.PTP_TD_EN.value:
|
||||
assert abs(ptp_ts_ns - tx_frame_sfd_ns - tb.clk_period*pipe_delay) < tb.clk_period*5
|
||||
else:
|
||||
assert abs(ptp_ts_ns - tx_frame_sfd_ns - tb.clk_period*pipe_delay) < 0.01
|
||||
|
||||
assert tb.axis_sink.empty()
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(dut.rx_clk)
|
||||
|
||||
|
||||
async def run_test_tx(dut, gbx_cfg=None, payload_lengths=None, payload_data=None, ifg=12):
|
||||
|
||||
if len(dut.serdes_tx_data) == 16:
|
||||
pipe_delay = 4
|
||||
else:
|
||||
pipe_delay = 4
|
||||
|
||||
tb = TB(dut, gbx_cfg)
|
||||
|
||||
tb.serdes_source.ifg = ifg
|
||||
tb.dut.cfg_tx_pad_en.value = 1
|
||||
tb.dut.cfg_tx_min_pkt_len.value = 60-1
|
||||
tb.dut.cfg_tx_max_pkt_len.value = 9218-1
|
||||
tb.dut.cfg_tx_ifg.value = ifg
|
||||
|
||||
await tb.reset()
|
||||
|
||||
if dut.PTP_TD_EN.value:
|
||||
tb.log.info("Wait for PTP CDC lock")
|
||||
while not int(dut.tx_ptp_locked.value):
|
||||
await RisingEdge(dut.tx_clk)
|
||||
for k in range(2000):
|
||||
await RisingEdge(dut.tx_clk)
|
||||
else:
|
||||
for k in range(100):
|
||||
await RisingEdge(dut.tx_clk)
|
||||
|
||||
tb.dut.cfg_tx_enable.value = 1
|
||||
tb.serdes_sink.clear()
|
||||
|
||||
test_frames = [payload_data(x) for x in payload_lengths()]
|
||||
|
||||
for test_data in test_frames:
|
||||
await tb.axis_source.send(AxiStreamFrame(test_data, tid=0, tuser=0))
|
||||
|
||||
for test_data in test_frames:
|
||||
rx_frame = await tb.serdes_sink.recv()
|
||||
tx_cpl = await tb.tx_cpl_sink.recv()
|
||||
|
||||
ptp_ts_ns = int(tx_cpl.tdata[0]) / 2**16
|
||||
|
||||
rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
|
||||
|
||||
tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
|
||||
tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
|
||||
tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))
|
||||
tb.log.info("Error: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period*pipe_delay))
|
||||
|
||||
assert rx_frame.get_payload() == test_data
|
||||
assert rx_frame.check_fcs()
|
||||
assert rx_frame.error is None
|
||||
if gbx_cfg is None:
|
||||
if dut.PTP_TD_EN.value:
|
||||
assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period*pipe_delay) < tb.clk_period*5
|
||||
else:
|
||||
assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period*pipe_delay) < 0.01
|
||||
|
||||
assert tb.serdes_sink.empty()
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(dut.tx_clk)
|
||||
|
||||
|
||||
async def run_test_tx_underrun(dut, gbx_cfg=None, ifg=12):
|
||||
|
||||
tb = TB(dut, gbx_cfg)
|
||||
|
||||
tb.serdes_source.ifg = ifg
|
||||
tb.dut.cfg_tx_pad_en.value = 1
|
||||
tb.dut.cfg_tx_min_pkt_len.value = 60-1
|
||||
tb.dut.cfg_tx_max_pkt_len.value = 9218-1
|
||||
tb.dut.cfg_tx_ifg.value = ifg
|
||||
|
||||
await tb.reset()
|
||||
|
||||
for k in range(100):
|
||||
await RisingEdge(dut.tx_clk)
|
||||
|
||||
tb.dut.cfg_tx_enable.value = 1
|
||||
tb.serdes_sink.clear()
|
||||
|
||||
test_data = bytes(x for x in range(60))
|
||||
|
||||
for k in range(3):
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.axis_source.send(test_frame)
|
||||
|
||||
for k in range(64*16 // tb.axis_source.width):
|
||||
await RisingEdge(dut.tx_clk)
|
||||
|
||||
tb.axis_source.pause = True
|
||||
|
||||
for k in range(4):
|
||||
await RisingEdge(dut.tx_clk)
|
||||
|
||||
tb.axis_source.pause = False
|
||||
|
||||
for k in range(3):
|
||||
rx_frame = await tb.serdes_sink.recv()
|
||||
|
||||
if k == 1:
|
||||
assert rx_frame.data[-1] == 0xFE
|
||||
assert rx_frame.error[-1] == 1
|
||||
else:
|
||||
assert rx_frame.get_payload() == test_data
|
||||
assert rx_frame.check_fcs()
|
||||
assert rx_frame.error is None
|
||||
|
||||
assert tb.serdes_sink.empty()
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(dut.tx_clk)
|
||||
|
||||
|
||||
async def run_test_tx_error(dut, gbx_cfg=None, ifg=12):
|
||||
|
||||
tb = TB(dut, gbx_cfg)
|
||||
|
||||
tb.serdes_source.ifg = ifg
|
||||
tb.dut.cfg_tx_pad_en.value = 1
|
||||
tb.dut.cfg_tx_min_pkt_len.value = 60-1
|
||||
tb.dut.cfg_tx_max_pkt_len.value = 9218-1
|
||||
tb.dut.cfg_tx_ifg.value = ifg
|
||||
|
||||
await tb.reset()
|
||||
|
||||
for k in range(100):
|
||||
await RisingEdge(dut.tx_clk)
|
||||
|
||||
tb.dut.cfg_tx_enable.value = 1
|
||||
tb.serdes_sink.clear()
|
||||
|
||||
test_data = bytes(x for x in range(60))
|
||||
|
||||
for k in range(3):
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
if k == 1:
|
||||
test_frame.tuser = 1
|
||||
await tb.axis_source.send(test_frame)
|
||||
|
||||
for k in range(3):
|
||||
rx_frame = await tb.serdes_sink.recv()
|
||||
|
||||
if k == 1:
|
||||
assert rx_frame.data[-1] == 0xFE
|
||||
assert rx_frame.error[-1] == 1
|
||||
else:
|
||||
assert rx_frame.get_payload() == test_data
|
||||
assert rx_frame.check_fcs()
|
||||
assert rx_frame.error is None
|
||||
|
||||
assert tb.serdes_sink.empty()
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(dut.tx_clk)
|
||||
|
||||
|
||||
async def run_test_lfc(dut, gbx_cfg=None, ifg=12):
|
||||
|
||||
tb = TB(dut, gbx_cfg)
|
||||
|
||||
tb.serdes_source.ifg = ifg
|
||||
tb.dut.cfg_tx_pad_en.value = 1
|
||||
tb.dut.cfg_tx_min_pkt_len.value = 60-1
|
||||
tb.dut.cfg_tx_max_pkt_len.value = 9218-1
|
||||
tb.dut.cfg_tx_ifg.value = ifg
|
||||
tb.dut.cfg_rx_max_pkt_len.value = 9218-1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
for k in range(100):
|
||||
await RisingEdge(dut.tx_clk)
|
||||
|
||||
tb.log.info("Wait for block lock")
|
||||
while not int(dut.rx_block_lock.value):
|
||||
await RisingEdge(dut.rx_clk)
|
||||
|
||||
tb.dut.cfg_tx_enable.value = 1
|
||||
tb.dut.cfg_rx_enable.value = 1
|
||||
tb.serdes_sink.clear()
|
||||
|
||||
dut.tx_lfc_req.value = 0
|
||||
dut.tx_lfc_resend.value = 0
|
||||
dut.rx_lfc_en.value = 1
|
||||
dut.rx_lfc_ack.value = 0
|
||||
|
||||
dut.tx_lfc_pause_en.value = 1
|
||||
dut.tx_pause_req.value = 0
|
||||
|
||||
dut.cfg_mcf_rx_eth_dst_mcast.value = 0x0180C2000001
|
||||
dut.cfg_mcf_rx_check_eth_dst_mcast.value = 1
|
||||
dut.cfg_mcf_rx_eth_dst_ucast.value = 0xDAD1D2D3D4D5
|
||||
dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0
|
||||
dut.cfg_mcf_rx_eth_src.value = 0x5A5152535455
|
||||
dut.cfg_mcf_rx_check_eth_src.value = 0
|
||||
dut.cfg_mcf_rx_eth_type.value = 0x8808
|
||||
dut.cfg_mcf_rx_opcode_lfc.value = 0x0001
|
||||
dut.cfg_mcf_rx_check_opcode_lfc.value = 1
|
||||
dut.cfg_mcf_rx_opcode_pfc.value = 0x0101
|
||||
dut.cfg_mcf_rx_check_opcode_pfc.value = 1
|
||||
|
||||
dut.cfg_mcf_rx_forward.value = 0
|
||||
dut.cfg_mcf_rx_enable.value = 1
|
||||
|
||||
dut.cfg_tx_lfc_eth_dst.value = 0x0180C2000001
|
||||
dut.cfg_tx_lfc_eth_src.value = 0x5A5152535455
|
||||
dut.cfg_tx_lfc_eth_type.value = 0x8808
|
||||
dut.cfg_tx_lfc_opcode.value = 0x0001
|
||||
dut.cfg_tx_lfc_en.value = 1
|
||||
dut.cfg_tx_lfc_quanta.value = 0xFFFF
|
||||
dut.cfg_tx_lfc_refresh.value = 0x7F00
|
||||
|
||||
dut.cfg_rx_lfc_opcode.value = 0x0001
|
||||
dut.cfg_rx_lfc_en.value = 1
|
||||
|
||||
test_tx_pkts = []
|
||||
test_rx_pkts = []
|
||||
|
||||
for k in range(32):
|
||||
length = 512
|
||||
payload = bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000)
|
||||
test_pkt = eth / payload
|
||||
test_tx_pkts.append(test_pkt.copy())
|
||||
|
||||
await tb.axis_source.send(bytes(test_pkt))
|
||||
|
||||
eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='5A:51:52:53:54:55', type=0x8000)
|
||||
test_pkt = eth / payload
|
||||
test_rx_pkts.append(test_pkt.copy())
|
||||
|
||||
test_frame = GmiiFrame.from_payload(bytes(test_pkt))
|
||||
await tb.serdes_source.send(test_frame)
|
||||
|
||||
if k == 16:
|
||||
eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808)
|
||||
test_pkt = eth / struct.pack('!HH', 0x0001, 100)
|
||||
test_rx_pkts.append(test_pkt.copy())
|
||||
|
||||
test_frame = GmiiFrame.from_payload(bytes(test_pkt))
|
||||
await tb.serdes_source.send(test_frame)
|
||||
|
||||
for k in range(200):
|
||||
await RisingEdge(dut.tx_clk)
|
||||
|
||||
dut.tx_lfc_req.value = 1
|
||||
|
||||
for k in range(200):
|
||||
await RisingEdge(dut.tx_clk)
|
||||
|
||||
dut.tx_lfc_req.value = 0
|
||||
|
||||
while not int(dut.rx_lfc_req.value):
|
||||
await RisingEdge(dut.tx_clk)
|
||||
|
||||
for k in range(200):
|
||||
await RisingEdge(dut.tx_clk)
|
||||
|
||||
dut.tx_lfc_req.value = 1
|
||||
|
||||
for k in range(200):
|
||||
await RisingEdge(dut.tx_clk)
|
||||
|
||||
dut.tx_lfc_req.value = 0
|
||||
|
||||
while test_rx_pkts:
|
||||
rx_frame = await tb.axis_sink.recv()
|
||||
|
||||
rx_pkt = Ether(bytes(rx_frame))
|
||||
|
||||
tb.log.info("RX packet: %s", repr(rx_pkt))
|
||||
|
||||
if rx_pkt.type == 0x8808:
|
||||
test_pkt = test_rx_pkts.pop(0)
|
||||
# check prefix as frame gets zero-padded
|
||||
assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
|
||||
if isinstance(rx_frame.tuser, list):
|
||||
assert rx_frame.tuser[-1] & 1
|
||||
else:
|
||||
assert rx_frame.tuser & 1
|
||||
else:
|
||||
test_pkt = test_rx_pkts.pop(0)
|
||||
# check prefix as frame gets zero-padded
|
||||
assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
|
||||
if isinstance(rx_frame.tuser, list):
|
||||
assert not rx_frame.tuser[-1] & 1
|
||||
else:
|
||||
assert not rx_frame.tuser & 1
|
||||
|
||||
tx_lfc_cnt = 0
|
||||
|
||||
while test_tx_pkts:
|
||||
tx_frame = await tb.serdes_sink.recv()
|
||||
|
||||
tx_pkt = Ether(bytes(tx_frame.get_payload()))
|
||||
|
||||
tb.log.info("TX packet: %s", repr(tx_pkt))
|
||||
|
||||
if tx_pkt.type == 0x8808:
|
||||
tx_lfc_cnt += 1
|
||||
else:
|
||||
test_pkt = test_tx_pkts.pop(0)
|
||||
# check prefix as frame gets zero-padded
|
||||
assert bytes(tx_pkt).find(bytes(test_pkt)) == 0
|
||||
|
||||
assert tx_lfc_cnt == 4
|
||||
|
||||
assert tb.axis_sink.empty()
|
||||
assert tb.serdes_sink.empty()
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(dut.tx_clk)
|
||||
|
||||
|
||||
async def run_test_pfc(dut, gbx_cfg=None, ifg=12):
|
||||
|
||||
tb = TB(dut, gbx_cfg)
|
||||
|
||||
tb.serdes_source.ifg = ifg
|
||||
tb.dut.cfg_tx_pad_en.value = 1
|
||||
tb.dut.cfg_tx_min_pkt_len.value = 60-1
|
||||
tb.dut.cfg_tx_max_pkt_len.value = 9218-1
|
||||
tb.dut.cfg_tx_ifg.value = ifg
|
||||
tb.dut.cfg_rx_max_pkt_len.value = 9218-1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
for k in range(100):
|
||||
await RisingEdge(dut.tx_clk)
|
||||
|
||||
tb.log.info("Wait for block lock")
|
||||
while not int(dut.rx_block_lock.value):
|
||||
await RisingEdge(dut.rx_clk)
|
||||
|
||||
tb.dut.cfg_tx_enable.value = 1
|
||||
tb.dut.cfg_rx_enable.value = 1
|
||||
tb.serdes_sink.clear()
|
||||
|
||||
dut.tx_pfc_req.value = 0x00
|
||||
dut.tx_pfc_resend.value = 0
|
||||
dut.rx_pfc_en.value = 0xff
|
||||
dut.rx_pfc_ack.value = 0x00
|
||||
|
||||
dut.tx_lfc_pause_en.value = 0
|
||||
dut.tx_pause_req.value = 0
|
||||
|
||||
dut.cfg_mcf_rx_eth_dst_mcast.value = 0x0180C2000001
|
||||
dut.cfg_mcf_rx_check_eth_dst_mcast.value = 1
|
||||
dut.cfg_mcf_rx_eth_dst_ucast.value = 0xDAD1D2D3D4D5
|
||||
dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0
|
||||
dut.cfg_mcf_rx_eth_src.value = 0x5A5152535455
|
||||
dut.cfg_mcf_rx_check_eth_src.value = 0
|
||||
dut.cfg_mcf_rx_eth_type.value = 0x8808
|
||||
dut.cfg_mcf_rx_opcode_lfc.value = 0x0001
|
||||
dut.cfg_mcf_rx_check_opcode_lfc.value = 1
|
||||
dut.cfg_mcf_rx_opcode_pfc.value = 0x0101
|
||||
dut.cfg_mcf_rx_check_opcode_pfc.value = 1
|
||||
|
||||
dut.cfg_mcf_rx_forward.value = 0
|
||||
dut.cfg_mcf_rx_enable.value = 1
|
||||
|
||||
dut.cfg_tx_pfc_eth_dst.value = 0x0180C2000001
|
||||
dut.cfg_tx_pfc_eth_src.value = 0x5A5152535455
|
||||
dut.cfg_tx_pfc_eth_type.value = 0x8808
|
||||
dut.cfg_tx_pfc_opcode.value = 0x0101
|
||||
dut.cfg_tx_pfc_en.value = 1
|
||||
dut.cfg_tx_pfc_quanta.value = [0xFFFF]*8
|
||||
dut.cfg_tx_pfc_refresh.value = [0x7F00]*8
|
||||
|
||||
dut.cfg_rx_pfc_opcode.value = 0x0101
|
||||
dut.cfg_rx_pfc_en.value = 1
|
||||
|
||||
test_tx_pkts = []
|
||||
test_rx_pkts = []
|
||||
|
||||
for k in range(32):
|
||||
length = 512
|
||||
payload = bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000)
|
||||
test_pkt = eth / payload
|
||||
test_tx_pkts.append(test_pkt.copy())
|
||||
|
||||
await tb.axis_source.send(bytes(test_pkt))
|
||||
|
||||
eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='5A:51:52:53:54:55', type=0x8000)
|
||||
test_pkt = eth / payload
|
||||
test_rx_pkts.append(test_pkt.copy())
|
||||
|
||||
test_frame = GmiiFrame.from_payload(bytes(test_pkt))
|
||||
await tb.serdes_source.send(test_frame)
|
||||
|
||||
if k == 16:
|
||||
eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808)
|
||||
test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x00FF, 10, 20, 30, 40, 50, 60, 70, 80)
|
||||
test_rx_pkts.append(test_pkt.copy())
|
||||
|
||||
test_frame = GmiiFrame.from_payload(bytes(test_pkt))
|
||||
await tb.serdes_source.send(test_frame)
|
||||
|
||||
dut.rx_pfc_ack.value = 0xff
|
||||
|
||||
for i in range(8):
|
||||
for k in range(500):
|
||||
await RisingEdge(dut.tx_clk)
|
||||
|
||||
dut.tx_pfc_req.value = 0xff >> (7-i)
|
||||
|
||||
for k in range(500):
|
||||
await RisingEdge(dut.tx_clk)
|
||||
|
||||
dut.tx_pfc_req.value = 0x00
|
||||
|
||||
while test_rx_pkts:
|
||||
rx_frame = await tb.axis_sink.recv()
|
||||
|
||||
rx_pkt = Ether(bytes(rx_frame))
|
||||
|
||||
tb.log.info("RX packet: %s", repr(rx_pkt))
|
||||
|
||||
if rx_pkt.type == 0x8808:
|
||||
test_pkt = test_rx_pkts.pop(0)
|
||||
# check prefix as frame gets zero-padded
|
||||
assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
|
||||
if isinstance(rx_frame.tuser, list):
|
||||
assert rx_frame.tuser[-1] & 1
|
||||
else:
|
||||
assert rx_frame.tuser & 1
|
||||
else:
|
||||
test_pkt = test_rx_pkts.pop(0)
|
||||
# check prefix as frame gets zero-padded
|
||||
assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
|
||||
if isinstance(rx_frame.tuser, list):
|
||||
assert not rx_frame.tuser[-1] & 1
|
||||
else:
|
||||
assert not rx_frame.tuser & 1
|
||||
|
||||
tx_pfc_cnt = 0
|
||||
|
||||
while test_tx_pkts:
|
||||
tx_frame = await tb.serdes_sink.recv()
|
||||
|
||||
tx_pkt = Ether(bytes(tx_frame.get_payload()))
|
||||
|
||||
tb.log.info("TX packet: %s", repr(tx_pkt))
|
||||
|
||||
if tx_pkt.type == 0x8808:
|
||||
tx_pfc_cnt += 1
|
||||
else:
|
||||
test_pkt = test_tx_pkts.pop(0)
|
||||
# check prefix as frame gets zero-padded
|
||||
assert bytes(tx_pkt).find(bytes(test_pkt)) == 0
|
||||
|
||||
assert tx_pfc_cnt == 9
|
||||
|
||||
assert tb.axis_sink.empty()
|
||||
assert tb.serdes_sink.empty()
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(dut.tx_clk)
|
||||
|
||||
|
||||
def size_list():
|
||||
return list(range(60, 128)) + [512, 1514, 9214] + [60]*10
|
||||
|
||||
|
||||
def incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
|
||||
def cycle_en():
|
||||
return itertools.cycle([0, 0, 0, 1])
|
||||
|
||||
|
||||
if getattr(cocotb, 'top', None) is not None:
|
||||
|
||||
gbx_cfgs = [None]
|
||||
|
||||
if cocotb.top.RX_GBX_IF_EN.value:
|
||||
gbx_cfgs.append((5, [4]))
|
||||
|
||||
for test in [run_test_rx, run_test_tx]:
|
||||
|
||||
factory = TestFactory(test)
|
||||
factory.add_option("payload_lengths", [size_list])
|
||||
factory.add_option("payload_data", [incrementing_payload])
|
||||
factory.add_option("ifg", [12, 0])
|
||||
factory.add_option("gbx_cfg", gbx_cfgs)
|
||||
factory.generate_tests()
|
||||
|
||||
for test in [run_test_tx_underrun, run_test_tx_error]:
|
||||
|
||||
factory = TestFactory(test)
|
||||
factory.add_option("ifg", [12])
|
||||
factory.add_option("gbx_cfg", gbx_cfgs)
|
||||
factory.generate_tests()
|
||||
|
||||
if cocotb.top.PFC_EN.value:
|
||||
for test in [run_test_lfc, run_test_pfc]:
|
||||
factory = TestFactory(test)
|
||||
factory.add_option("ifg", [12])
|
||||
factory.add_option("gbx_cfg", gbx_cfgs)
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize(("dic_en", "pfc_en"), [(1, 1), (1, 0), (0, 0)])
|
||||
@pytest.mark.parametrize("gbx_en", [1, 0])
|
||||
@pytest.mark.parametrize("ptp_td_en", [1, 0])
|
||||
@pytest.mark.parametrize("data_w", [8, 16])
|
||||
def test_taxi_eth_mac_phy_1g_basex(request, data_w, ptp_td_en, gbx_en, dic_en, pfc_en):
|
||||
dut = "taxi_eth_mac_phy_1g_basex"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.f"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['DATA_W'] = data_w
|
||||
parameters['TX_GBX_IF_EN'] = gbx_en
|
||||
parameters['RX_GBX_IF_EN'] = parameters['TX_GBX_IF_EN']
|
||||
parameters['DIC_EN'] = dic_en
|
||||
parameters['PTP_TS_EN'] = 1
|
||||
parameters['PTP_TD_EN'] = ptp_td_en
|
||||
parameters['PTP_TS_FMT_TOD'] = 1
|
||||
parameters['PTP_TS_W'] = 96 if parameters['PTP_TS_FMT_TOD'] else 64
|
||||
parameters['PTP_TD_SDI_PIPELINE'] = 2
|
||||
parameters['TX_TAG_W'] = 16
|
||||
parameters['BIT_REVERSE'] = 0
|
||||
parameters['ENC_8B10B_EN'] = 0
|
||||
parameters['DEC_8B10B_EN'] = parameters['ENC_8B10B_EN']
|
||||
parameters['PRBS31_EN'] = 1
|
||||
parameters['TX_SERDES_PIPELINE'] = 2
|
||||
parameters['RX_SERDES_PIPELINE'] = 2
|
||||
parameters['PFC_EN'] = pfc_en
|
||||
parameters['PAUSE_EN'] = parameters['PFC_EN']
|
||||
parameters['STAT_EN'] = 1
|
||||
parameters['STAT_TX_LEVEL'] = 2
|
||||
parameters['STAT_RX_LEVEL'] = parameters['STAT_TX_LEVEL']
|
||||
parameters['STAT_ID_BASE'] = 0
|
||||
parameters['STAT_UPDATE_PERIOD'] = 1024
|
||||
parameters['STAT_STR_EN'] = 1
|
||||
parameters['STAT_PREFIX_STR'] = "\"MAC\""
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
@@ -0,0 +1,414 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2026 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* 1000BASE-X Ethernet MAC/PHY combination testbench
|
||||
*/
|
||||
module test_taxi_eth_mac_phy_1g_basex #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter DATA_W = 16,
|
||||
parameter CTRL_W = DATA_W/8,
|
||||
parameter logic TX_GBX_IF_EN = 1'b0,
|
||||
parameter logic RX_GBX_IF_EN = TX_GBX_IF_EN,
|
||||
parameter logic DIC_EN = 1'b1,
|
||||
parameter logic PTP_TS_EN = 1'b0,
|
||||
parameter logic PTP_TD_EN = PTP_TS_EN,
|
||||
parameter logic PTP_TS_FMT_TOD = 1'b1,
|
||||
parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64,
|
||||
parameter PTP_TD_SDI_PIPELINE = 2,
|
||||
parameter TX_TAG_W = 16,
|
||||
parameter logic BIT_REVERSE = 1'b0,
|
||||
parameter logic ENC_8B10B_EN = 1'b0,
|
||||
parameter logic DEC_8B10B_EN = ENC_8B10B_EN,
|
||||
parameter logic PRBS31_EN = 1'b0,
|
||||
parameter TX_SERDES_PIPELINE = 0,
|
||||
parameter RX_SERDES_PIPELINE = 0,
|
||||
parameter logic PFC_EN = 1'b0,
|
||||
parameter logic PAUSE_EN = PFC_EN,
|
||||
parameter logic STAT_EN = 1'b0,
|
||||
parameter STAT_TX_LEVEL = 1,
|
||||
parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
|
||||
parameter STAT_ID_BASE = 0,
|
||||
parameter STAT_UPDATE_PERIOD = 1024,
|
||||
parameter logic STAT_STR_EN = 1'b1,
|
||||
parameter logic [8*8-1:0] STAT_PREFIX_STR = "MAC"
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
localparam TX_USER_W = 1;
|
||||
localparam RX_USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1;
|
||||
|
||||
logic rx_clk;
|
||||
logic rx_rst;
|
||||
logic tx_clk;
|
||||
logic tx_rst;
|
||||
|
||||
taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(TX_USER_W), .ID_EN(1), .ID_W(TX_TAG_W)) s_axis_tx();
|
||||
taxi_axis_if #(.DATA_W(PTP_TS_W), .KEEP_W(1), .ID_EN(1), .ID_W(TX_TAG_W)) m_axis_tx_cpl();
|
||||
taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(RX_USER_W)) m_axis_rx();
|
||||
|
||||
logic [DATA_W-1:0] serdes_tx_data;
|
||||
logic [CTRL_W-1:0] serdes_tx_data_k;
|
||||
logic [CTRL_W-1:0] serdes_tx_data_dm;
|
||||
logic [CTRL_W-1:0] serdes_tx_data_dv;
|
||||
logic serdes_tx_data_valid;
|
||||
logic serdes_tx_gbx_req_sync;
|
||||
logic serdes_tx_gbx_req_stall;
|
||||
logic serdes_tx_gbx_sync;
|
||||
logic [DATA_W-1:0] serdes_rx_data;
|
||||
logic [CTRL_W-1:0] serdes_rx_data_k;
|
||||
logic serdes_rx_data_valid;
|
||||
logic serdes_rx_reset_req;
|
||||
|
||||
logic ptp_clk;
|
||||
logic ptp_rst;
|
||||
logic ptp_sample_clk;
|
||||
logic ptp_td_sdi;
|
||||
logic [PTP_TS_W-1:0] tx_ptp_ts_in;
|
||||
logic [PTP_TS_W-1:0] tx_ptp_ts_out;
|
||||
logic tx_ptp_ts_step_out;
|
||||
logic tx_ptp_locked;
|
||||
logic [PTP_TS_W-1:0] rx_ptp_ts_in;
|
||||
logic [PTP_TS_W-1:0] rx_ptp_ts_out;
|
||||
logic rx_ptp_ts_step_out;
|
||||
logic rx_ptp_locked;
|
||||
|
||||
logic tx_lfc_req;
|
||||
logic tx_lfc_resend;
|
||||
logic rx_lfc_en;
|
||||
logic rx_lfc_req;
|
||||
logic rx_lfc_ack;
|
||||
|
||||
logic [7:0] tx_pfc_req;
|
||||
logic tx_pfc_resend;
|
||||
logic [7:0] rx_pfc_en;
|
||||
logic [7:0] rx_pfc_req;
|
||||
logic [7:0] rx_pfc_ack;
|
||||
|
||||
logic tx_lfc_pause_en;
|
||||
logic tx_pause_req;
|
||||
logic tx_pause_ack;
|
||||
|
||||
logic stat_clk;
|
||||
logic stat_rst;
|
||||
taxi_axis_if #(.DATA_W(24), .KEEP_W(1), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) m_axis_stat();
|
||||
|
||||
logic [1:0] tx_start_packet;
|
||||
logic [1:0] stat_tx_byte;
|
||||
logic [15:0] stat_tx_pkt_len;
|
||||
logic stat_tx_pkt_ucast;
|
||||
logic stat_tx_pkt_mcast;
|
||||
logic stat_tx_pkt_bcast;
|
||||
logic stat_tx_pkt_vlan;
|
||||
logic stat_tx_pkt_good;
|
||||
logic stat_tx_pkt_bad;
|
||||
logic stat_tx_pad_frame;
|
||||
logic stat_tx_err_oversize;
|
||||
logic stat_tx_err_user;
|
||||
logic stat_tx_err_underflow;
|
||||
logic [1:0] rx_start_packet;
|
||||
logic [4:0] rx_error_count;
|
||||
logic rx_block_lock;
|
||||
logic rx_high_ber;
|
||||
logic rx_status;
|
||||
logic [1:0] stat_rx_byte;
|
||||
logic [15:0] stat_rx_pkt_len;
|
||||
logic stat_rx_pkt_fragment;
|
||||
logic stat_rx_pkt_jabber;
|
||||
logic stat_rx_pkt_ucast;
|
||||
logic stat_rx_pkt_mcast;
|
||||
logic stat_rx_pkt_bcast;
|
||||
logic stat_rx_pkt_vlan;
|
||||
logic stat_rx_pkt_good;
|
||||
logic stat_rx_pkt_bad;
|
||||
logic stat_rx_err_oversize;
|
||||
logic stat_rx_err_bad_fcs;
|
||||
logic stat_rx_err_bad_block;
|
||||
logic stat_rx_err_framing;
|
||||
logic stat_rx_err_preamble;
|
||||
logic stat_rx_fifo_drop;
|
||||
logic stat_tx_mcf;
|
||||
logic stat_rx_mcf;
|
||||
logic stat_tx_lfc_pkt;
|
||||
logic stat_tx_lfc_xon;
|
||||
logic stat_tx_lfc_xoff;
|
||||
logic stat_tx_lfc_paused;
|
||||
logic stat_tx_pfc_pkt;
|
||||
logic [7:0] stat_tx_pfc_xon;
|
||||
logic [7:0] stat_tx_pfc_xoff;
|
||||
logic [7:0] stat_tx_pfc_paused;
|
||||
logic stat_rx_lfc_pkt;
|
||||
logic stat_rx_lfc_xon;
|
||||
logic stat_rx_lfc_xoff;
|
||||
logic stat_rx_lfc_paused;
|
||||
logic stat_rx_pfc_pkt;
|
||||
logic [7:0] stat_rx_pfc_xon;
|
||||
logic [7:0] stat_rx_pfc_xoff;
|
||||
logic [7:0] stat_rx_pfc_paused;
|
||||
|
||||
logic cfg_tx_pad_en;
|
||||
logic [7:0] cfg_tx_min_pkt_len;
|
||||
logic [15:0] cfg_tx_max_pkt_len;
|
||||
logic [7:0] cfg_tx_ifg;
|
||||
logic cfg_tx_enable;
|
||||
logic [15:0] cfg_rx_max_pkt_len;
|
||||
logic cfg_rx_enable;
|
||||
logic cfg_tx_prbs31_enable;
|
||||
logic cfg_rx_prbs31_enable;
|
||||
logic [47:0] cfg_mcf_rx_eth_dst_mcast;
|
||||
logic cfg_mcf_rx_check_eth_dst_mcast;
|
||||
logic [47:0] cfg_mcf_rx_eth_dst_ucast;
|
||||
logic cfg_mcf_rx_check_eth_dst_ucast;
|
||||
logic [47:0] cfg_mcf_rx_eth_src;
|
||||
logic cfg_mcf_rx_check_eth_src;
|
||||
logic [15:0] cfg_mcf_rx_eth_type;
|
||||
logic [15:0] cfg_mcf_rx_opcode_lfc;
|
||||
logic cfg_mcf_rx_check_opcode_lfc;
|
||||
logic [15:0] cfg_mcf_rx_opcode_pfc;
|
||||
logic cfg_mcf_rx_check_opcode_pfc;
|
||||
logic cfg_mcf_rx_forward;
|
||||
logic cfg_mcf_rx_enable;
|
||||
logic [47:0] cfg_tx_lfc_eth_dst;
|
||||
logic [47:0] cfg_tx_lfc_eth_src;
|
||||
logic [15:0] cfg_tx_lfc_eth_type;
|
||||
logic [15:0] cfg_tx_lfc_opcode;
|
||||
logic cfg_tx_lfc_en;
|
||||
logic [15:0] cfg_tx_lfc_quanta;
|
||||
logic [15:0] cfg_tx_lfc_refresh;
|
||||
logic [47:0] cfg_tx_pfc_eth_dst;
|
||||
logic [47:0] cfg_tx_pfc_eth_src;
|
||||
logic [15:0] cfg_tx_pfc_eth_type;
|
||||
logic [15:0] cfg_tx_pfc_opcode;
|
||||
logic cfg_tx_pfc_en;
|
||||
logic [15:0] cfg_tx_pfc_quanta[8];
|
||||
logic [15:0] cfg_tx_pfc_refresh[8];
|
||||
logic [15:0] cfg_rx_lfc_opcode;
|
||||
logic cfg_rx_lfc_en;
|
||||
logic [15:0] cfg_rx_pfc_opcode;
|
||||
logic cfg_rx_pfc_en;
|
||||
|
||||
taxi_eth_mac_phy_1g_basex #(
|
||||
.DATA_W(DATA_W),
|
||||
.CTRL_W(CTRL_W),
|
||||
.TX_GBX_IF_EN(TX_GBX_IF_EN),
|
||||
.RX_GBX_IF_EN(RX_GBX_IF_EN),
|
||||
.DIC_EN(DIC_EN),
|
||||
.PTP_TS_EN(PTP_TS_EN),
|
||||
.PTP_TD_EN(PTP_TD_EN),
|
||||
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
|
||||
.PTP_TS_W(PTP_TS_W),
|
||||
.PTP_TD_SDI_PIPELINE(PTP_TD_SDI_PIPELINE),
|
||||
.BIT_REVERSE(BIT_REVERSE),
|
||||
.ENC_8B10B_EN(ENC_8B10B_EN),
|
||||
.DEC_8B10B_EN(DEC_8B10B_EN),
|
||||
.PRBS31_EN(PRBS31_EN),
|
||||
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
|
||||
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
|
||||
.PFC_EN(PFC_EN),
|
||||
.PAUSE_EN(PAUSE_EN),
|
||||
.STAT_EN(STAT_EN),
|
||||
.STAT_TX_LEVEL(STAT_TX_LEVEL),
|
||||
.STAT_RX_LEVEL(STAT_RX_LEVEL),
|
||||
.STAT_ID_BASE(STAT_ID_BASE),
|
||||
.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD),
|
||||
.STAT_STR_EN(STAT_STR_EN),
|
||||
.STAT_PREFIX_STR(STAT_PREFIX_STR)
|
||||
)
|
||||
uut (
|
||||
.rx_clk(rx_clk),
|
||||
.rx_rst(rx_rst),
|
||||
.tx_clk(tx_clk),
|
||||
.tx_rst(tx_rst),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(s_axis_tx),
|
||||
.m_axis_tx_cpl(m_axis_tx_cpl),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(m_axis_rx),
|
||||
|
||||
/*
|
||||
* SERDES interface
|
||||
*/
|
||||
.serdes_tx_data(serdes_tx_data),
|
||||
.serdes_tx_data_k(serdes_tx_data_k),
|
||||
.serdes_tx_data_dm(serdes_tx_data_dm),
|
||||
.serdes_tx_data_dv(serdes_tx_data_dv),
|
||||
.serdes_tx_data_valid(serdes_tx_data_valid),
|
||||
.serdes_tx_gbx_req_sync(serdes_tx_gbx_req_sync),
|
||||
.serdes_tx_gbx_req_stall(serdes_tx_gbx_req_stall),
|
||||
.serdes_tx_gbx_sync(serdes_tx_gbx_sync),
|
||||
.serdes_rx_data(serdes_rx_data),
|
||||
.serdes_rx_data_k(serdes_rx_data_k),
|
||||
.serdes_rx_data_valid(serdes_rx_data_valid),
|
||||
.serdes_rx_reset_req(serdes_rx_reset_req),
|
||||
|
||||
/*
|
||||
* PTP
|
||||
*/
|
||||
.ptp_clk(ptp_clk),
|
||||
.ptp_rst(ptp_rst),
|
||||
.ptp_sample_clk(ptp_sample_clk),
|
||||
.ptp_td_sdi(ptp_td_sdi),
|
||||
.tx_ptp_ts_in(tx_ptp_ts_in),
|
||||
.tx_ptp_ts_out(tx_ptp_ts_out),
|
||||
.tx_ptp_ts_step_out(tx_ptp_ts_step_out),
|
||||
.tx_ptp_locked(tx_ptp_locked),
|
||||
.rx_ptp_ts_in(rx_ptp_ts_in),
|
||||
.rx_ptp_ts_out(rx_ptp_ts_out),
|
||||
.rx_ptp_ts_step_out(rx_ptp_ts_step_out),
|
||||
.rx_ptp_locked(rx_ptp_locked),
|
||||
|
||||
/*
|
||||
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
|
||||
*/
|
||||
.tx_lfc_req(tx_lfc_req),
|
||||
.tx_lfc_resend(tx_lfc_resend),
|
||||
.rx_lfc_en(rx_lfc_en),
|
||||
.rx_lfc_req(rx_lfc_req),
|
||||
.rx_lfc_ack(rx_lfc_ack),
|
||||
|
||||
/*
|
||||
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
|
||||
*/
|
||||
.tx_pfc_req(tx_pfc_req),
|
||||
.tx_pfc_resend(tx_pfc_resend),
|
||||
.rx_pfc_en(rx_pfc_en),
|
||||
.rx_pfc_req(rx_pfc_req),
|
||||
.rx_pfc_ack(rx_pfc_ack),
|
||||
|
||||
/*
|
||||
* Pause interface
|
||||
*/
|
||||
.tx_lfc_pause_en(tx_lfc_pause_en),
|
||||
.tx_pause_req(tx_pause_req),
|
||||
.tx_pause_ack(tx_pause_ack),
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
.stat_clk(stat_clk),
|
||||
.stat_rst(stat_rst),
|
||||
.m_axis_stat(m_axis_stat),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_start_packet(tx_start_packet),
|
||||
.stat_tx_byte(stat_tx_byte),
|
||||
.stat_tx_pkt_len(stat_tx_pkt_len),
|
||||
.stat_tx_pkt_ucast(stat_tx_pkt_ucast),
|
||||
.stat_tx_pkt_mcast(stat_tx_pkt_mcast),
|
||||
.stat_tx_pkt_bcast(stat_tx_pkt_bcast),
|
||||
.stat_tx_pkt_vlan(stat_tx_pkt_vlan),
|
||||
.stat_tx_pkt_good(stat_tx_pkt_good),
|
||||
.stat_tx_pkt_bad(stat_tx_pkt_bad),
|
||||
.stat_tx_pad_frame(stat_tx_pad_frame),
|
||||
.stat_tx_err_oversize(stat_tx_err_oversize),
|
||||
.stat_tx_err_user(stat_tx_err_user),
|
||||
.stat_tx_err_underflow(stat_tx_err_underflow),
|
||||
.rx_start_packet(rx_start_packet),
|
||||
.rx_error_count(rx_error_count),
|
||||
.rx_block_lock(rx_block_lock),
|
||||
.rx_high_ber(rx_high_ber),
|
||||
.rx_status(rx_status),
|
||||
.stat_rx_byte(stat_rx_byte),
|
||||
.stat_rx_pkt_len(stat_rx_pkt_len),
|
||||
.stat_rx_pkt_fragment(stat_rx_pkt_fragment),
|
||||
.stat_rx_pkt_jabber(stat_rx_pkt_jabber),
|
||||
.stat_rx_pkt_ucast(stat_rx_pkt_ucast),
|
||||
.stat_rx_pkt_mcast(stat_rx_pkt_mcast),
|
||||
.stat_rx_pkt_bcast(stat_rx_pkt_bcast),
|
||||
.stat_rx_pkt_vlan(stat_rx_pkt_vlan),
|
||||
.stat_rx_pkt_good(stat_rx_pkt_good),
|
||||
.stat_rx_pkt_bad(stat_rx_pkt_bad),
|
||||
.stat_rx_err_oversize(stat_rx_err_oversize),
|
||||
.stat_rx_err_bad_fcs(stat_rx_err_bad_fcs),
|
||||
.stat_rx_err_bad_block(stat_rx_err_bad_block),
|
||||
.stat_rx_err_framing(stat_rx_err_framing),
|
||||
.stat_rx_err_preamble(stat_rx_err_preamble),
|
||||
.stat_rx_fifo_drop(stat_rx_fifo_drop),
|
||||
.stat_tx_mcf(stat_tx_mcf),
|
||||
.stat_rx_mcf(stat_rx_mcf),
|
||||
.stat_tx_lfc_pkt(stat_tx_lfc_pkt),
|
||||
.stat_tx_lfc_xon(stat_tx_lfc_xon),
|
||||
.stat_tx_lfc_xoff(stat_tx_lfc_xoff),
|
||||
.stat_tx_lfc_paused(stat_tx_lfc_paused),
|
||||
.stat_tx_pfc_pkt(stat_tx_pfc_pkt),
|
||||
.stat_tx_pfc_xon(stat_tx_pfc_xon),
|
||||
.stat_tx_pfc_xoff(stat_tx_pfc_xoff),
|
||||
.stat_tx_pfc_paused(stat_tx_pfc_paused),
|
||||
.stat_rx_lfc_pkt(stat_rx_lfc_pkt),
|
||||
.stat_rx_lfc_xon(stat_rx_lfc_xon),
|
||||
.stat_rx_lfc_xoff(stat_rx_lfc_xoff),
|
||||
.stat_rx_lfc_paused(stat_rx_lfc_paused),
|
||||
.stat_rx_pfc_pkt(stat_rx_pfc_pkt),
|
||||
.stat_rx_pfc_xon(stat_rx_pfc_xon),
|
||||
.stat_rx_pfc_xoff(stat_rx_pfc_xoff),
|
||||
.stat_rx_pfc_paused(stat_rx_pfc_paused),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_tx_pad_en(cfg_tx_pad_en),
|
||||
.cfg_tx_min_pkt_len(cfg_tx_min_pkt_len),
|
||||
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
|
||||
.cfg_tx_ifg(cfg_tx_ifg),
|
||||
.cfg_tx_enable(cfg_tx_enable),
|
||||
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
|
||||
.cfg_rx_enable(cfg_rx_enable),
|
||||
.cfg_tx_prbs31_enable(cfg_tx_prbs31_enable),
|
||||
.cfg_rx_prbs31_enable(cfg_rx_prbs31_enable),
|
||||
.cfg_mcf_rx_eth_dst_mcast(cfg_mcf_rx_eth_dst_mcast),
|
||||
.cfg_mcf_rx_check_eth_dst_mcast(cfg_mcf_rx_check_eth_dst_mcast),
|
||||
.cfg_mcf_rx_eth_dst_ucast(cfg_mcf_rx_eth_dst_ucast),
|
||||
.cfg_mcf_rx_check_eth_dst_ucast(cfg_mcf_rx_check_eth_dst_ucast),
|
||||
.cfg_mcf_rx_eth_src(cfg_mcf_rx_eth_src),
|
||||
.cfg_mcf_rx_check_eth_src(cfg_mcf_rx_check_eth_src),
|
||||
.cfg_mcf_rx_eth_type(cfg_mcf_rx_eth_type),
|
||||
.cfg_mcf_rx_opcode_lfc(cfg_mcf_rx_opcode_lfc),
|
||||
.cfg_mcf_rx_check_opcode_lfc(cfg_mcf_rx_check_opcode_lfc),
|
||||
.cfg_mcf_rx_opcode_pfc(cfg_mcf_rx_opcode_pfc),
|
||||
.cfg_mcf_rx_check_opcode_pfc(cfg_mcf_rx_check_opcode_pfc),
|
||||
.cfg_mcf_rx_forward(cfg_mcf_rx_forward),
|
||||
.cfg_mcf_rx_enable(cfg_mcf_rx_enable),
|
||||
.cfg_tx_lfc_eth_dst(cfg_tx_lfc_eth_dst),
|
||||
.cfg_tx_lfc_eth_src(cfg_tx_lfc_eth_src),
|
||||
.cfg_tx_lfc_eth_type(cfg_tx_lfc_eth_type),
|
||||
.cfg_tx_lfc_opcode(cfg_tx_lfc_opcode),
|
||||
.cfg_tx_lfc_en(cfg_tx_lfc_en),
|
||||
.cfg_tx_lfc_quanta(cfg_tx_lfc_quanta),
|
||||
.cfg_tx_lfc_refresh(cfg_tx_lfc_refresh),
|
||||
.cfg_tx_pfc_eth_dst(cfg_tx_pfc_eth_dst),
|
||||
.cfg_tx_pfc_eth_src(cfg_tx_pfc_eth_src),
|
||||
.cfg_tx_pfc_eth_type(cfg_tx_pfc_eth_type),
|
||||
.cfg_tx_pfc_opcode(cfg_tx_pfc_opcode),
|
||||
.cfg_tx_pfc_en(cfg_tx_pfc_en),
|
||||
.cfg_tx_pfc_quanta(cfg_tx_pfc_quanta),
|
||||
.cfg_tx_pfc_refresh(cfg_tx_pfc_refresh),
|
||||
.cfg_rx_lfc_opcode(cfg_rx_lfc_opcode),
|
||||
.cfg_rx_lfc_en(cfg_rx_lfc_en),
|
||||
.cfg_rx_pfc_opcode(cfg_rx_pfc_opcode),
|
||||
.cfg_rx_pfc_en(cfg_rx_pfc_en)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
86
src/eth/tb/taxi_eth_mac_phy_1g_basex_fifo/Makefile
Normal file
86
src/eth/tb/taxi_eth_mac_phy_1g_basex_fifo/Makefile
Normal file
@@ -0,0 +1,86 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2021-2026 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_eth_mac_phy_1g_basex_fifo
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_DATA_W := 16
|
||||
export PARAM_TX_GBX_IF_EN := 1
|
||||
export PARAM_RX_GBX_IF_EN := $(PARAM_TX_GBX_IF_EN)
|
||||
export PARAM_AXIS_DATA_W := $(PARAM_DATA_W)
|
||||
export PARAM_DIC_EN := 1
|
||||
export PARAM_PTP_TS_EN := 1
|
||||
export PARAM_PTP_TD_EN := $(PARAM_PTP_TS_EN)
|
||||
export PARAM_PTP_TS_FMT_TOD := 1
|
||||
export PARAM_PTP_TS_W := $(if $(filter-out 1,$(PARAM_PTP_TS_FMT_TOD)),64,96)
|
||||
export PARAM_PTP_TD_SDI_PIPELINE := 2
|
||||
export PARAM_TX_TAG_W := 16
|
||||
export PARAM_BIT_REVERSE := 0
|
||||
export PARAM_ENC_8B10B_EN := 0
|
||||
export PARAM_DEC_8B10B_EN := $(PARAM_ENC_8B10B_EN)
|
||||
export PARAM_PRBS31_EN := 1
|
||||
export PARAM_TX_SERDES_PIPELINE := 2
|
||||
export PARAM_RX_SERDES_PIPELINE := 2
|
||||
export PARAM_STAT_EN := 1
|
||||
export PARAM_STAT_TX_LEVEL := 2
|
||||
export PARAM_STAT_RX_LEVEL := $(PARAM_STAT_TX_LEVEL)
|
||||
export PARAM_STAT_ID_BASE := 0
|
||||
export PARAM_STAT_UPDATE_PERIOD := 1024
|
||||
export PARAM_STAT_STR_EN := 1
|
||||
export PARAM_STAT_PREFIX_STR := "\"MAC\""
|
||||
export PARAM_TX_FIFO_DEPTH := 16384
|
||||
export PARAM_TX_FIFO_RAM_PIPELINE := 1
|
||||
export PARAM_TX_FRAME_FIFO := 1
|
||||
export PARAM_TX_DROP_OVERSIZE_FRAME := $(PARAM_TX_FRAME_FIFO)
|
||||
export PARAM_TX_DROP_BAD_FRAME := $(PARAM_TX_DROP_OVERSIZE_FRAME)
|
||||
export PARAM_TX_DROP_WHEN_FULL := 0
|
||||
export PARAM_TX_CPL_FIFO_DEPTH := 64
|
||||
export PARAM_RX_FIFO_DEPTH := 16384
|
||||
export PARAM_RX_FIFO_RAM_PIPELINE := 1
|
||||
export PARAM_RX_FRAME_FIFO := 1
|
||||
export PARAM_RX_DROP_OVERSIZE_FRAME := $(PARAM_RX_FRAME_FIFO)
|
||||
export PARAM_RX_DROP_BAD_FRAME := $(PARAM_RX_DROP_OVERSIZE_FRAME)
|
||||
export PARAM_RX_DROP_WHEN_FULL := $(PARAM_RX_DROP_OVERSIZE_FRAME)
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
1
src/eth/tb/taxi_eth_mac_phy_1g_basex_fifo/basex.py
Symbolic link
1
src/eth/tb/taxi_eth_mac_phy_1g_basex_fifo/basex.py
Symbolic link
@@ -0,0 +1 @@
|
||||
../basex.py
|
||||
1
src/eth/tb/taxi_eth_mac_phy_1g_basex_fifo/ptp_td.py
Symbolic link
1
src/eth/tb/taxi_eth_mac_phy_1g_basex_fifo/ptp_td.py
Symbolic link
@@ -0,0 +1 @@
|
||||
../../lib/taxi/src/ptp/tb/ptp_td.py
|
||||
@@ -0,0 +1,384 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2021-2026 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import sys
|
||||
|
||||
import pytest
|
||||
import cocotb_test.simulator
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge
|
||||
from cocotb.utils import get_time_from_sim_steps
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.eth import GmiiFrame, PtpClockSimTime
|
||||
from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame
|
||||
|
||||
try:
|
||||
from basex import BaseXSerdesSource, BaseXSerdesSink
|
||||
from ptp_td import PtpTdSource
|
||||
except ImportError:
|
||||
# attempt import from current directory
|
||||
sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
|
||||
try:
|
||||
from basex import BaseXSerdesSource, BaseXSerdesSink
|
||||
from ptp_td import PtpTdSource
|
||||
finally:
|
||||
del sys.path[0]
|
||||
|
||||
|
||||
class TB:
|
||||
def __init__(self, dut, gbx_cfg=None):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
if len(dut.serdes_tx_data) == 16:
|
||||
if gbx_cfg:
|
||||
self.clk_period = 16
|
||||
else:
|
||||
self.clk_period = 16
|
||||
else:
|
||||
if gbx_cfg:
|
||||
self.clk_period = 8
|
||||
else:
|
||||
self.clk_period = 8
|
||||
|
||||
cocotb.start_soon(Clock(dut.logic_clk, self.clk_period, units="ns").start())
|
||||
cocotb.start_soon(Clock(dut.rx_clk, self.clk_period, units="ns").start())
|
||||
cocotb.start_soon(Clock(dut.tx_clk, self.clk_period, units="ns").start())
|
||||
cocotb.start_soon(Clock(dut.stat_clk, self.clk_period, units="ns").start())
|
||||
|
||||
self.serdes_source = BaseXSerdesSource(
|
||||
data=dut.serdes_rx_data,
|
||||
data_k=dut.serdes_rx_data_k,
|
||||
data_valid=dut.serdes_rx_data_valid,
|
||||
clock=dut.rx_clk,
|
||||
enc_8b10b=False,
|
||||
gbx_cfg=gbx_cfg
|
||||
)
|
||||
self.serdes_sink = BaseXSerdesSink(
|
||||
data=dut.serdes_tx_data,
|
||||
data_k=dut.serdes_tx_data_k,
|
||||
data_valid=dut.serdes_tx_data_valid,
|
||||
gbx_req_sync=dut.serdes_tx_gbx_req_sync,
|
||||
gbx_req_stall=dut.serdes_tx_gbx_req_stall,
|
||||
gbx_sync=dut.serdes_tx_gbx_sync,
|
||||
clock=dut.tx_clk,
|
||||
dec_8b10b=False,
|
||||
gbx_cfg=gbx_cfg
|
||||
)
|
||||
|
||||
self.axis_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_tx), dut.logic_clk, dut.logic_rst)
|
||||
self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.logic_clk, dut.logic_rst)
|
||||
self.axis_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.logic_clk, dut.logic_rst)
|
||||
|
||||
self.stat_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_stat), dut.stat_clk, dut.stat_rst)
|
||||
|
||||
self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts_in, clock=dut.logic_clk)
|
||||
dut.ptp_ts_step_in.setimmediatevalue(0)
|
||||
|
||||
self.ptp_clk_period = self.clk_period
|
||||
|
||||
cocotb.start_soon(Clock(dut.ptp_clk, self.ptp_clk_period, units="ns").start())
|
||||
cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start())
|
||||
|
||||
self.ptp_td_source = PtpTdSource(
|
||||
data=dut.ptp_td_sdi,
|
||||
clock=dut.ptp_clk,
|
||||
reset=dut.ptp_rst,
|
||||
period_ns=self.ptp_clk_period
|
||||
)
|
||||
|
||||
dut.cfg_tx_pad_en.setimmediatevalue(0)
|
||||
dut.cfg_tx_min_pkt_len.setimmediatevalue(0)
|
||||
dut.cfg_tx_max_pkt_len.setimmediatevalue(0)
|
||||
dut.cfg_tx_ifg.setimmediatevalue(0)
|
||||
dut.cfg_tx_enable.setimmediatevalue(0)
|
||||
dut.cfg_rx_max_pkt_len.setimmediatevalue(0)
|
||||
dut.cfg_rx_enable.setimmediatevalue(0)
|
||||
dut.cfg_tx_prbs31_enable.setimmediatevalue(0)
|
||||
dut.cfg_rx_prbs31_enable.setimmediatevalue(0)
|
||||
|
||||
async def reset(self):
|
||||
self.dut.logic_rst.setimmediatevalue(0)
|
||||
self.dut.rx_rst.setimmediatevalue(0)
|
||||
self.dut.tx_rst.setimmediatevalue(0)
|
||||
self.dut.ptp_rst.setimmediatevalue(0)
|
||||
self.dut.stat_rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.logic_clk)
|
||||
await RisingEdge(self.dut.logic_clk)
|
||||
self.dut.logic_rst.value = 1
|
||||
self.dut.rx_rst.value = 1
|
||||
self.dut.tx_rst.value = 1
|
||||
self.dut.ptp_rst.value = 1
|
||||
self.dut.stat_rst.value = 1
|
||||
await RisingEdge(self.dut.logic_clk)
|
||||
await RisingEdge(self.dut.logic_clk)
|
||||
self.dut.logic_rst.value = 0
|
||||
self.dut.rx_rst.value = 0
|
||||
self.dut.tx_rst.value = 0
|
||||
self.dut.ptp_rst.value = 0
|
||||
self.dut.stat_rst.value = 0
|
||||
await RisingEdge(self.dut.logic_clk)
|
||||
await RisingEdge(self.dut.logic_clk)
|
||||
|
||||
self.ptp_td_source.set_ts_tod_sim_time()
|
||||
self.ptp_td_source.set_ts_rel_sim_time()
|
||||
|
||||
|
||||
async def run_test_rx(dut, gbx_cfg=None, payload_lengths=None, payload_data=None, ifg=12):
|
||||
|
||||
if len(dut.serdes_tx_data) == 64:
|
||||
pipe_delay = 3
|
||||
else:
|
||||
pipe_delay = 3
|
||||
|
||||
tb = TB(dut, gbx_cfg)
|
||||
|
||||
tb.serdes_source.ifg = ifg
|
||||
tb.dut.cfg_tx_ifg.value = ifg
|
||||
tb.dut.cfg_rx_max_pkt_len.value = 9218-1
|
||||
tb.dut.cfg_rx_enable.value = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.log.info("Wait for block lock")
|
||||
while not int(dut.rx_block_lock.value):
|
||||
await RisingEdge(dut.rx_clk)
|
||||
|
||||
tb.log.info("Wait for PTP CDC lock")
|
||||
while not int(dut.rx_ptp_locked.value):
|
||||
await RisingEdge(dut.rx_clk)
|
||||
for k in range(2000):
|
||||
await RisingEdge(dut.rx_clk)
|
||||
|
||||
# clear out sink buffer
|
||||
tb.axis_sink.clear()
|
||||
|
||||
test_frames = [payload_data(x) for x in payload_lengths()]
|
||||
tx_frames = []
|
||||
|
||||
for test_data in test_frames:
|
||||
test_frame = GmiiFrame.from_payload(test_data, tx_complete=tx_frames.append)
|
||||
await tb.serdes_source.send(test_frame)
|
||||
|
||||
for test_data in test_frames:
|
||||
rx_frame = await tb.axis_sink.recv()
|
||||
tx_frame = tx_frames.pop(0)
|
||||
|
||||
frame_error = rx_frame.tuser & 1
|
||||
ptp_ts = rx_frame.tuser >> 1
|
||||
ptp_ts_ns = ptp_ts / 2**16
|
||||
|
||||
tx_frame_sfd_ns = get_time_from_sim_steps(tx_frame.sim_time_sfd, "ns")
|
||||
|
||||
tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns)
|
||||
tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns)
|
||||
tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns))
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert frame_error == 0
|
||||
if gbx_cfg is None:
|
||||
if dut.PTP_TD_EN.value:
|
||||
assert abs(ptp_ts_ns - tx_frame_sfd_ns - tb.clk_period*pipe_delay) < tb.clk_period*5
|
||||
else:
|
||||
assert abs(ptp_ts_ns - tx_frame_sfd_ns - tb.clk_period*pipe_delay) < tb.clk_period*2
|
||||
|
||||
assert tb.axis_sink.empty()
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(dut.logic_clk)
|
||||
|
||||
|
||||
async def run_test_tx(dut, gbx_cfg=None, payload_lengths=None, payload_data=None, ifg=12):
|
||||
|
||||
if len(dut.serdes_tx_data) == 16:
|
||||
pipe_delay = 4
|
||||
else:
|
||||
pipe_delay = 4
|
||||
|
||||
tb = TB(dut, gbx_cfg)
|
||||
|
||||
tb.serdes_source.ifg = ifg
|
||||
tb.dut.cfg_tx_pad_en.value = 1
|
||||
tb.dut.cfg_tx_min_pkt_len.value = 60-1
|
||||
tb.dut.cfg_tx_max_pkt_len.value = 9218-1
|
||||
tb.dut.cfg_tx_ifg.value = ifg
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.log.info("Wait for PTP CDC lock")
|
||||
while not int(dut.tx_ptp_locked.value):
|
||||
await RisingEdge(dut.tx_clk)
|
||||
for k in range(2000):
|
||||
await RisingEdge(dut.tx_clk)
|
||||
|
||||
tb.dut.cfg_tx_enable.value = 1
|
||||
tb.serdes_sink.clear()
|
||||
|
||||
test_frames = [payload_data(x) for x in payload_lengths()]
|
||||
|
||||
for test_data in test_frames:
|
||||
await tb.axis_source.send(AxiStreamFrame(test_data, tid=0, tuser=0))
|
||||
|
||||
for test_data in test_frames:
|
||||
rx_frame = await tb.serdes_sink.recv()
|
||||
tx_cpl = await tb.tx_cpl_sink.recv()
|
||||
|
||||
ptp_ts_ns = int(tx_cpl.tdata[0]) / 2**16
|
||||
|
||||
rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
|
||||
|
||||
tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
|
||||
tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
|
||||
tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))
|
||||
|
||||
assert rx_frame.get_payload() == test_data
|
||||
assert rx_frame.check_fcs()
|
||||
assert rx_frame.error is None
|
||||
if gbx_cfg is None:
|
||||
if dut.PTP_TD_EN.value:
|
||||
assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period*pipe_delay) < tb.clk_period*5
|
||||
else:
|
||||
assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period*pipe_delay) < tb.clk_period*2
|
||||
|
||||
assert tb.serdes_sink.empty()
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(dut.logic_clk)
|
||||
|
||||
|
||||
def size_list():
|
||||
return list(range(60, 128)) + [512, 1514, 9214] + [60]*10
|
||||
|
||||
|
||||
def incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
|
||||
def cycle_en():
|
||||
return itertools.cycle([0, 0, 0, 1])
|
||||
|
||||
|
||||
if getattr(cocotb, 'top', None) is not None:
|
||||
|
||||
gbx_cfgs = [None]
|
||||
|
||||
if cocotb.top.RX_GBX_IF_EN.value:
|
||||
gbx_cfgs.append((5, [4]))
|
||||
|
||||
for test in [run_test_rx, run_test_tx]:
|
||||
|
||||
factory = TestFactory(test)
|
||||
factory.add_option("payload_lengths", [size_list])
|
||||
factory.add_option("payload_data", [incrementing_payload])
|
||||
factory.add_option("ifg", [12, 0])
|
||||
factory.add_option("gbx_cfg", gbx_cfgs)
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("dic_en", [1, 0])
|
||||
@pytest.mark.parametrize("gbx_en", [1, 0])
|
||||
@pytest.mark.parametrize("data_w", [8, 16])
|
||||
def test_taxi_eth_mac_phy_1g_basex_fifo(request, data_w, gbx_en, dic_en):
|
||||
dut = "taxi_eth_mac_phy_1g_basex_fifo"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.f"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['DATA_W'] = data_w
|
||||
parameters['TX_GBX_IF_EN'] = gbx_en
|
||||
parameters['RX_GBX_IF_EN'] = parameters['TX_GBX_IF_EN']
|
||||
parameters['AXIS_DATA_W'] = parameters['DATA_W']
|
||||
parameters['DIC_EN'] = dic_en
|
||||
parameters['PTP_TS_EN'] = 1
|
||||
parameters['PTP_TD_EN'] = parameters['PTP_TS_EN']
|
||||
parameters['PTP_TS_FMT_TOD'] = 1
|
||||
parameters['PTP_TS_W'] = 96 if parameters['PTP_TS_FMT_TOD'] else 64
|
||||
parameters['PTP_TD_SDI_PIPELINE'] = 2
|
||||
parameters['TX_TAG_W'] = 16
|
||||
parameters['BIT_REVERSE'] = 0
|
||||
parameters['ENC_8B10B_EN'] = 0
|
||||
parameters['DEC_8B10B_EN'] = parameters['ENC_8B10B_EN']
|
||||
parameters['PRBS31_EN'] = 1
|
||||
parameters['TX_SERDES_PIPELINE'] = 2
|
||||
parameters['RX_SERDES_PIPELINE'] = 2
|
||||
parameters['STAT_EN'] = 1
|
||||
parameters['STAT_TX_LEVEL'] = 2
|
||||
parameters['STAT_RX_LEVEL'] = parameters['STAT_TX_LEVEL']
|
||||
parameters['STAT_ID_BASE'] = 0
|
||||
parameters['STAT_UPDATE_PERIOD'] = 1024
|
||||
parameters['STAT_STR_EN'] = 1
|
||||
parameters['STAT_PREFIX_STR'] = "\"MAC\""
|
||||
parameters['TX_FIFO_DEPTH'] = 16384
|
||||
parameters['TX_FIFO_RAM_PIPELINE'] = 1
|
||||
parameters['TX_FRAME_FIFO'] = 1
|
||||
parameters['TX_DROP_OVERSIZE_FRAME'] = parameters['TX_FRAME_FIFO']
|
||||
parameters['TX_DROP_BAD_FRAME'] = parameters['TX_DROP_OVERSIZE_FRAME']
|
||||
parameters['TX_DROP_WHEN_FULL'] = 0
|
||||
parameters['TX_CPL_FIFO_DEPTH'] = 64
|
||||
parameters['RX_FIFO_DEPTH'] = 16384
|
||||
parameters['RX_FIFO_RAM_PIPELINE'] = 1
|
||||
parameters['RX_FRAME_FIFO'] = 1
|
||||
parameters['RX_DROP_OVERSIZE_FRAME'] = parameters['RX_FRAME_FIFO']
|
||||
parameters['RX_DROP_BAD_FRAME'] = parameters['RX_DROP_OVERSIZE_FRAME']
|
||||
parameters['RX_DROP_WHEN_FULL'] = parameters['RX_DROP_OVERSIZE_FRAME']
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
@@ -0,0 +1,262 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2026 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* 1000BASE-X Ethernet MAC/PHY combination with TX and RX FIFOs testbench
|
||||
*/
|
||||
module test_taxi_eth_mac_phy_1g_basex_fifo #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter DATA_W = 16,
|
||||
parameter CTRL_W = DATA_W/8,
|
||||
parameter logic TX_GBX_IF_EN = 1'b0,
|
||||
parameter logic RX_GBX_IF_EN = TX_GBX_IF_EN,
|
||||
parameter AXIS_DATA_W = 8,
|
||||
parameter logic DIC_EN = 1'b1,
|
||||
parameter logic PTP_TS_EN = 1'b0,
|
||||
parameter logic PTP_TD_EN = PTP_TS_EN,
|
||||
parameter logic PTP_TS_FMT_TOD = 1'b1,
|
||||
parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64,
|
||||
parameter PTP_TD_SDI_PIPELINE = 2,
|
||||
parameter TX_TAG_W = 16,
|
||||
parameter logic BIT_REVERSE = 1'b0,
|
||||
parameter logic ENC_8B10B_EN = 1'b0,
|
||||
parameter logic DEC_8B10B_EN = ENC_8B10B_EN,
|
||||
parameter logic PRBS31_EN = 1'b0,
|
||||
parameter TX_SERDES_PIPELINE = 0,
|
||||
parameter RX_SERDES_PIPELINE = 0,
|
||||
parameter logic STAT_EN = 1'b0,
|
||||
parameter STAT_TX_LEVEL = 1,
|
||||
parameter STAT_RX_LEVEL = STAT_TX_LEVEL,
|
||||
parameter STAT_ID_BASE = 0,
|
||||
parameter STAT_UPDATE_PERIOD = 1024,
|
||||
parameter logic STAT_STR_EN = 1'b1,
|
||||
parameter logic [8*8-1:0] STAT_PREFIX_STR = "MAC",
|
||||
parameter TX_FIFO_DEPTH = 4096,
|
||||
parameter TX_FIFO_RAM_PIPELINE = 1,
|
||||
parameter logic TX_FRAME_FIFO = 1'b1,
|
||||
parameter logic TX_DROP_OVERSIZE_FRAME = TX_FRAME_FIFO,
|
||||
parameter logic TX_DROP_BAD_FRAME = TX_DROP_OVERSIZE_FRAME,
|
||||
parameter logic TX_DROP_WHEN_FULL = 1'b0,
|
||||
parameter TX_CPL_FIFO_DEPTH = 64,
|
||||
parameter RX_FIFO_DEPTH = 4096,
|
||||
parameter RX_FIFO_RAM_PIPELINE = 1,
|
||||
parameter logic RX_FRAME_FIFO = 1'b1,
|
||||
parameter logic RX_DROP_OVERSIZE_FRAME = RX_FRAME_FIFO,
|
||||
parameter logic RX_DROP_BAD_FRAME = RX_DROP_OVERSIZE_FRAME,
|
||||
parameter logic RX_DROP_WHEN_FULL = RX_DROP_OVERSIZE_FRAME
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
localparam TX_USER_W = 1;
|
||||
localparam RX_USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1;
|
||||
|
||||
logic rx_clk;
|
||||
logic rx_rst;
|
||||
logic tx_clk;
|
||||
logic tx_rst;
|
||||
logic logic_clk;
|
||||
logic logic_rst;
|
||||
|
||||
taxi_axis_if #(.DATA_W(AXIS_DATA_W), .USER_EN(1), .USER_W(TX_USER_W), .ID_EN(1), .ID_W(TX_TAG_W)) s_axis_tx();
|
||||
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_EN(1), .ID_W(TX_TAG_W)) m_axis_tx_cpl();
|
||||
taxi_axis_if #(.DATA_W(AXIS_DATA_W), .USER_EN(1), .USER_W(RX_USER_W)) m_axis_rx();
|
||||
|
||||
logic [DATA_W-1:0] serdes_tx_data;
|
||||
logic [CTRL_W-1:0] serdes_tx_data_k;
|
||||
logic [CTRL_W-1:0] serdes_tx_data_dm;
|
||||
logic [CTRL_W-1:0] serdes_tx_data_dv;
|
||||
logic serdes_tx_data_valid;
|
||||
logic serdes_tx_gbx_req_sync;
|
||||
logic serdes_tx_gbx_req_stall;
|
||||
logic serdes_tx_gbx_sync;
|
||||
logic [DATA_W-1:0] serdes_rx_data;
|
||||
logic [CTRL_W-1:0] serdes_rx_data_k;
|
||||
logic serdes_rx_data_valid;
|
||||
logic serdes_rx_reset_req;
|
||||
|
||||
logic ptp_clk;
|
||||
logic ptp_rst;
|
||||
logic ptp_sample_clk;
|
||||
logic ptp_td_sdi;
|
||||
logic [PTP_TS_W-1:0] ptp_ts_in;
|
||||
logic ptp_ts_step_in;
|
||||
logic [PTP_TS_W-1:0] tx_ptp_ts_out;
|
||||
logic tx_ptp_ts_step_out;
|
||||
logic tx_ptp_locked;
|
||||
logic [PTP_TS_W-1:0] rx_ptp_ts_out;
|
||||
logic rx_ptp_ts_step_out;
|
||||
logic rx_ptp_locked;
|
||||
|
||||
logic stat_clk;
|
||||
logic stat_rst;
|
||||
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) m_axis_stat();
|
||||
|
||||
logic tx_error_underflow;
|
||||
logic tx_fifo_overflow;
|
||||
logic tx_fifo_bad_frame;
|
||||
logic tx_fifo_good_frame;
|
||||
logic rx_error_bad_frame;
|
||||
logic rx_error_bad_fcs;
|
||||
logic rx_bad_block;
|
||||
logic rx_sequence_error;
|
||||
logic rx_block_lock;
|
||||
logic rx_high_ber;
|
||||
logic rx_status;
|
||||
logic rx_fifo_overflow;
|
||||
logic rx_fifo_bad_frame;
|
||||
logic rx_fifo_good_frame;
|
||||
|
||||
logic cfg_tx_pad_en;
|
||||
logic [7:0] cfg_tx_min_pkt_len;
|
||||
logic [15:0] cfg_tx_max_pkt_len;
|
||||
logic [7:0] cfg_tx_ifg;
|
||||
logic cfg_tx_enable;
|
||||
logic [15:0] cfg_rx_max_pkt_len;
|
||||
logic cfg_rx_enable;
|
||||
logic cfg_tx_prbs31_enable;
|
||||
logic cfg_rx_prbs31_enable;
|
||||
|
||||
taxi_eth_mac_phy_1g_basex_fifo #(
|
||||
.DATA_W(DATA_W),
|
||||
.CTRL_W(CTRL_W),
|
||||
.TX_GBX_IF_EN(TX_GBX_IF_EN),
|
||||
.RX_GBX_IF_EN(RX_GBX_IF_EN),
|
||||
.DIC_EN(DIC_EN),
|
||||
.PTP_TS_EN(PTP_TS_EN),
|
||||
.PTP_TD_EN(PTP_TD_EN),
|
||||
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
|
||||
.PTP_TS_W(PTP_TS_W),
|
||||
.PTP_TD_SDI_PIPELINE(PTP_TD_SDI_PIPELINE),
|
||||
.BIT_REVERSE(BIT_REVERSE),
|
||||
.ENC_8B10B_EN(ENC_8B10B_EN),
|
||||
.DEC_8B10B_EN(DEC_8B10B_EN),
|
||||
.PRBS31_EN(PRBS31_EN),
|
||||
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
|
||||
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
|
||||
.STAT_EN(STAT_EN),
|
||||
.STAT_TX_LEVEL(STAT_TX_LEVEL),
|
||||
.STAT_RX_LEVEL(STAT_RX_LEVEL),
|
||||
.STAT_ID_BASE(STAT_ID_BASE),
|
||||
.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD),
|
||||
.STAT_STR_EN(STAT_STR_EN),
|
||||
.STAT_PREFIX_STR(STAT_PREFIX_STR),
|
||||
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
|
||||
.TX_FIFO_RAM_PIPELINE(TX_FIFO_RAM_PIPELINE),
|
||||
.TX_FRAME_FIFO(TX_FRAME_FIFO),
|
||||
.TX_DROP_OVERSIZE_FRAME(TX_DROP_OVERSIZE_FRAME),
|
||||
.TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
|
||||
.TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL),
|
||||
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
|
||||
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
|
||||
.RX_FIFO_RAM_PIPELINE(RX_FIFO_RAM_PIPELINE),
|
||||
.RX_FRAME_FIFO(RX_FRAME_FIFO),
|
||||
.RX_DROP_OVERSIZE_FRAME(RX_DROP_OVERSIZE_FRAME),
|
||||
.RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
|
||||
.RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
|
||||
)
|
||||
uut (
|
||||
.rx_clk(rx_clk),
|
||||
.rx_rst(rx_rst),
|
||||
.tx_clk(tx_clk),
|
||||
.tx_rst(tx_rst),
|
||||
.logic_clk(logic_clk),
|
||||
.logic_rst(logic_rst),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(s_axis_tx),
|
||||
.m_axis_tx_cpl(m_axis_tx_cpl),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(m_axis_rx),
|
||||
|
||||
/*
|
||||
* SERDES interface
|
||||
*/
|
||||
.serdes_tx_data(serdes_tx_data),
|
||||
.serdes_tx_data_k(serdes_tx_data_k),
|
||||
.serdes_tx_data_dm(serdes_tx_data_dm),
|
||||
.serdes_tx_data_dv(serdes_tx_data_dv),
|
||||
.serdes_tx_data_valid(serdes_tx_data_valid),
|
||||
.serdes_tx_gbx_req_sync(serdes_tx_gbx_req_sync),
|
||||
.serdes_tx_gbx_req_stall(serdes_tx_gbx_req_stall),
|
||||
.serdes_tx_gbx_sync(serdes_tx_gbx_sync),
|
||||
.serdes_rx_data(serdes_rx_data),
|
||||
.serdes_rx_data_k(serdes_rx_data_k),
|
||||
.serdes_rx_data_valid(serdes_rx_data_valid),
|
||||
.serdes_rx_reset_req(serdes_rx_reset_req),
|
||||
|
||||
/*
|
||||
* PTP clock
|
||||
*/
|
||||
.ptp_clk(ptp_clk),
|
||||
.ptp_rst(ptp_rst),
|
||||
.ptp_sample_clk(ptp_sample_clk),
|
||||
.ptp_td_sdi(ptp_td_sdi),
|
||||
.ptp_ts_in(ptp_ts_in),
|
||||
.ptp_ts_step_in(ptp_ts_step_in),
|
||||
.tx_ptp_ts_out(tx_ptp_ts_out),
|
||||
.tx_ptp_ts_step_out(tx_ptp_ts_step_out),
|
||||
.tx_ptp_locked(tx_ptp_locked),
|
||||
.rx_ptp_ts_out(rx_ptp_ts_out),
|
||||
.rx_ptp_ts_step_out(rx_ptp_ts_step_out),
|
||||
.rx_ptp_locked(rx_ptp_locked),
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
.stat_clk(stat_clk),
|
||||
.stat_rst(stat_rst),
|
||||
.m_axis_stat(m_axis_stat),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_error_underflow(tx_error_underflow),
|
||||
.tx_fifo_overflow(tx_fifo_overflow),
|
||||
.tx_fifo_bad_frame(tx_fifo_bad_frame),
|
||||
.tx_fifo_good_frame(tx_fifo_good_frame),
|
||||
.rx_error_bad_frame(rx_error_bad_frame),
|
||||
.rx_error_bad_fcs(rx_error_bad_fcs),
|
||||
.rx_bad_block(rx_bad_block),
|
||||
.rx_sequence_error(rx_sequence_error),
|
||||
.rx_block_lock(rx_block_lock),
|
||||
.rx_high_ber(rx_high_ber),
|
||||
.rx_status(rx_status),
|
||||
.rx_fifo_overflow(rx_fifo_overflow),
|
||||
.rx_fifo_bad_frame(rx_fifo_bad_frame),
|
||||
.rx_fifo_good_frame(rx_fifo_good_frame),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_tx_pad_en(cfg_tx_pad_en),
|
||||
.cfg_tx_min_pkt_len(cfg_tx_min_pkt_len),
|
||||
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
|
||||
.cfg_tx_ifg(cfg_tx_ifg),
|
||||
.cfg_tx_enable(cfg_tx_enable),
|
||||
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
|
||||
.cfg_rx_enable(cfg_rx_enable),
|
||||
.cfg_tx_prbs31_enable(cfg_tx_prbs31_enable),
|
||||
.cfg_rx_prbs31_enable(cfg_rx_prbs31_enable)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user