axi: Add AXI RAM module and testbench

Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-12-07 16:28:40 -08:00 · 2025-02-27 00:27:11 -08:00
parent 0632b1982e
commit 55c097f47d
5 changed files with 672 additions and 0 deletions
--- a/README.md
+++ b/README.md
@@ -25,6 +25,7 @@ To facilitate the dual-license model, contributions to the project can only be a
 *  AXI
    *  SV interface for AXI
    *  Register slice
+    *  Single port RAM
 *  AXI lite
    *  SV interface for AXI lite
    *  Register slice