axi: Add AXI RAM module and testbench

Signed-off-by: Alex Forencich <alex@alexforencich.com>

tb/axi/taxi_axi_ram/Makefile

@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2020-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+DUT      = taxi_axi_ram
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += ../../../rtl/axi/$(DUT).sv
+VERILOG_SOURCES += ../../../rtl/axi/taxi_axi_if.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_DATA_W := 32
+export PARAM_ADDR_W := 16
+export PARAM_PIPELINE_OUTPUT := 0
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

tb/axi/taxi_axi_ram/test_taxi_axi_ram.py

@@ -0,0 +1,240 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import random
+
+import cocotb_test.simulator
+import pytest
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge, Timer
+from cocotb.regression import TestFactory
+
+from cocotbext.axi import AxiBus, AxiMaster
+
+
+class TB(object):
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
+
+        self.axi_master = AxiMaster(AxiBus.from_entity(dut.s_axi), dut.clk, dut.rst)
+
+    def set_idle_generator(self, generator=None):
+        if generator:
+            self.axi_master.write_if.aw_channel.set_pause_generator(generator())
+            self.axi_master.write_if.w_channel.set_pause_generator(generator())
+            self.axi_master.read_if.ar_channel.set_pause_generator(generator())
+
+    def set_backpressure_generator(self, generator=None):
+        if generator:
+            self.axi_master.write_if.b_channel.set_pause_generator(generator())
+            self.axi_master.read_if.r_channel.set_pause_generator(generator())
+
+    async def cycle_reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+
+async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, size=None):
+
+    tb = TB(dut)
+
+    byte_lanes = tb.axi_master.write_if.byte_lanes
+    max_burst_size = tb.axi_master.write_if.max_burst_size
+
+    if size is None:
+        size = max_burst_size
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    for length in list(range(1, byte_lanes*2))+[1024]:
+        for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
+            tb.log.info("length %d, offset %d, size %d", length, offset, size)
+            addr = offset+0x1000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            await tb.axi_master.write(addr-4, b'\xaa'*(length+8))
+
+            await tb.axi_master.write(addr, test_data, size=size)
+
+            data = await tb.axi_master.read(addr-1, length+2)
+
+            assert data.data == b'\xaa'+test_data+b'\xaa'
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, size=None):
+
+    tb = TB(dut)
+
+    byte_lanes = tb.axi_master.write_if.byte_lanes
+    max_burst_size = tb.axi_master.write_if.max_burst_size
+
+    if size is None:
+        size = max_burst_size
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    for length in list(range(1, byte_lanes*2))+[1024]:
+        for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
+            tb.log.info("length %d, offset %d, size %d", length, offset, size)
+            addr = offset+0x1000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            await tb.axi_master.write(addr, test_data)
+
+            data = await tb.axi_master.read(addr, length, size=size)
+
+            assert data.data == test_data
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
+
+    tb = TB(dut)
+
+    await tb.cycle_reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    async def worker(master, offset, aperture, count=16):
+        for k in range(count):
+            length = random.randint(1, min(512, aperture))
+            addr = offset+random.randint(0, aperture-length)
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            await Timer(random.randint(1, 100), 'ns')
+
+            await master.write(addr, test_data)
+
+            await Timer(random.randint(1, 100), 'ns')
+
+            data = await master.read(addr, length)
+            assert data.data == test_data
+
+    workers = []
+
+    for k in range(16):
+        workers.append(cocotb.start_soon(worker(tb.axi_master, k*0x1000, 0x1000, count=16)))
+
+    while workers:
+        await workers.pop(0).join()
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+def cycle_pause():
+    return itertools.cycle([1, 1, 1, 0])
+
+
+if cocotb.SIM_NAME:
+
+    data_width = len(cocotb.top.s_axi.wdata)
+    byte_lanes = data_width // 8
+    max_burst_size = (byte_lanes-1).bit_length()
+
+    for test in [run_test_write, run_test_read]:
+
+        factory = TestFactory(test)
+        factory.add_option("idle_inserter", [None, cycle_pause])
+        factory.add_option("backpressure_inserter", [None, cycle_pause])
+        factory.add_option("size", [None]+list(range(max_burst_size)))
+        factory.generate_tests()
+
+    factory = TestFactory(run_stress_test)
+    factory.add_option("idle_inserter", [None, cycle_pause])
+    factory.add_option("backpressure_inserter", [None, cycle_pause])
+    factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize("data_w", [8, 16, 32])
+def test_taxi_axi_ram(request, data_w):
+    dut = "taxi_axi_ram"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, "axi", f"{dut}.sv"),
+        os.path.join(rtl_dir, "axi", "taxi_axi_if.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['DATA_W'] = data_w
+    parameters['ADDR_W'] = 16
+    parameters['ID_W'] = 8
+    parameters['PIPELINE_OUTPUT'] = 0
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

tb/axi/taxi_axi_ram/test_taxi_axi_ram.sv

@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 RAM testbench
+ */
+module test_taxi_axi_ram #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter DATA_W = 32,
+    parameter ADDR_W = 16,
+    parameter ID_W = 8,
+    parameter PIPELINE_OUTPUT = 0
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+logic clk;
+logic rst;
+
+taxi_axi_if #(
+    .DATA_W(DATA_W),
+    .ADDR_W(ADDR_W+16),
+    .ID_W(ID_W)
+) s_axi(), m_axi();
+
+taxi_axi_ram #(
+    .ADDR_W(ADDR_W),
+    .PIPELINE_OUTPUT(PIPELINE_OUTPUT)
+)
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI4-Lite slave interface
+     */
+    .s_axi_wr(s_axi),
+    .s_axi_rd(s_axi)
+);
+
+endmodule
+
+`resetall