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axi: Normalize unpacked dimension

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-03-06 16:16:29 -08:00
parent c422297666
commit 56215865da
3 changed files with 4 additions and 4 deletions
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rtl/axi/taxi_axil_ram.sv
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@@ -67,7 +67,7 @@ logic [DATA_W-1:0] s_axil_rdata_pipe_reg = '0;
logic s_axil_rvalid_pipe_reg = 1'b0;
// (* RAM_STYLE="BLOCK" *)
logic [DATA_W-1:0] mem[(2**VALID_ADDR_W)-1:0];
logic [DATA_W-1:0] mem[2**VALID_ADDR_W];
wire [VALID_ADDR_W-1:0] s_axil_awaddr_valid = VALID_ADDR_W'(s_axil_wr.awaddr >> (ADDR_W - VALID_ADDR_W));
wire [VALID_ADDR_W-1:0] s_axil_araddr_valid = VALID_ADDR_W'(s_axil_rd.araddr >> (ADDR_W - VALID_ADDR_W));