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eth: Normalize signal and register names in MAC modules

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-10-05 18:11:27 -07:00
parent 2810b72147
commit 59a3d5f511
10 changed files with 385 additions and 385 deletions
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14
src/eth/rtl/taxi_axis_xgmii_tx_32.sv
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@@ -161,7 +161,7 @@ logic [TX_TAG_W-1:0] m_axis_tx_cpl_tag_reg = '0, m_axis_tx_cpl_tag_next;
logic m_axis_tx_cpl_valid_reg = 1'b0, m_axis_tx_cpl_valid_next;
logic [31:0] crc_state_reg[4];
wire [31:0] crc_state_next[4];
wire [31:0] crc_state[4];
logic [DATA_W-1:0] xgmii_txd_reg = {CTRL_W{XGMII_IDLE}}, xgmii_txd_next;
logic [CTRL_W-1:0] xgmii_txc_reg = {CTRL_W{1'b1}}, xgmii_txc_next;
@@ -228,7 +228,7 @@ for (genvar n = 0; n < 4; n = n + 1) begin : crc
.data_in(s_tdata_reg[0 +: 8*(n+1)]),
.state_in(crc_state_reg[3]),
.data_out(),
.state_out(crc_state_next[n])
.state_out(crc_state[n])
);
end
@@ -254,7 +254,7 @@ end
always_comb begin
casez (s_empty_reg)
2'd3: begin
fcs_output_txd_0 = {~crc_state_next[0][23:0], s_tdata_reg[7:0]};
fcs_output_txd_0 = {~crc_state[0][23:0], s_tdata_reg[7:0]};
fcs_output_txd_1 = {{2{XGMII_IDLE}}, XGMII_TERM, ~crc_state_reg[0][31:24]};
fcs_output_txc_0 = 4'b0000;
fcs_output_txc_1 = 4'b1110;
@@ -262,7 +262,7 @@ always_comb begin
extra_cycle = 1'b0;
end
2'd2: begin
fcs_output_txd_0 = {~crc_state_next[1][15:0], s_tdata_reg[15:0]};
fcs_output_txd_0 = {~crc_state[1][15:0], s_tdata_reg[15:0]};
fcs_output_txd_1 = {XGMII_IDLE, XGMII_TERM, ~crc_state_reg[1][31:16]};
fcs_output_txc_0 = 4'b0000;
fcs_output_txc_1 = 4'b1100;
@@ -270,7 +270,7 @@ always_comb begin
extra_cycle = 1'b0;
end
2'd1: begin
fcs_output_txd_0 = {~crc_state_next[2][7:0], s_tdata_reg[23:0]};
fcs_output_txd_0 = {~crc_state[2][7:0], s_tdata_reg[23:0]};
fcs_output_txd_1 = {XGMII_TERM, ~crc_state_reg[2][31:8]};
fcs_output_txc_0 = 4'b0000;
fcs_output_txc_1 = 4'b1000;
@@ -693,12 +693,12 @@ always_ff @(posedge clk) begin
// gearbox stall
end else begin
for (integer i = 0; i < 3; i = i + 1) begin
crc_state_reg[i] <= crc_state_next[i];
crc_state_reg[i] <= crc_state[i];
end
end
if (update_crc) begin
crc_state_reg[3] <= crc_state_next[3];
crc_state_reg[3] <= crc_state[3];
end
if (reset_crc) begin