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eth: Normalize signal and register names in MAC modules

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-10-05 18:11:27 -07:00
parent 2810b72147
commit 59a3d5f511
10 changed files with 385 additions and 385 deletions
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134
src/eth/rtl/taxi_axis_baser_rx_32.sv
View File

@@ -152,14 +152,14 @@ logic [1:0] term_lane_reg = 0;
logic [1:0] term_lane_d0_reg = 0;
logic framing_error_reg = 1'b0;
logic [DATA_W-1:0] input_data_d0 = '0;
logic [DATA_W-1:0] input_data_d1 = '0;
logic [DATA_W-1:0] input_data_d2 = '0;
logic [DATA_W-1:0] input_data_d0_reg = '0;
logic [DATA_W-1:0] input_data_d1_reg = '0;
logic [DATA_W-1:0] input_data_d2_reg = '0;
logic input_start_alt = 1'b0;
logic input_start_d0 = 1'b0;
logic input_start_d1 = 1'b0;
logic input_start_d2 = 1'b0;
logic input_start_alt_reg = 1'b0;
logic input_start_d0_reg = 1'b0;
logic input_start_d1_reg = 1'b0;
logic input_start_d2_reg = 1'b0;
logic [DATA_W-1:0] encoded_rx_data_reg = '0;
logic encoded_rx_data_valid_reg = 1'b0;
@@ -206,15 +206,15 @@ logic [PTP_TS_W-1:0] ptp_ts_out_reg = '0, ptp_ts_out_next;
logic [31:0] crc_state_reg = '1;
wire [31:0] crc_state_next;
wire [31:0] crc_state;
wire [3:0] crc_valid;
logic [3:0] crc_valid_save;
logic [3:0] crc_valid_reg = '0;
assign crc_valid[3] = crc_state_next == ~32'h2144df1c;
assign crc_valid[2] = crc_state_next == ~32'hc622f71d;
assign crc_valid[1] = crc_state_next == ~32'hb1c2a1a3;
assign crc_valid[0] = crc_state_next == ~32'h9d6cdf7e;
assign crc_valid[3] = crc_state == ~32'h2144df1c;
assign crc_valid[2] = crc_state == ~32'hc622f71d;
assign crc_valid[1] = crc_state == ~32'hb1c2a1a3;
assign crc_valid[0] = crc_state == ~32'h9d6cdf7e;
assign m_axis_rx.tdata = m_axis_rx_tdata_reg;
assign m_axis_rx.tkeep = m_axis_rx_tkeep_reg;
@@ -259,10 +259,10 @@ taxi_lfsr #(
.DATA_OUT_EN(1'b0)
)
eth_crc (
.data_in(input_data_d0),
.data_in(input_data_d0_reg),
.state_in(crc_state_reg),
.data_out(),
.state_out(crc_state_next)
.state_out(crc_state)
);
always_comb begin
@@ -281,7 +281,7 @@ always_comb begin
frame_len_lim_last_next = frame_len_lim_last_reg;
frame_len_lim_check_next = frame_len_lim_check_reg;
m_axis_rx_tdata_next = input_data_d2;
m_axis_rx_tdata_next = input_data_d2_reg;
m_axis_rx_tkeep_next = {KEEP_W{1'b1}};
m_axis_rx_tvalid_next = 1'b0;
m_axis_rx_tlast_next = 1'b0;
@@ -339,11 +339,11 @@ always_comb begin
case (hdr_ptr_reg)
3'd0: begin
is_mcast_next = input_data_d2[0];
is_bcast_next = &input_data_d2;
is_mcast_next = input_data_d2_reg[0];
is_bcast_next = &input_data_d2_reg;
end
3'd1: is_bcast_next = is_bcast_reg && &input_data_d2[15:0];
3'd3: is_8021q_next = {input_data_d2[7:0], input_data_d2[15:8]} == 16'h8100;
3'd1: is_bcast_next = is_bcast_reg && &input_data_d2_reg[15:0];
3'd3: is_8021q_next = {input_data_d2_reg[7:0], input_data_d2_reg[15:8]} == 16'h8100;
default: begin
// do nothing
end
@@ -360,9 +360,9 @@ always_comb begin
frame_len_lim_check_next = 1'b0;
hdr_ptr_next = 0;
pre_ok_next = input_data_d2[31:8] == 24'h555555;
pre_ok_next = input_data_d2_reg[31:8] == 24'h555555;
if (input_start_d2 && cfg_rx_enable) begin
if (input_start_d2_reg && cfg_rx_enable) begin
// start condition
if (framing_error_reg) begin
// control or error characters in first data word
@@ -385,7 +385,7 @@ always_comb begin
hdr_ptr_next = 0;
pre_ok_next = pre_ok_reg && input_data_d2 == 32'hD5555555;
pre_ok_next = pre_ok_reg && input_data_d2_reg == 32'hD5555555;
if (framing_error_reg) begin
// control or error characters in packet
@@ -399,7 +399,7 @@ always_comb begin
end
STATE_PAYLOAD: begin
// read payload
m_axis_rx_tdata_next = input_data_d2;
m_axis_rx_tdata_next = input_data_d2_reg;
m_axis_rx_tkeep_next = {KEEP_W{1'b1}};
m_axis_rx_tvalid_next = 1'b1;
m_axis_rx_tlast_next = 1'b0;
@@ -441,7 +441,7 @@ always_comb begin
// end this cycle
m_axis_rx_tkeep_next = 4'b1111;
m_axis_rx_tlast_next = 1'b1;
if (crc_valid_save[3]) begin
if (crc_valid_reg[3]) begin
// CRC valid
if (frame_oversize_next) begin
// too long
@@ -477,7 +477,7 @@ always_comb begin
end
STATE_LAST: begin
// last cycle of packet
m_axis_rx_tdata_next = input_data_d2;
m_axis_rx_tdata_next = input_data_d2_reg;
m_axis_rx_tkeep_next = {KEEP_W{1'b1}} >> 2'(KEEP_W-term_lane_d0_reg);
m_axis_rx_tvalid_next = 1'b1;
m_axis_rx_tlast_next = 1'b1;
@@ -485,9 +485,9 @@ always_comb begin
reset_crc = 1'b1;
if ((term_lane_d0_reg == 1 && crc_valid_save[0]) ||
(term_lane_d0_reg == 2 && crc_valid_save[1]) ||
(term_lane_d0_reg == 3 && crc_valid_save[2])) begin
if ((term_lane_d0_reg == 1 && crc_valid_reg[0]) ||
(term_lane_d0_reg == 2 && crc_valid_reg[1]) ||
(term_lane_d0_reg == 3 && crc_valid_reg[2])) begin
// CRC valid
if (frame_oversize_reg) begin
// too long
@@ -578,64 +578,64 @@ always_ff @(posedge clk) begin
term_lane_reg <= term_lane_alt_reg;
term_lane_d0_reg <= term_lane_reg;
input_data_d0 <= encoded_rx_data_reg;
input_data_d1 <= input_data_d0;
input_data_d2 <= input_data_d1;
input_data_d0_reg <= encoded_rx_data_reg;
input_data_d1_reg <= input_data_d0_reg;
input_data_d2_reg <= input_data_d1_reg;
input_start_alt <= 1'b0;
input_start_d0 <= input_start_alt;
input_start_d1 <= input_start_d0;
input_start_d2 <= input_start_d1;
input_start_alt_reg <= 1'b0;
input_start_d0_reg <= input_start_alt_reg;
input_start_d1_reg <= input_start_d0_reg;
input_start_d2_reg <= input_start_d1_reg;
if (encoded_rx_hdr_valid_reg) begin
// portion with header
if (encoded_rx_hdr_reg[0] == 0) begin
// data
input_data_d0 <= encoded_rx_data_reg;
input_data_d0_reg <= encoded_rx_data_reg;
framing_error_reg <= !frame_reg;
end else begin
// control
case (encoded_rx_data_reg[7:4])
BLOCK_TYPE_CTRL[7:4]: begin
input_data_d0 <= encoded_rx_data_reg;
input_data_d0_reg <= encoded_rx_data_reg;
framing_error_reg <= frame_reg;
frame_reg <= 1'b0;
end
BLOCK_TYPE_OS_4[7:4]: begin
input_data_d0 <= encoded_rx_data_reg;
input_data_d0_reg <= encoded_rx_data_reg;
framing_error_reg <= frame_reg;
frame_reg <= 1'b0;
end
BLOCK_TYPE_START_4[7:4]: begin
input_data_d0 <= encoded_rx_data_reg;
input_start_alt <= 1'b1;
input_data_d0_reg <= encoded_rx_data_reg;
input_start_alt_reg <= 1'b1;
framing_error_reg <= frame_reg;
frame_reg <= 1'b1;
end
BLOCK_TYPE_OS_START[7:4]: begin
input_data_d0 <= encoded_rx_data_reg;
input_start_alt <= 1'b1;
input_data_d0_reg <= encoded_rx_data_reg;
input_start_alt_reg <= 1'b1;
framing_error_reg <= frame_reg;
frame_reg <= 1'b1;
end
BLOCK_TYPE_OS_04[7:4]: begin
input_data_d0 <= encoded_rx_data_reg;
input_data_d0_reg <= encoded_rx_data_reg;
framing_error_reg <= frame_reg;
frame_reg <= 1'b0;
end
BLOCK_TYPE_START_0[7:4]: begin
input_data_d0 <= encoded_rx_data_reg;
input_start_d0 <= 1'b1;
input_data_d0_reg <= encoded_rx_data_reg;
input_start_d0_reg <= 1'b1;
framing_error_reg <= frame_reg;
frame_reg <= 1'b1;
end
BLOCK_TYPE_OS_0[7:4]: begin
input_data_d0 <= encoded_rx_data_reg;
input_data_d0_reg <= encoded_rx_data_reg;
framing_error_reg <= frame_reg;
frame_reg <= 1'b0;
end
BLOCK_TYPE_TERM_0[7:4]: begin
input_data_d0 <= encoded_rx_data_reg; // don't care
input_data_d0_reg <= encoded_rx_data_reg; // don't care
term_present_reg <= 1'b1;
term_first_cycle_reg <= 1'b1;
term_lane_reg <= 0;
@@ -643,28 +643,28 @@ always_ff @(posedge clk) begin
frame_reg <= 1'b0;
end
BLOCK_TYPE_TERM_1[7:4]: begin
input_data_d0 <= {24'd0, encoded_rx_data_reg[15:8]};
input_data_d0_reg <= {24'd0, encoded_rx_data_reg[15:8]};
term_present_reg <= 1'b1;
term_lane_reg <= 1;
framing_error_reg <= !frame_reg;
frame_reg <= 1'b0;
end
BLOCK_TYPE_TERM_2[7:4]: begin
input_data_d0 <= {16'd0, encoded_rx_data_reg[23:8]};
input_data_d0_reg <= {16'd0, encoded_rx_data_reg[23:8]};
term_present_reg <= 1'b1;
term_lane_reg <= 2;
framing_error_reg <= !frame_reg;
frame_reg <= 1'b0;
end
BLOCK_TYPE_TERM_3[7:4]: begin
input_data_d0 <= {8'd0, encoded_rx_data_reg[31:8]};
input_data_d0_reg <= {8'd0, encoded_rx_data_reg[31:8]};
term_present_reg <= 1'b1;
term_lane_reg <= 3;
framing_error_reg <= !frame_reg;
frame_reg <= 1'b0;
end
BLOCK_TYPE_TERM_4[7:4]: begin
input_data_d0 <= {encoded_rx_data[7:0], encoded_rx_data_reg[31:8]};
input_data_d0_reg <= {encoded_rx_data[7:0], encoded_rx_data_reg[31:8]};
term_present_alt_reg <= 1'b1;
term_first_cycle_alt_reg <= 1'b1;
term_lane_alt_reg <= 0;
@@ -672,21 +672,21 @@ always_ff @(posedge clk) begin
frame_reg <= 1'b0;
end
BLOCK_TYPE_TERM_5[7:4]: begin
input_data_d0 <= {encoded_rx_data[7:0], encoded_rx_data_reg[31:8]};
input_data_d0_reg <= {encoded_rx_data[7:0], encoded_rx_data_reg[31:8]};
term_present_alt_reg <= 1'b1;
term_lane_alt_reg <= 1;
framing_error_reg <= !frame_reg;
frame_reg <= 1'b0;
end
BLOCK_TYPE_TERM_6[7:4]: begin
input_data_d0 <= {encoded_rx_data[7:0], encoded_rx_data_reg[31:8]};
input_data_d0_reg <= {encoded_rx_data[7:0], encoded_rx_data_reg[31:8]};
term_present_alt_reg <= 1'b1;
term_lane_alt_reg <= 2;
framing_error_reg <= !frame_reg;
frame_reg <= 1'b0;
end
BLOCK_TYPE_TERM_7[7:4]: begin
input_data_d0 <= {encoded_rx_data[7:0], encoded_rx_data_reg[31:8]};
input_data_d0_reg <= {encoded_rx_data[7:0], encoded_rx_data_reg[31:8]};
term_present_alt_reg <= 1'b1;
term_lane_alt_reg <= 3;
framing_error_reg <= !frame_reg;
@@ -694,7 +694,7 @@ always_ff @(posedge clk) begin
end
default: begin
// invalid block type
input_data_d0 <= encoded_rx_data_reg;
input_data_d0_reg <= encoded_rx_data_reg;
framing_error_reg <= frame_reg;
frame_reg <= 1'b0;
end
@@ -732,13 +732,13 @@ always_ff @(posedge clk) begin
stat_rx_err_bad_block_reg <= 1'b1;
end
end else begin
input_data_d0 <= encoded_rx_data_reg;
input_data_d0_reg <= encoded_rx_data_reg;
if (term_present_alt_reg) begin
case (term_lane_alt_reg)
1: input_data_d0 <= {24'd0, encoded_rx_data_reg[15:8]};
2: input_data_d0 <= {16'd0, encoded_rx_data_reg[23:8]};
3: input_data_d0 <= {8'd0, encoded_rx_data_reg[31:8]};
default: input_data_d0 <= encoded_rx_data_reg;
1: input_data_d0_reg <= {24'd0, encoded_rx_data_reg[15:8]};
2: input_data_d0_reg <= {16'd0, encoded_rx_data_reg[23:8]};
3: input_data_d0_reg <= {8'd0, encoded_rx_data_reg[31:8]};
default: input_data_d0_reg <= encoded_rx_data_reg;
endcase
end
end
@@ -746,10 +746,10 @@ always_ff @(posedge clk) begin
if (reset_crc) begin
crc_state_reg <= '1;
end else begin
crc_state_reg <= crc_state_next;
crc_state_reg <= crc_state;
end
crc_valid_save <= crc_valid;
crc_valid_reg <= crc_valid;
end
if (rst) begin
@@ -776,10 +776,10 @@ always_ff @(posedge clk) begin
stat_rx_err_framing_reg <= 1'b0;
stat_rx_err_preamble_reg <= 1'b0;
input_start_alt <= 1'b0;
input_start_d0 <= 1'b0;
input_start_d1 <= 1'b0;
input_start_d2 <= 1'b0;
input_start_alt_reg <= 1'b0;
input_start_d0_reg <= 1'b0;
input_start_d1_reg <= 1'b0;
input_start_d2_reg <= 1'b0;
end
end

106
src/eth/rtl/taxi_axis_baser_rx_64.sv
View File

@@ -143,8 +143,8 @@ logic [1:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
logic reset_crc;
logic lanes_swapped = 1'b0;
logic [31:0] swap_data = 32'd0;
logic lanes_swapped_reg = 1'b0;
logic [31:0] swap_data_reg = 32'd0;
logic [2:0] term_lane_alt_reg = 0;
logic [2:0] term_lane_reg = 0;
@@ -155,12 +155,12 @@ logic term_first_cycle_alt_reg = 1'b0;
logic term_first_cycle_reg = 1'b0;
logic framing_error_reg = 1'b0, framing_error_d0_reg = 1'b0;
logic [DATA_W-1:0] input_data_d0 = '0;
logic [DATA_W-1:0] input_data_d1 = '0;
logic [DATA_W-1:0] input_data_d0_reg = '0;
logic [DATA_W-1:0] input_data_d1_reg = '0;
logic input_start_swap = 1'b0;
logic input_start_d0 = 1'b0;
logic input_start_d1 = 1'b0;
logic input_start_swap_reg = 1'b0;
logic input_start_d0_reg = 1'b0;
logic input_start_d1_reg = 1'b0;
logic frame_oversize_reg = 1'b0, frame_oversize_next;
logic pre_ok_reg = 1'b0, pre_ok_next;
@@ -205,19 +205,19 @@ logic ptp_ts_borrow_reg = '0;
logic [31:0] crc_state_reg = '1;
wire [31:0] crc_state_next;
wire [31:0] crc_state;
wire [7:0] crc_valid;
logic [7:0] crc_valid_save;
logic [7:0] crc_valid_reg = '0;
assign crc_valid[7] = crc_state_next == ~32'h2144df1c;
assign crc_valid[6] = crc_state_next == ~32'hc622f71d;
assign crc_valid[5] = crc_state_next == ~32'hb1c2a1a3;
assign crc_valid[4] = crc_state_next == ~32'h9d6cdf7e;
assign crc_valid[3] = crc_state_next == ~32'h6522df69;
assign crc_valid[2] = crc_state_next == ~32'he60914ae;
assign crc_valid[1] = crc_state_next == ~32'he38a6876;
assign crc_valid[0] = crc_state_next == ~32'h6b87b1ec;
assign crc_valid[7] = crc_state == ~32'h2144df1c;
assign crc_valid[6] = crc_state == ~32'hc622f71d;
assign crc_valid[5] = crc_state == ~32'hb1c2a1a3;
assign crc_valid[4] = crc_state == ~32'h9d6cdf7e;
assign crc_valid[3] = crc_state == ~32'h6522df69;
assign crc_valid[2] = crc_state == ~32'he60914ae;
assign crc_valid[1] = crc_state == ~32'he38a6876;
assign crc_valid[0] = crc_state == ~32'h6b87b1ec;
logic [4+16-1:0] last_ts_reg = '0;
logic [4+16-1:0] ts_inc_reg = '0;
@@ -263,10 +263,10 @@ taxi_lfsr #(
.DATA_OUT_EN(1'b0)
)
eth_crc (
.data_in(input_data_d0),
.data_in(input_data_d0_reg),
.state_in(crc_state_reg),
.data_out(),
.state_out(crc_state_next)
.state_out(crc_state)
);
// Mask input data
@@ -312,7 +312,7 @@ always_comb begin
frame_len_lim_last_next = frame_len_lim_last_reg;
frame_len_lim_check_next = frame_len_lim_check_reg;
m_axis_rx_tdata_next = input_data_d1;
m_axis_rx_tdata_next = input_data_d1_reg;
m_axis_rx_tkeep_next = 8'd0;
m_axis_rx_tvalid_next = 1'b0;
m_axis_rx_tlast_next = 1'b0;
@@ -369,10 +369,10 @@ always_comb begin
case (hdr_ptr_reg)
2'd0: begin
is_mcast_next = input_data_d1[0];
is_bcast_next = &input_data_d1[47:0];
is_mcast_next = input_data_d1_reg[0];
is_bcast_next = &input_data_d1_reg[47:0];
end
2'd1: is_8021q_next = {input_data_d1[39:32], input_data_d1[47:40]} == 16'h8100;
2'd1: is_8021q_next = {input_data_d1_reg[39:32], input_data_d1_reg[47:40]} == 16'h8100;
default: begin
// do nothing
end
@@ -389,9 +389,9 @@ always_comb begin
frame_len_lim_check_next = 1'b0;
hdr_ptr_next = 0;
pre_ok_next = input_data_d1[63:8] == 56'hD5555555555555;
pre_ok_next = input_data_d1_reg[63:8] == 56'hD5555555555555;
if (input_start_d1 && cfg_rx_enable) begin
if (input_start_d1_reg && cfg_rx_enable) begin
// start condition
reset_crc = 1'b0;
stat_rx_byte_next = 4'(KEEP_W);
@@ -402,7 +402,7 @@ always_comb begin
end
STATE_PAYLOAD: begin
// read payload
m_axis_rx_tdata_next = input_data_d1;
m_axis_rx_tdata_next = input_data_d1_reg;
m_axis_rx_tkeep_next = 8'hff;
m_axis_rx_tvalid_next = 1'b1;
m_axis_rx_tlast_next = 1'b0;
@@ -450,7 +450,7 @@ always_comb begin
// end this cycle
m_axis_rx_tkeep_next = {KEEP_W{1'b1}} >> 3'(KEEP_W-4-term_lane_reg);
m_axis_rx_tlast_next = 1'b1;
if ((term_lane_reg == 0 && crc_valid_save[7]) ||
if ((term_lane_reg == 0 && crc_valid_reg[7]) ||
(term_lane_reg == 1 && crc_valid[0]) ||
(term_lane_reg == 2 && crc_valid[1]) ||
(term_lane_reg == 3 && crc_valid[2]) ||
@@ -492,7 +492,7 @@ always_comb begin
end
STATE_LAST: begin
// last cycle of packet
m_axis_rx_tdata_next = input_data_d1;
m_axis_rx_tdata_next = input_data_d1_reg;
m_axis_rx_tkeep_next = {KEEP_W{1'b1}} >> 3'(KEEP_W-4-term_lane_d0_reg);
m_axis_rx_tvalid_next = 1'b1;
m_axis_rx_tlast_next = 1'b1;
@@ -500,9 +500,9 @@ always_comb begin
reset_crc = 1'b1;
if ((term_lane_d0_reg == 5 && crc_valid_save[4]) ||
(term_lane_d0_reg == 6 && crc_valid_save[5]) ||
(term_lane_d0_reg == 7 && crc_valid_save[6])) begin
if ((term_lane_d0_reg == 5 && crc_valid_reg[4]) ||
(term_lane_d0_reg == 6 && crc_valid_reg[5]) ||
(term_lane_d0_reg == 7 && crc_valid_reg[6])) begin
// CRC valid
if (frame_oversize_reg) begin
// too long
@@ -580,10 +580,10 @@ always_ff @(posedge clk) begin
stat_rx_err_preamble_reg <= stat_rx_err_preamble_next;
if (!GBX_IF_EN || encoded_rx_data_valid) begin
swap_data <= encoded_rx_data_masked[63:32];
swap_data_reg <= encoded_rx_data_masked[63:32];
input_start_swap <= 1'b0;
input_start_d0 <= input_start_swap;
input_start_swap_reg <= 1'b0;
input_start_d0_reg <= input_start_swap_reg;
term_present_alt_reg <= 1'b0;
term_present_reg <= term_present_alt_reg;
@@ -602,7 +602,7 @@ always_ff @(posedge clk) begin
end
// lane swapping and termination character detection
if (lanes_swapped) begin
if (lanes_swapped_reg) begin
if (!term_present_alt_reg && encoded_rx_hdr[0] == SYNC_CTRL[0]) begin
case (encoded_rx_data[7:4])
BLOCK_TYPE_TERM_0[7:4]: begin
@@ -649,9 +649,9 @@ always_ff @(posedge clk) begin
end
if (term_present_alt_reg) begin
// mask off trailing data
input_data_d0 <= {32'd0, swap_data};
input_data_d0_reg <= {32'd0, swap_data_reg};
end else begin
input_data_d0 <= {encoded_rx_data_masked[31:0], swap_data};
input_data_d0_reg <= {encoded_rx_data_masked[31:0], swap_data_reg};
end
end else begin
if (encoded_rx_hdr[0] == SYNC_CTRL[0]) begin
@@ -698,17 +698,17 @@ always_ff @(posedge clk) begin
end
endcase
end
input_data_d0 <= encoded_rx_data_masked;
input_data_d0_reg <= encoded_rx_data_masked;
end
// start control character detection
if (encoded_rx_hdr == SYNC_CTRL && encoded_rx_data[7:0] == BLOCK_TYPE_START_0) begin
lanes_swapped <= 1'b0;
input_start_d0 <= 1'b1;
input_data_d0 <= encoded_rx_data_masked;
lanes_swapped_reg <= 1'b0;
input_start_d0_reg <= 1'b1;
input_data_d0_reg <= encoded_rx_data_masked;
end else if (encoded_rx_hdr == SYNC_CTRL && (encoded_rx_data[7:0] == BLOCK_TYPE_START_4 || encoded_rx_data[7:0] == BLOCK_TYPE_OS_START)) begin
lanes_swapped <= 1'b1;
input_start_swap <= 1'b1;
lanes_swapped_reg <= 1'b1;
input_start_swap_reg <= 1'b1;
end
// check for framing errors
@@ -812,7 +812,7 @@ always_ff @(posedge clk) begin
end
// capture timestamps
if (input_start_swap) begin
if (input_start_swap_reg) begin
start_packet_reg <= 2'b10;
if (PTP_TS_FMT_TOD) begin
ptp_ts_reg[45:0] <= ptp_ts[45:0] + 46'(ts_inc_reg >> 1);
@@ -822,21 +822,21 @@ always_ff @(posedge clk) begin
end
end
if (input_start_d0 && !lanes_swapped) begin
if (input_start_d0_reg && !lanes_swapped_reg) begin
start_packet_reg <= 2'b01;
ptp_ts_reg <= ptp_ts;
end
input_start_d1 <= input_start_d0;
input_data_d1 <= input_data_d0;
input_start_d1_reg <= input_start_d0_reg;
input_data_d1_reg <= input_data_d0_reg;
if (reset_crc) begin
crc_state_reg <= '1;
end else begin
crc_state_reg <= crc_state_next;
crc_state_reg <= crc_state;
end
crc_valid_save <= crc_valid;
crc_valid_reg <= crc_valid;
end
last_ts_reg <= (4+16)'(ptp_ts);
@@ -866,11 +866,11 @@ always_ff @(posedge clk) begin
stat_rx_err_framing_reg <= 1'b0;
stat_rx_err_preamble_reg <= 1'b0;
input_start_swap <= 1'b0;
input_start_d0 <= 1'b0;
input_start_d1 <= 1'b0;
input_start_swap_reg <= 1'b0;
input_start_d0_reg <= 1'b0;
input_start_d1_reg <= 1'b0;
lanes_swapped <= 1'b0;
lanes_swapped_reg <= 1'b0;
end
end

14
src/eth/rtl/taxi_axis_baser_tx_32.sv
View File

@@ -205,7 +205,7 @@ logic [TX_TAG_W-1:0] m_axis_tx_cpl_tag_reg = '0, m_axis_tx_cpl_tag_next;
logic m_axis_tx_cpl_valid_reg = 1'b0, m_axis_tx_cpl_valid_next;
logic [31:0] crc_state_reg[4];
wire [31:0] crc_state_next[4];
wire [31:0] crc_state[4];
logic [DATA_W-1:0] encoded_tx_data_reg = {24'd0, BLOCK_TYPE_CTRL};
logic encoded_tx_data_valid_reg = 1'b0;
@@ -279,7 +279,7 @@ for (genvar n = 0; n < 4; n = n + 1) begin : crc
.data_in(s_tdata_reg[0 +: 8*(n+1)]),
.state_in(crc_state_reg[3]),
.data_out(),
.state_out(crc_state_next[n])
.state_out(crc_state[n])
);
end
@@ -305,7 +305,7 @@ end
always_comb begin
casez (s_empty_reg)
2'd3: begin
fcs_output_data_0 = {~crc_state_next[0][23:0], s_tdata_reg[7:0]};
fcs_output_data_0 = {~crc_state[0][23:0], s_tdata_reg[7:0]};
fcs_output_data_1 = {24'd0, ~crc_state_reg[0][31:24]};
fcs_output_type_0 = OUTPUT_TYPE_DATA;
fcs_output_type_1 = OUTPUT_TYPE_TERM_1;
@@ -313,7 +313,7 @@ always_comb begin
extra_cycle = 1'b0;
end
2'd2: begin
fcs_output_data_0 = {~crc_state_next[1][15:0], s_tdata_reg[15:0]};
fcs_output_data_0 = {~crc_state[1][15:0], s_tdata_reg[15:0]};
fcs_output_data_1 = {16'd0, ~crc_state_reg[1][31:16]};
fcs_output_type_0 = OUTPUT_TYPE_DATA;
fcs_output_type_1 = OUTPUT_TYPE_TERM_2;
@@ -321,7 +321,7 @@ always_comb begin
extra_cycle = 1'b0;
end
2'd1: begin
fcs_output_data_0 = {~crc_state_next[2][7:0], s_tdata_reg[23:0]};
fcs_output_data_0 = {~crc_state[2][7:0], s_tdata_reg[23:0]};
fcs_output_data_1 = {8'd0, ~crc_state_reg[2][31:8]};
fcs_output_type_0 = OUTPUT_TYPE_DATA;
fcs_output_type_1 = OUTPUT_TYPE_TERM_3;
@@ -858,11 +858,11 @@ always_ff @(posedge clk) begin
end
for (integer i = 0; i < 3; i = i + 1) begin
crc_state_reg[i] <= crc_state_next[i];
crc_state_reg[i] <= crc_state[i];
end
if (update_crc) begin
crc_state_reg[3] <= crc_state_next[3];
crc_state_reg[3] <= crc_state[3];
end
if (reset_crc) begin

50
src/eth/rtl/taxi_axis_baser_tx_64.sv
View File

@@ -175,7 +175,7 @@ logic update_crc;
logic swap_lanes_reg = 1'b0, swap_lanes_next;
logic swap_lanes_d1_reg = 1'b0;
logic [31:0] swap_data = 32'd0;
logic [31:0] swap_data_reg = 32'd0;
logic output_data_finish_reg = 1'b0;
@@ -217,7 +217,7 @@ logic m_axis_tx_cpl_valid_int_reg = 1'b0;
logic m_axis_tx_cpl_ts_borrow_reg = 1'b0;
logic [31:0] crc_state_reg[8];
wire [31:0] crc_state_next[8];
wire [31:0] crc_state[8];
logic [DATA_W-1:0] encoded_tx_data_reg = {{8{CTRL_IDLE}}, BLOCK_TYPE_CTRL};
logic encoded_tx_data_valid_reg = 1'b0;
@@ -292,7 +292,7 @@ for (genvar n = 0; n < 8; n = n + 1) begin : crc
.data_in(s_tdata_reg[0 +: 8*(n+1)]),
.state_in(crc_state_reg[7]),
.data_out(),
.state_out(crc_state_next[n])
.state_out(crc_state[n])
);
end
@@ -322,49 +322,49 @@ end
always_comb begin
casez (s_empty_reg)
3'd7: begin
fcs_output_data_0 = {24'd0, ~crc_state_next[0][31:0], s_tdata_reg[7:0]};
fcs_output_data_0 = {24'd0, ~crc_state[0][31:0], s_tdata_reg[7:0]};
fcs_output_data_1 = 64'd0;
fcs_output_type_0 = OUTPUT_TYPE_TERM_5;
fcs_output_type_1 = OUTPUT_TYPE_IDLE;
ifg_offset = 8'd3;
end
3'd6: begin
fcs_output_data_0 = {16'd0, ~crc_state_next[1][31:0], s_tdata_reg[15:0]};
fcs_output_data_0 = {16'd0, ~crc_state[1][31:0], s_tdata_reg[15:0]};
fcs_output_data_1 = 64'd0;
fcs_output_type_0 = OUTPUT_TYPE_TERM_6;
fcs_output_type_1 = OUTPUT_TYPE_IDLE;
ifg_offset = 8'd2;
end
3'd5: begin
fcs_output_data_0 = {8'd0, ~crc_state_next[2][31:0], s_tdata_reg[23:0]};
fcs_output_data_0 = {8'd0, ~crc_state[2][31:0], s_tdata_reg[23:0]};
fcs_output_data_1 = 64'd0;
fcs_output_type_0 = OUTPUT_TYPE_TERM_7;
fcs_output_type_1 = OUTPUT_TYPE_IDLE;
ifg_offset = 8'd1;
end
3'd4: begin
fcs_output_data_0 = {~crc_state_next[3][31:0], s_tdata_reg[31:0]};
fcs_output_data_0 = {~crc_state[3][31:0], s_tdata_reg[31:0]};
fcs_output_data_1 = 64'd0;
fcs_output_type_0 = OUTPUT_TYPE_DATA;
fcs_output_type_1 = OUTPUT_TYPE_TERM_0;
ifg_offset = 8'd8;
end
3'd3: begin
fcs_output_data_0 = {~crc_state_next[4][23:0], s_tdata_reg[39:0]};
fcs_output_data_0 = {~crc_state[4][23:0], s_tdata_reg[39:0]};
fcs_output_data_1 = {56'd0, ~crc_state_reg[4][31:24]};
fcs_output_type_0 = OUTPUT_TYPE_DATA;
fcs_output_type_1 = OUTPUT_TYPE_TERM_1;
ifg_offset = 8'd7;
end
3'd2: begin
fcs_output_data_0 = {~crc_state_next[5][15:0], s_tdata_reg[47:0]};
fcs_output_data_0 = {~crc_state[5][15:0], s_tdata_reg[47:0]};
fcs_output_data_1 = {48'd0, ~crc_state_reg[5][31:16]};
fcs_output_type_0 = OUTPUT_TYPE_DATA;
fcs_output_type_1 = OUTPUT_TYPE_TERM_2;
ifg_offset = 8'd6;
end
3'd1: begin
fcs_output_data_0 = {~crc_state_next[6][7:0], s_tdata_reg[55:0]};
fcs_output_data_0 = {~crc_state[6][7:0], s_tdata_reg[55:0]};
fcs_output_data_1 = {40'd0, ~crc_state_reg[6][31:8]};
fcs_output_type_0 = OUTPUT_TYPE_DATA;
fcs_output_type_1 = OUTPUT_TYPE_TERM_3;
@@ -796,7 +796,7 @@ always_ff @(posedge clk) begin
end else begin
output_data_finish_reg <= 1'b0;
swap_data <= output_data_reg[63:32];
swap_data_reg <= output_data_reg[63:32];
output_data_reg <= output_data_next;
output_type_reg <= output_type_next;
@@ -844,15 +844,15 @@ always_ff @(posedge clk) begin
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_5: begin
encoded_tx_data_reg <= {{6{CTRL_IDLE}}, 6'd0, swap_data[7:0], BLOCK_TYPE_TERM_1};
encoded_tx_data_reg <= {{6{CTRL_IDLE}}, 6'd0, swap_data_reg[7:0], BLOCK_TYPE_TERM_1};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_6: begin
encoded_tx_data_reg <= {{5{CTRL_IDLE}}, 5'd0, swap_data[15:0], BLOCK_TYPE_TERM_2};
encoded_tx_data_reg <= {{5{CTRL_IDLE}}, 5'd0, swap_data_reg[15:0], BLOCK_TYPE_TERM_2};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_7: begin
encoded_tx_data_reg <= {{4{CTRL_IDLE}}, 4'd0, swap_data[23:0], BLOCK_TYPE_TERM_3};
encoded_tx_data_reg <= {{4{CTRL_IDLE}}, 4'd0, swap_data_reg[23:0], BLOCK_TYPE_TERM_3};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
default: begin
@@ -875,45 +875,45 @@ always_ff @(posedge clk) begin
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_DATA: begin
encoded_tx_data_reg <= {output_data_reg[31:0], swap_data};
encoded_tx_data_reg <= {output_data_reg[31:0], swap_data_reg};
encoded_tx_hdr_reg <= SYNC_DATA;
end
OUTPUT_TYPE_TERM_0: begin
encoded_tx_data_reg <= {{3{CTRL_IDLE}}, 3'd0, swap_data, BLOCK_TYPE_TERM_4};
encoded_tx_data_reg <= {{3{CTRL_IDLE}}, 3'd0, swap_data_reg, BLOCK_TYPE_TERM_4};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_1: begin
encoded_tx_data_reg <= {{2{CTRL_IDLE}}, 2'd0, output_data_reg[7:0], swap_data, BLOCK_TYPE_TERM_5};
encoded_tx_data_reg <= {{2{CTRL_IDLE}}, 2'd0, output_data_reg[7:0], swap_data_reg, BLOCK_TYPE_TERM_5};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_2: begin
encoded_tx_data_reg <= {{1{CTRL_IDLE}}, 1'd0, output_data_reg[15:0], swap_data, BLOCK_TYPE_TERM_6};
encoded_tx_data_reg <= {{1{CTRL_IDLE}}, 1'd0, output_data_reg[15:0], swap_data_reg, BLOCK_TYPE_TERM_6};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_3: begin
encoded_tx_data_reg <= {output_data_reg[23:0], swap_data, BLOCK_TYPE_TERM_7};
encoded_tx_data_reg <= {output_data_reg[23:0], swap_data_reg, BLOCK_TYPE_TERM_7};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_4: begin
encoded_tx_data_reg <= {output_data_reg[31:0], swap_data};
encoded_tx_data_reg <= {output_data_reg[31:0], swap_data_reg};
encoded_tx_hdr_reg <= SYNC_DATA;
output_data_finish_reg <= 1'b1;
output_type_reg <= OUTPUT_TYPE_TERM_4;
end
OUTPUT_TYPE_TERM_5: begin
encoded_tx_data_reg <= {output_data_reg[31:0], swap_data};
encoded_tx_data_reg <= {output_data_reg[31:0], swap_data_reg};
encoded_tx_hdr_reg <= SYNC_DATA;
output_data_finish_reg <= 1'b1;
output_type_reg <= OUTPUT_TYPE_TERM_5;
end
OUTPUT_TYPE_TERM_6: begin
encoded_tx_data_reg <= {output_data_reg[31:0], swap_data};
encoded_tx_data_reg <= {output_data_reg[31:0], swap_data_reg};
encoded_tx_hdr_reg <= SYNC_DATA;
output_data_finish_reg <= 1'b1;
output_type_reg <= OUTPUT_TYPE_TERM_6;
end
OUTPUT_TYPE_TERM_7: begin
encoded_tx_data_reg <= {output_data_reg[31:0], swap_data};
encoded_tx_data_reg <= {output_data_reg[31:0], swap_data_reg};
encoded_tx_hdr_reg <= SYNC_DATA;
output_data_finish_reg <= 1'b1;
output_type_reg <= OUTPUT_TYPE_TERM_7;
@@ -985,11 +985,11 @@ always_ff @(posedge clk) begin
encoded_tx_hdr_valid_reg <= 1'b1;
for (integer i = 0; i < 7; i = i + 1) begin
crc_state_reg[i] <= crc_state_next[i];
crc_state_reg[i] <= crc_state[i];
end
if (update_crc) begin
crc_state_reg[7] <= crc_state_next[7];
crc_state_reg[7] <= crc_state[7];
end
if (reset_crc) begin

182
src/eth/rtl/taxi_axis_gmii_rx.sv
View File

@@ -102,26 +102,26 @@ logic [1:0] state_reg = STATE_IDLE, state_next;
logic reset_crc;
logic update_crc;
logic mii_odd = 1'b0;
logic in_frame = 1'b0;
logic mii_odd_reg = 1'b0;
logic in_frame_reg = 1'b0;
logic [DATA_W-1:0] gmii_rxd_d0 = '0;
logic [DATA_W-1:0] gmii_rxd_d1 = '0;
logic [DATA_W-1:0] gmii_rxd_d2 = '0;
logic [DATA_W-1:0] gmii_rxd_d3 = '0;
logic [DATA_W-1:0] gmii_rxd_d4 = '0;
logic [DATA_W-1:0] gmii_rxd_d0_reg = '0;
logic [DATA_W-1:0] gmii_rxd_d1_reg = '0;
logic [DATA_W-1:0] gmii_rxd_d2_reg = '0;
logic [DATA_W-1:0] gmii_rxd_d3_reg = '0;
logic [DATA_W-1:0] gmii_rxd_d4_reg = '0;
logic gmii_rx_dv_d0 = 1'b0;
logic gmii_rx_dv_d1 = 1'b0;
logic gmii_rx_dv_d2 = 1'b0;
logic gmii_rx_dv_d3 = 1'b0;
logic gmii_rx_dv_d4 = 1'b0;
logic gmii_rx_dv_d0_reg = 1'b0;
logic gmii_rx_dv_d1_reg = 1'b0;
logic gmii_rx_dv_d2_reg = 1'b0;
logic gmii_rx_dv_d3_reg = 1'b0;
logic gmii_rx_dv_d4_reg = 1'b0;
logic gmii_rx_er_d0 = 1'b0;
logic gmii_rx_er_d1 = 1'b0;
logic gmii_rx_er_d2 = 1'b0;
logic gmii_rx_er_d3 = 1'b0;
logic gmii_rx_er_d4 = 1'b0;
logic gmii_rx_er_d0_reg = 1'b0;
logic gmii_rx_er_d1_reg = 1'b0;
logic gmii_rx_er_d2_reg = 1'b0;
logic gmii_rx_er_d3_reg = 1'b0;
logic gmii_rx_er_d4_reg = 1'b0;
logic frame_error_reg = 1'b0, frame_error_next;
logic in_pre_reg = 1'b0, in_pre_next;
@@ -159,8 +159,8 @@ logic stat_rx_err_preamble_reg = 1'b0, stat_rx_err_preamble_next;
logic [PTP_TS_W-1:0] ptp_ts_out_reg = '0;
logic [31:0] crc_state = '1;
wire [31:0] crc_next;
logic [31:0] crc_state_reg = '1;
wire [31:0] crc_state;
assign m_axis_rx.tdata = m_axis_rx_tdata_reg;
assign m_axis_rx.tkeep = 1'b1;
@@ -203,13 +203,13 @@ taxi_lfsr #(
.DATA_OUT_EN(1'b0)
)
eth_crc_8 (
.data_in(gmii_rxd_d0),
.state_in(crc_state),
.data_in(gmii_rxd_d0_reg),
.state_in(crc_state_reg),
.data_out(),
.state_out(crc_next)
.state_out(crc_state)
);
wire crc_valid = crc_next == ~32'h2144df1c;
wire crc_valid = crc_state == ~32'h2144df1c;
always_comb begin
state_next = STATE_IDLE;
@@ -251,7 +251,7 @@ always_comb begin
if (!clk_enable) begin
// clock disabled - hold state
state_next = state_reg;
end else if (mii_select && !mii_odd) begin
end else if (mii_select && !mii_odd_reg) begin
// MII even cycle - hold state
state_next = state_reg;
end else begin
@@ -273,16 +273,16 @@ always_comb begin
case (hdr_ptr_reg)
4'd0: begin
is_mcast_next = gmii_rxd_d4[0];
is_bcast_next = gmii_rxd_d4 == 8'hff;
is_mcast_next = gmii_rxd_d4_reg[0];
is_bcast_next = gmii_rxd_d4_reg == 8'hff;
end
4'd1: is_bcast_next = is_bcast_reg && gmii_rxd_d4 == 8'hff;
4'd2: is_bcast_next = is_bcast_reg && gmii_rxd_d4 == 8'hff;
4'd3: is_bcast_next = is_bcast_reg && gmii_rxd_d4 == 8'hff;
4'd4: is_bcast_next = is_bcast_reg && gmii_rxd_d4 == 8'hff;
4'd5: is_bcast_next = is_bcast_reg && gmii_rxd_d4 == 8'hff;
4'd12: is_8021q_next = gmii_rxd_d4 == 8'h81;
4'd13: is_8021q_next = is_8021q_reg && gmii_rxd_d4 == 8'h00;
4'd1: is_bcast_next = is_bcast_reg && gmii_rxd_d4_reg == 8'hff;
4'd2: is_bcast_next = is_bcast_reg && gmii_rxd_d4_reg == 8'hff;
4'd3: is_bcast_next = is_bcast_reg && gmii_rxd_d4_reg == 8'hff;
4'd4: is_bcast_next = is_bcast_reg && gmii_rxd_d4_reg == 8'hff;
4'd5: is_bcast_next = is_bcast_reg && gmii_rxd_d4_reg == 8'hff;
4'd12: is_8021q_next = gmii_rxd_d4_reg == 8'h81;
4'd13: is_8021q_next = is_8021q_reg && gmii_rxd_d4_reg == 8'h00;
default: begin
// do nothing
end
@@ -302,15 +302,15 @@ always_comb begin
state_next = STATE_IDLE;
if (gmii_rx_dv_d0) begin
if (gmii_rx_er_d0) begin
if (gmii_rx_dv_d0_reg) begin
if (gmii_rx_er_d0_reg) begin
// error in preamble
in_pre_next = 1'b0;
pre_ok_next = 1'b0;
stat_rx_err_framing_next = 1'b1;
end else if (gmii_rxd_d0 == ETH_PRE) begin
end else if (gmii_rxd_d0_reg == ETH_PRE) begin
// normal preamble
end else if (gmii_rxd_d0 == ETH_SFD) begin
end else if (gmii_rxd_d0_reg == ETH_SFD) begin
// start
in_pre_next = 1'b0;
if (in_pre_reg && cfg_rx_enable) begin
@@ -342,7 +342,7 @@ always_comb begin
stat_rx_err_framing_next = 1'b1;
end
if (gmii_rx_dv_d4 && !gmii_rx_er_d4 && gmii_rxd_d4 == ETH_SFD) begin
if (gmii_rx_dv_d4_reg && !gmii_rx_er_d4_reg && gmii_rxd_d4_reg == ETH_SFD) begin
state_next = STATE_PAYLOAD;
end else begin
state_next = STATE_PIPE;
@@ -352,7 +352,7 @@ always_comb begin
// read payload
update_crc = 1'b1;
m_axis_rx_tdata_next = gmii_rxd_d4;
m_axis_rx_tdata_next = gmii_rxd_d4_reg;
m_axis_rx_tvalid_next = 1'b1;
stat_rx_byte_next = gmii_rx_dv;
@@ -371,7 +371,7 @@ always_comb begin
stat_rx_pkt_bcast_next = is_bcast_reg;
stat_rx_pkt_vlan_next = is_8021q_reg;
stat_rx_err_oversize_next = frame_len_lim_reg == 0;
stat_rx_err_framing_next = !gmii_rx_dv_d0;
stat_rx_err_framing_next = !gmii_rx_dv_d0_reg;
stat_rx_err_preamble_next = !pre_ok_reg;
if (frame_error_next) begin
// error
@@ -440,71 +440,71 @@ always_ff @(posedge clk) begin
if (clk_enable) begin
if (mii_select) begin
mii_odd <= !mii_odd || !gmii_rx_dv;
mii_odd_reg <= !mii_odd_reg || !gmii_rx_dv;
if (in_frame) begin
in_frame <= gmii_rx_dv;
end else if (gmii_rx_dv && {gmii_rxd[3:0], gmii_rxd_d0[7:4]} == ETH_SFD) begin
in_frame <= 1'b1;
if (in_frame_reg) begin
in_frame_reg <= gmii_rx_dv;
end else if (gmii_rx_dv && {gmii_rxd[3:0], gmii_rxd_d0_reg[7:4]} == ETH_SFD) begin
in_frame_reg <= 1'b1;
start_packet_int_reg <= 1'b1;
mii_odd <= 1'b1;
mii_odd_reg <= 1'b1;
end
gmii_rxd_d0 <= {gmii_rxd[3:0], gmii_rxd_d0[7:4]};
gmii_rxd_d0_reg <= {gmii_rxd[3:0], gmii_rxd_d0_reg[7:4]};
if (mii_odd) begin
gmii_rxd_d1 <= gmii_rxd_d0;
gmii_rxd_d2 <= gmii_rxd_d1;
gmii_rxd_d3 <= gmii_rxd_d2;
gmii_rxd_d4 <= gmii_rxd_d3;
if (mii_odd_reg) begin
gmii_rxd_d1_reg <= gmii_rxd_d0_reg;
gmii_rxd_d2_reg <= gmii_rxd_d1_reg;
gmii_rxd_d3_reg <= gmii_rxd_d2_reg;
gmii_rxd_d4_reg <= gmii_rxd_d3_reg;
gmii_rx_dv_d0 <= gmii_rx_dv;
gmii_rx_dv_d1 <= gmii_rx_dv_d0;
gmii_rx_dv_d2 <= gmii_rx_dv_d1;
gmii_rx_dv_d3 <= gmii_rx_dv_d2;
gmii_rx_dv_d4 <= gmii_rx_dv_d3;
gmii_rx_dv_d0_reg <= gmii_rx_dv;
gmii_rx_dv_d1_reg <= gmii_rx_dv_d0_reg;
gmii_rx_dv_d2_reg <= gmii_rx_dv_d1_reg;
gmii_rx_dv_d3_reg <= gmii_rx_dv_d2_reg;
gmii_rx_dv_d4_reg <= gmii_rx_dv_d3_reg;
gmii_rx_er_d0 <= gmii_rx_er;
gmii_rx_er_d1 <= gmii_rx_er_d0;
gmii_rx_er_d2 <= gmii_rx_er_d1;
gmii_rx_er_d3 <= gmii_rx_er_d2;
gmii_rx_er_d4 <= gmii_rx_er_d3;
gmii_rx_er_d0_reg <= gmii_rx_er;
gmii_rx_er_d1_reg <= gmii_rx_er_d0_reg;
gmii_rx_er_d2_reg <= gmii_rx_er_d1_reg;
gmii_rx_er_d3_reg <= gmii_rx_er_d2_reg;
gmii_rx_er_d4_reg <= gmii_rx_er_d3_reg;
end else begin
gmii_rx_dv_d0 <= gmii_rx_dv & gmii_rx_dv_d0;
gmii_rx_er_d0 <= gmii_rx_er | gmii_rx_er_d0;
gmii_rx_dv_d0_reg <= gmii_rx_dv & gmii_rx_dv_d0_reg;
gmii_rx_er_d0_reg <= gmii_rx_er | gmii_rx_er_d0_reg;
end
end else begin
if (in_frame) begin
in_frame <= gmii_rx_dv;
if (in_frame_reg) begin
in_frame_reg <= gmii_rx_dv;
end else if (gmii_rx_dv && gmii_rxd == ETH_SFD) begin
in_frame <= 1'b1;
in_frame_reg <= 1'b1;
start_packet_int_reg <= 1'b1;
end
gmii_rxd_d0 <= gmii_rxd;
gmii_rxd_d1 <= gmii_rxd_d0;
gmii_rxd_d2 <= gmii_rxd_d1;
gmii_rxd_d3 <= gmii_rxd_d2;
gmii_rxd_d4 <= gmii_rxd_d3;
gmii_rxd_d0_reg <= gmii_rxd;
gmii_rxd_d1_reg <= gmii_rxd_d0_reg;
gmii_rxd_d2_reg <= gmii_rxd_d1_reg;
gmii_rxd_d3_reg <= gmii_rxd_d2_reg;
gmii_rxd_d4_reg <= gmii_rxd_d3_reg;
gmii_rx_dv_d0 <= gmii_rx_dv;
gmii_rx_dv_d1 <= gmii_rx_dv_d0;
gmii_rx_dv_d2 <= gmii_rx_dv_d1;
gmii_rx_dv_d3 <= gmii_rx_dv_d2;
gmii_rx_dv_d4 <= gmii_rx_dv_d3;
gmii_rx_dv_d0_reg <= gmii_rx_dv;
gmii_rx_dv_d1_reg <= gmii_rx_dv_d0_reg;
gmii_rx_dv_d2_reg <= gmii_rx_dv_d1_reg;
gmii_rx_dv_d3_reg <= gmii_rx_dv_d2_reg;
gmii_rx_dv_d4_reg <= gmii_rx_dv_d3_reg;
gmii_rx_er_d0 <= gmii_rx_er;
gmii_rx_er_d1 <= gmii_rx_er_d0;
gmii_rx_er_d2 <= gmii_rx_er_d1;
gmii_rx_er_d3 <= gmii_rx_er_d2;
gmii_rx_er_d4 <= gmii_rx_er_d3;
gmii_rx_er_d0_reg <= gmii_rx_er;
gmii_rx_er_d1_reg <= gmii_rx_er_d0_reg;
gmii_rx_er_d2_reg <= gmii_rx_er_d1_reg;
gmii_rx_er_d3_reg <= gmii_rx_er_d2_reg;
gmii_rx_er_d4_reg <= gmii_rx_er_d3_reg;
end
end
if (reset_crc) begin
crc_state <= '1;
crc_state_reg <= '1;
end else if (update_crc) begin
crc_state <= crc_next;
crc_state_reg <= crc_state;
end
stat_rx_byte_reg <= stat_rx_byte_next;
@@ -547,14 +547,14 @@ always_ff @(posedge clk) begin
stat_rx_err_framing_reg <= 1'b0;
stat_rx_err_preamble_reg <= 1'b0;
in_frame <= 1'b0;
mii_odd <= 1'b0;
in_frame_reg <= 1'b0;
mii_odd_reg <= 1'b0;
gmii_rx_dv_d0 <= 1'b0;
gmii_rx_dv_d1 <= 1'b0;
gmii_rx_dv_d2 <= 1'b0;
gmii_rx_dv_d3 <= 1'b0;
gmii_rx_dv_d4 <= 1'b0;
gmii_rx_dv_d0_reg <= 1'b0;
gmii_rx_dv_d1_reg <= 1'b0;
gmii_rx_dv_d2_reg <= 1'b0;
gmii_rx_dv_d3_reg <= 1'b0;
gmii_rx_dv_d4_reg <= 1'b0;
end
end

20
src/eth/rtl/taxi_axis_gmii_tx.sv
View File

@@ -153,8 +153,8 @@ logic stat_tx_err_oversize_reg = 1'b0, stat_tx_err_oversize_next;
logic stat_tx_err_user_reg = 1'b0, stat_tx_err_user_next;
logic stat_tx_err_underflow_reg = 1'b0, stat_tx_err_underflow_next;
logic [31:0] crc_state = '1;
wire [31:0] crc_next;
logic [31:0] crc_state_reg = '1;
wire [31:0] crc_state;
assign s_axis_tx.tready = s_axis_tx_tready_reg;
@@ -196,9 +196,9 @@ taxi_lfsr #(
)
eth_crc_8 (
.data_in(s_tdata_reg),
.state_in(crc_state),
.state_in(crc_state_reg),
.data_out(),
.state_out(crc_next)
.state_out(crc_state)
);
always_comb begin
@@ -471,10 +471,10 @@ always_comb begin
ifg_cnt_next = cfg_tx_ifg;
case (fcs_ptr_reg)
2'd0: gmii_txd_next = ~crc_state[7:0];
2'd1: gmii_txd_next = ~crc_state[15:8];
2'd2: gmii_txd_next = ~crc_state[23:16];
2'd3: gmii_txd_next = ~crc_state[31:24];
2'd0: gmii_txd_next = ~crc_state_reg[7:0];
2'd1: gmii_txd_next = ~crc_state_reg[15:8];
2'd2: gmii_txd_next = ~crc_state_reg[23:16];
2'd3: gmii_txd_next = ~crc_state_reg[31:24];
endcase
gmii_tx_en_next = 1'b1;
gmii_tx_er_next = frame_error_reg;
@@ -552,9 +552,9 @@ always_ff @(posedge clk) begin
gmii_tx_er_reg <= gmii_tx_er_next;
if (reset_crc) begin
crc_state <= '1;
crc_state_reg <= '1;
end else if (update_crc) begin
crc_state <= crc_next;
crc_state_reg <= crc_state;
end
start_packet_int_reg <= start_packet_int_next;

84
src/eth/rtl/taxi_axis_xgmii_rx_32.sv
View File

@@ -114,15 +114,15 @@ logic term_first_cycle_reg = 1'b0;
logic [1:0] term_lane_reg = 0, term_lane_d0_reg = 0;
logic framing_error_reg = 1'b0;
logic [DATA_W-1:0] xgmii_rxd_d0 = '0;
logic [DATA_W-1:0] xgmii_rxd_d1 = '0;
logic [DATA_W-1:0] xgmii_rxd_d2 = '0;
logic [DATA_W-1:0] xgmii_rxd_d0_reg = '0;
logic [DATA_W-1:0] xgmii_rxd_d1_reg = '0;
logic [DATA_W-1:0] xgmii_rxd_d2_reg = '0;
logic [CTRL_W-1:0] xgmii_rxc_d0 = '0;
logic [CTRL_W-1:0] xgmii_rxc_d0_reg = '0;
logic xgmii_start_d0 = 1'b0;
logic xgmii_start_d1 = 1'b0;
logic xgmii_start_d2 = 1'b0;
logic xgmii_start_d0_reg = 1'b0;
logic xgmii_start_d1_reg = 1'b0;
logic xgmii_start_d2_reg = 1'b0;
logic frame_oversize_reg = 1'b0, frame_oversize_next;
logic pre_ok_reg = 1'b0, pre_ok_next;
@@ -163,15 +163,15 @@ logic [PTP_TS_W-1:0] ptp_ts_out_reg = '0, ptp_ts_out_next;
logic [31:0] crc_state_reg = '1;
wire [31:0] crc_state_next;
wire [31:0] crc_state;
wire [3:0] crc_valid;
logic [3:0] crc_valid_save;
logic [3:0] crc_valid_reg = '0;
assign crc_valid[3] = crc_state_next == ~32'h2144df1c;
assign crc_valid[2] = crc_state_next == ~32'hc622f71d;
assign crc_valid[1] = crc_state_next == ~32'hb1c2a1a3;
assign crc_valid[0] = crc_state_next == ~32'h9d6cdf7e;
assign crc_valid[3] = crc_state == ~32'h2144df1c;
assign crc_valid[2] = crc_state == ~32'hc622f71d;
assign crc_valid[1] = crc_state == ~32'hb1c2a1a3;
assign crc_valid[0] = crc_state == ~32'h9d6cdf7e;
assign m_axis_rx.tdata = m_axis_rx_tdata_reg;
assign m_axis_rx.tkeep = m_axis_rx_tkeep_reg;
@@ -216,10 +216,10 @@ taxi_lfsr #(
.DATA_OUT_EN(1'b0)
)
eth_crc (
.data_in(xgmii_rxd_d0),
.data_in(xgmii_rxd_d0_reg),
.state_in(crc_state_reg),
.data_out(),
.state_out(crc_state_next)
.state_out(crc_state)
);
// Mask input data
@@ -247,7 +247,7 @@ always_comb begin
frame_len_lim_last_next = frame_len_lim_last_reg;
frame_len_lim_check_next = frame_len_lim_check_reg;
m_axis_rx_tdata_next = xgmii_rxd_d2;
m_axis_rx_tdata_next = xgmii_rxd_d2_reg;
m_axis_rx_tkeep_next = {KEEP_W{1'b1}};
m_axis_rx_tvalid_next = 1'b0;
m_axis_rx_tlast_next = 1'b0;
@@ -306,11 +306,11 @@ always_comb begin
case (hdr_ptr_reg)
3'd0: begin
is_mcast_next = xgmii_rxd_d2[0];
is_bcast_next = &xgmii_rxd_d2;
is_mcast_next = xgmii_rxd_d2_reg[0];
is_bcast_next = &xgmii_rxd_d2_reg;
end
3'd1: is_bcast_next = is_bcast_reg && &xgmii_rxd_d2[15:0];
3'd3: is_8021q_next = {xgmii_rxd_d2[7:0], xgmii_rxd_d2[15:8]} == 16'h8100;
3'd1: is_bcast_next = is_bcast_reg && &xgmii_rxd_d2_reg[15:0];
3'd3: is_8021q_next = {xgmii_rxd_d2_reg[7:0], xgmii_rxd_d2_reg[15:8]} == 16'h8100;
default: begin
// do nothing
end
@@ -327,9 +327,9 @@ always_comb begin
frame_len_lim_check_next = 1'b0;
hdr_ptr_next = 0;
pre_ok_next = xgmii_rxd_d2[31:8] == 24'h555555;
pre_ok_next = xgmii_rxd_d2_reg[31:8] == 24'h555555;
if (xgmii_start_d2 && cfg_rx_enable) begin
if (xgmii_start_d2_reg && cfg_rx_enable) begin
// start condition
if (framing_error_reg) begin
// control or error characters in first data word
@@ -352,7 +352,7 @@ always_comb begin
hdr_ptr_next = 0;
pre_ok_next = pre_ok_reg && xgmii_rxd_d2 == 32'hD5555555;
pre_ok_next = pre_ok_reg && xgmii_rxd_d2_reg == 32'hD5555555;
if (framing_error_reg) begin
// control or error characters in packet
@@ -366,7 +366,7 @@ always_comb begin
end
STATE_PAYLOAD: begin
// read payload
m_axis_rx_tdata_next = xgmii_rxd_d2;
m_axis_rx_tdata_next = xgmii_rxd_d2_reg;
m_axis_rx_tkeep_next = {KEEP_W{1'b1}};
m_axis_rx_tvalid_next = 1'b1;
m_axis_rx_tlast_next = 1'b0;
@@ -408,7 +408,7 @@ always_comb begin
// end this cycle
m_axis_rx_tkeep_next = 4'b1111;
m_axis_rx_tlast_next = 1'b1;
if (crc_valid_save[3]) begin
if (crc_valid_reg[3]) begin
// CRC valid
if (frame_oversize_next) begin
// too long
@@ -444,7 +444,7 @@ always_comb begin
end
STATE_LAST: begin
// last cycle of packet
m_axis_rx_tdata_next = xgmii_rxd_d2;
m_axis_rx_tdata_next = xgmii_rxd_d2_reg;
m_axis_rx_tkeep_next = {KEEP_W{1'b1}} >> 2'(CTRL_W-term_lane_d0_reg);
m_axis_rx_tvalid_next = 1'b1;
m_axis_rx_tlast_next = 1'b1;
@@ -452,9 +452,9 @@ always_comb begin
reset_crc = 1'b1;
if ((term_lane_d0_reg == 1 && crc_valid_save[0]) ||
(term_lane_d0_reg == 2 && crc_valid_save[1]) ||
(term_lane_d0_reg == 3 && crc_valid_save[2])) begin
if ((term_lane_d0_reg == 1 && crc_valid_reg[0]) ||
(term_lane_d0_reg == 2 && crc_valid_reg[1]) ||
(term_lane_d0_reg == 3 && crc_valid_reg[2])) begin
// CRC valid
if (frame_oversize_reg) begin
// too long
@@ -551,19 +551,19 @@ always_ff @(posedge clk) begin
if (reset_crc) begin
crc_state_reg <= '1;
end else begin
crc_state_reg <= crc_state_next;
crc_state_reg <= crc_state;
end
crc_valid_save <= crc_valid;
crc_valid_reg <= crc_valid;
xgmii_rxc_d0 <= xgmii_rxc;
xgmii_rxd_d0 <= xgmii_rxd_masked;
xgmii_rxd_d1 <= xgmii_rxd_d0;
xgmii_rxd_d2 <= xgmii_rxd_d1;
xgmii_rxc_d0_reg <= xgmii_rxc;
xgmii_rxd_d0_reg <= xgmii_rxd_masked;
xgmii_rxd_d1_reg <= xgmii_rxd_d0_reg;
xgmii_rxd_d2_reg <= xgmii_rxd_d1_reg;
xgmii_start_d0 <= xgmii_rxc[0] && xgmii_rxd[7:0] == XGMII_START;
xgmii_start_d1 <= xgmii_start_d0;
xgmii_start_d2 <= xgmii_start_d1;
xgmii_start_d0_reg <= xgmii_rxc[0] && xgmii_rxd[7:0] == XGMII_START;
xgmii_start_d1_reg <= xgmii_start_d0_reg;
xgmii_start_d2_reg <= xgmii_start_d1_reg;
end
if (rst) begin
@@ -589,11 +589,11 @@ always_ff @(posedge clk) begin
stat_rx_err_framing_reg <= 1'b0;
stat_rx_err_preamble_reg <= 1'b0;
xgmii_rxc_d0 <= '0;
xgmii_rxc_d0_reg <= '0;
xgmii_start_d0 <= 1'b0;
xgmii_start_d1 <= 1'b0;
xgmii_start_d2 <= 1'b0;
xgmii_start_d0_reg <= 1'b0;
xgmii_start_d1_reg <= 1'b0;
xgmii_start_d2_reg <= 1'b0;
end
end

132
src/eth/rtl/taxi_axis_xgmii_rx_64.sv
View File

@@ -109,24 +109,24 @@ logic [1:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
logic reset_crc;
logic lanes_swapped = 1'b0;
logic [31:0] swap_rxd = 32'd0;
logic [3:0] swap_rxc = 4'd0;
logic [3:0] swap_rxc_term = 4'd0;
logic lanes_swapped_reg = 1'b0;
logic [31:0] swap_rxd_reg = 32'd0;
logic [3:0] swap_rxc_reg = 4'd0;
logic [3:0] swap_rxc_term_reg = 4'd0;
logic term_present_reg = 1'b0;
logic term_first_cycle_reg = 1'b0;
logic [2:0] term_lane_reg = 0, term_lane_d0_reg = 0;
logic framing_error_reg = 1'b0, framing_error_d0_reg = 1'b0;
logic [DATA_W-1:0] xgmii_rxd_d0 = '0;
logic [DATA_W-1:0] xgmii_rxd_d1 = '0;
logic [DATA_W-1:0] xgmii_rxd_d0_reg = '0;
logic [DATA_W-1:0] xgmii_rxd_d1_reg = '0;
logic [CTRL_W-1:0] xgmii_rxc_d0 = '0;
logic [CTRL_W-1:0] xgmii_rxc_d0_reg = '0;
logic xgmii_start_swap = 1'b0;
logic xgmii_start_d0 = 1'b0;
logic xgmii_start_d1 = 1'b0;
logic xgmii_start_swap_reg = 1'b0;
logic xgmii_start_d0_reg = 1'b0;
logic xgmii_start_d1_reg = 1'b0;
logic frame_oversize_reg = 1'b0, frame_oversize_next;
logic pre_ok_reg = 1'b0, pre_ok_next;
@@ -170,19 +170,19 @@ logic ptp_ts_borrow_reg = '0;
logic [31:0] crc_state_reg = '1;
wire [31:0] crc_state_next;
wire [31:0] crc_state;
wire [7:0] crc_valid;
logic [7:0] crc_valid_save;
logic [7:0] crc_valid_reg = '0;
assign crc_valid[7] = crc_state_next == ~32'h2144df1c;
assign crc_valid[6] = crc_state_next == ~32'hc622f71d;
assign crc_valid[5] = crc_state_next == ~32'hb1c2a1a3;
assign crc_valid[4] = crc_state_next == ~32'h9d6cdf7e;
assign crc_valid[3] = crc_state_next == ~32'h6522df69;
assign crc_valid[2] = crc_state_next == ~32'he60914ae;
assign crc_valid[1] = crc_state_next == ~32'he38a6876;
assign crc_valid[0] = crc_state_next == ~32'h6b87b1ec;
assign crc_valid[7] = crc_state == ~32'h2144df1c;
assign crc_valid[6] = crc_state == ~32'hc622f71d;
assign crc_valid[5] = crc_state == ~32'hb1c2a1a3;
assign crc_valid[4] = crc_state == ~32'h9d6cdf7e;
assign crc_valid[3] = crc_state == ~32'h6522df69;
assign crc_valid[2] = crc_state == ~32'he60914ae;
assign crc_valid[1] = crc_state == ~32'he38a6876;
assign crc_valid[0] = crc_state == ~32'h6b87b1ec;
logic [4+16-1:0] last_ts_reg = '0;
logic [4+16-1:0] ts_inc_reg = '0;
@@ -228,10 +228,10 @@ taxi_lfsr #(
.DATA_OUT_EN(1'b0)
)
eth_crc (
.data_in(xgmii_rxd_d0),
.data_in(xgmii_rxd_d0_reg),
.state_in(crc_state_reg),
.data_out(),
.state_out(crc_state_next)
.state_out(crc_state)
);
// Mask input data
@@ -259,7 +259,7 @@ always_comb begin
frame_len_lim_last_next = frame_len_lim_last_reg;
frame_len_lim_check_next = frame_len_lim_check_reg;
m_axis_rx_tdata_next = xgmii_rxd_d1;
m_axis_rx_tdata_next = xgmii_rxd_d1_reg;
m_axis_rx_tkeep_next = {KEEP_W{1'b1}};
m_axis_rx_tvalid_next = 1'b0;
m_axis_rx_tlast_next = 1'b0;
@@ -316,10 +316,10 @@ always_comb begin
case (hdr_ptr_reg)
2'd0: begin
is_mcast_next = xgmii_rxd_d1[0];
is_bcast_next = &xgmii_rxd_d1[47:0];
is_mcast_next = xgmii_rxd_d1_reg[0];
is_bcast_next = &xgmii_rxd_d1_reg[47:0];
end
2'd1: is_8021q_next = {xgmii_rxd_d1[39:32], xgmii_rxd_d1[47:40]} == 16'h8100;
2'd1: is_8021q_next = {xgmii_rxd_d1_reg[39:32], xgmii_rxd_d1_reg[47:40]} == 16'h8100;
default: begin
// do nothing
end
@@ -336,9 +336,9 @@ always_comb begin
frame_len_lim_check_next = 1'b0;
hdr_ptr_next = 0;
pre_ok_next = xgmii_rxd_d1[63:8] == 56'hD5555555555555;
pre_ok_next = xgmii_rxd_d1_reg[63:8] == 56'hD5555555555555;
if (xgmii_start_d1 && cfg_rx_enable) begin
if (xgmii_start_d1_reg && cfg_rx_enable) begin
// start condition
reset_crc = 1'b0;
@@ -350,7 +350,7 @@ always_comb begin
end
STATE_PAYLOAD: begin
// read payload
m_axis_rx_tdata_next = xgmii_rxd_d1;
m_axis_rx_tdata_next = xgmii_rxd_d1_reg;
m_axis_rx_tkeep_next = {KEEP_W{1'b1}};
m_axis_rx_tvalid_next = 1'b1;
m_axis_rx_tlast_next = 1'b0;
@@ -396,7 +396,7 @@ always_comb begin
// end this cycle
m_axis_rx_tkeep_next = {KEEP_W{1'b1}} >> 3'(CTRL_W-4-term_lane_reg);
m_axis_rx_tlast_next = 1'b1;
if ((term_lane_reg == 0 && crc_valid_save[7]) ||
if ((term_lane_reg == 0 && crc_valid_reg[7]) ||
(term_lane_reg == 1 && crc_valid[0]) ||
(term_lane_reg == 2 && crc_valid[1]) ||
(term_lane_reg == 3 && crc_valid[2]) ||
@@ -436,7 +436,7 @@ always_comb begin
end
STATE_LAST: begin
// last cycle of packet
m_axis_rx_tdata_next = xgmii_rxd_d1;
m_axis_rx_tdata_next = xgmii_rxd_d1_reg;
m_axis_rx_tkeep_next = {KEEP_W{1'b1}} >> 3'(CTRL_W+4-term_lane_d0_reg);
m_axis_rx_tvalid_next = 1'b1;
m_axis_rx_tlast_next = 1'b1;
@@ -444,9 +444,9 @@ always_comb begin
reset_crc = 1'b1;
if ((term_lane_d0_reg == 5 && crc_valid_save[4]) ||
(term_lane_d0_reg == 6 && crc_valid_save[5]) ||
(term_lane_d0_reg == 7 && crc_valid_save[6])) begin
if ((term_lane_d0_reg == 5 && crc_valid_reg[4]) ||
(term_lane_d0_reg == 6 && crc_valid_reg[5]) ||
(term_lane_d0_reg == 7 && crc_valid_reg[6])) begin
// CRC valid
if (frame_oversize_reg) begin
// too long
@@ -473,7 +473,7 @@ always_comb begin
stat_rx_err_oversize_next = frame_oversize_reg;
stat_rx_err_preamble_next = !pre_ok_reg;
if (xgmii_start_d1 && cfg_rx_enable) begin
if (xgmii_start_d1_reg && cfg_rx_enable) begin
// start condition
reset_crc = 1'b0;
@@ -531,12 +531,12 @@ always_ff @(posedge clk) begin
stat_rx_err_preamble_reg <= stat_rx_err_preamble_next;
if (!GBX_IF_EN || xgmii_rx_valid) begin
swap_rxd <= xgmii_rxd_masked[63:32];
swap_rxc <= xgmii_rxc[7:4];
swap_rxc_term <= xgmii_term[7:4];
swap_rxd_reg <= xgmii_rxd_masked[63:32];
swap_rxc_reg <= xgmii_rxc[7:4];
swap_rxc_term_reg <= xgmii_term[7:4];
xgmii_start_swap <= 1'b0;
xgmii_start_d0 <= xgmii_start_swap;
xgmii_start_swap_reg <= 1'b0;
xgmii_start_d0_reg <= xgmii_start_swap_reg;
if (PTP_TS_EN && PTP_TS_FMT_TOD) begin
// ns field rollover
@@ -547,26 +547,26 @@ always_ff @(posedge clk) begin
end
// lane swapping and termination character detection
if (lanes_swapped) begin
xgmii_rxd_d0 <= {xgmii_rxd_masked[31:0], swap_rxd};
xgmii_rxc_d0 <= {xgmii_rxc[3:0], swap_rxc};
if (lanes_swapped_reg) begin
xgmii_rxd_d0_reg <= {xgmii_rxd_masked[31:0], swap_rxd_reg};
xgmii_rxc_d0_reg <= {xgmii_rxc[3:0], swap_rxc_reg};
term_present_reg <= 1'b0;
term_first_cycle_reg <= 1'b0;
term_lane_reg <= 0;
framing_error_reg <= {xgmii_rxc[3:0], swap_rxc} != 0;
framing_error_reg <= {xgmii_rxc[3:0], swap_rxc_reg} != 0;
for (integer i = CTRL_W-1; i >= 0; i = i - 1) begin
if ({xgmii_term[3:0], swap_rxc_term}[i]) begin
if ({xgmii_term[3:0], swap_rxc_term_reg}[i]) begin
term_present_reg <= 1'b1;
term_first_cycle_reg <= i <= 4;
term_lane_reg <= 3'(i);
framing_error_reg <= ({xgmii_rxc[3:0], swap_rxc} & ({CTRL_W{1'b1}} >> (CTRL_W-i))) != 0;
framing_error_reg <= ({xgmii_rxc[3:0], swap_rxc_reg} & ({CTRL_W{1'b1}} >> (CTRL_W-i))) != 0;
end
end
end else begin
xgmii_rxd_d0 <= xgmii_rxd_masked;
xgmii_rxc_d0 <= xgmii_rxc;
xgmii_rxd_d0_reg <= xgmii_rxd_masked;
xgmii_rxc_d0_reg <= xgmii_rxc;
term_present_reg <= 1'b0;
term_first_cycle_reg <= 1'b0;
@@ -585,22 +585,22 @@ always_ff @(posedge clk) begin
// start control character detection
if (xgmii_rxc[0] && xgmii_rxd[7:0] == XGMII_START) begin
lanes_swapped <= 1'b0;
xgmii_start_d0 <= 1'b1;
lanes_swapped_reg <= 1'b0;
xgmii_start_d0_reg <= 1'b1;
xgmii_rxd_d0 <= xgmii_rxd_masked;
xgmii_rxc_d0 <= xgmii_rxc;
xgmii_rxd_d0_reg <= xgmii_rxd_masked;
xgmii_rxc_d0_reg <= xgmii_rxc;
framing_error_reg <= xgmii_rxc[7:1] != 0;
end else if (xgmii_rxc[4] && xgmii_rxd[39:32] == XGMII_START) begin
lanes_swapped <= 1'b1;
xgmii_start_swap <= 1'b1;
lanes_swapped_reg <= 1'b1;
xgmii_start_swap_reg <= 1'b1;
framing_error_reg <= xgmii_rxc[7:5] != 0;
end
// capture timestamps
if (xgmii_start_swap) begin
if (xgmii_start_swap_reg) begin
start_packet_reg <= 2'b10;
if (PTP_TS_FMT_TOD) begin
ptp_ts_reg[45:0] <= ptp_ts[45:0] + 46'(ts_inc_reg >> 1);
@@ -610,8 +610,8 @@ always_ff @(posedge clk) begin
end
end
if (xgmii_start_d0) begin
if (!lanes_swapped) begin
if (xgmii_start_d0_reg) begin
if (!lanes_swapped_reg) begin
start_packet_reg <= 2'b01;
ptp_ts_reg <= ptp_ts;
end
@@ -623,13 +623,13 @@ always_ff @(posedge clk) begin
if (reset_crc) begin
crc_state_reg <= '1;
end else begin
crc_state_reg <= crc_state_next;
crc_state_reg <= crc_state;
end
crc_valid_save <= crc_valid;
crc_valid_reg <= crc_valid;
xgmii_rxd_d1 <= xgmii_rxd_d0;
xgmii_start_d1 <= xgmii_start_d0;
xgmii_rxd_d1_reg <= xgmii_rxd_d0_reg;
xgmii_start_d1_reg <= xgmii_start_d0_reg;
end
last_ts_reg <= (4+16)'(ptp_ts);
@@ -658,13 +658,13 @@ always_ff @(posedge clk) begin
stat_rx_err_framing_reg <= 1'b0;
stat_rx_err_preamble_reg <= 1'b0;
xgmii_rxc_d0 <= '0;
xgmii_rxc_d0_reg <= '0;
xgmii_start_swap <= 1'b0;
xgmii_start_d0 <= 1'b0;
xgmii_start_d1 <= 1'b0;
xgmii_start_swap_reg <= 1'b0;
xgmii_start_d0_reg <= 1'b0;
xgmii_start_d1_reg <= 1'b0;
lanes_swapped <= 1'b0;
lanes_swapped_reg <= 1'b0;
end
end

14
src/eth/rtl/taxi_axis_xgmii_tx_32.sv
View File

@@ -161,7 +161,7 @@ logic [TX_TAG_W-1:0] m_axis_tx_cpl_tag_reg = '0, m_axis_tx_cpl_tag_next;
logic m_axis_tx_cpl_valid_reg = 1'b0, m_axis_tx_cpl_valid_next;
logic [31:0] crc_state_reg[4];
wire [31:0] crc_state_next[4];
wire [31:0] crc_state[4];
logic [DATA_W-1:0] xgmii_txd_reg = {CTRL_W{XGMII_IDLE}}, xgmii_txd_next;
logic [CTRL_W-1:0] xgmii_txc_reg = {CTRL_W{1'b1}}, xgmii_txc_next;
@@ -228,7 +228,7 @@ for (genvar n = 0; n < 4; n = n + 1) begin : crc
.data_in(s_tdata_reg[0 +: 8*(n+1)]),
.state_in(crc_state_reg[3]),
.data_out(),
.state_out(crc_state_next[n])
.state_out(crc_state[n])
);
end
@@ -254,7 +254,7 @@ end
always_comb begin
casez (s_empty_reg)
2'd3: begin
fcs_output_txd_0 = {~crc_state_next[0][23:0], s_tdata_reg[7:0]};
fcs_output_txd_0 = {~crc_state[0][23:0], s_tdata_reg[7:0]};
fcs_output_txd_1 = {{2{XGMII_IDLE}}, XGMII_TERM, ~crc_state_reg[0][31:24]};
fcs_output_txc_0 = 4'b0000;
fcs_output_txc_1 = 4'b1110;
@@ -262,7 +262,7 @@ always_comb begin
extra_cycle = 1'b0;
end
2'd2: begin
fcs_output_txd_0 = {~crc_state_next[1][15:0], s_tdata_reg[15:0]};
fcs_output_txd_0 = {~crc_state[1][15:0], s_tdata_reg[15:0]};
fcs_output_txd_1 = {XGMII_IDLE, XGMII_TERM, ~crc_state_reg[1][31:16]};
fcs_output_txc_0 = 4'b0000;
fcs_output_txc_1 = 4'b1100;
@@ -270,7 +270,7 @@ always_comb begin
extra_cycle = 1'b0;
end
2'd1: begin
fcs_output_txd_0 = {~crc_state_next[2][7:0], s_tdata_reg[23:0]};
fcs_output_txd_0 = {~crc_state[2][7:0], s_tdata_reg[23:0]};
fcs_output_txd_1 = {XGMII_TERM, ~crc_state_reg[2][31:8]};
fcs_output_txc_0 = 4'b0000;
fcs_output_txc_1 = 4'b1000;
@@ -693,12 +693,12 @@ always_ff @(posedge clk) begin
// gearbox stall
end else begin
for (integer i = 0; i < 3; i = i + 1) begin
crc_state_reg[i] <= crc_state_next[i];
crc_state_reg[i] <= crc_state[i];
end
end
if (update_crc) begin
crc_state_reg[3] <= crc_state_next[3];
crc_state_reg[3] <= crc_state[3];
end
if (reset_crc) begin

34
src/eth/rtl/taxi_axis_xgmii_tx_64.sv
View File

@@ -125,8 +125,8 @@ logic reset_crc;
logic update_crc;
logic swap_lanes_reg = 1'b0, swap_lanes_next;
logic [31:0] swap_txd = 32'd0;
logic [3:0] swap_txc = 4'd0;
logic [31:0] swap_txd_reg = 32'd0;
logic [3:0] swap_txc_reg = 4'd0;
logic [DATA_W-1:0] s_tdata_reg = '0, s_tdata_next;
logic [EMPTY_W-1:0] s_empty_reg = '0, s_empty_next;
@@ -166,7 +166,7 @@ logic m_axis_tx_cpl_valid_int_reg = 1'b0;
logic m_axis_tx_cpl_ts_borrow_reg = 1'b0;
logic [31:0] crc_state_reg[8];
wire [31:0] crc_state_next[8];
wire [31:0] crc_state[8];
logic [4+16-1:0] last_ts_reg = '0;
logic [4+16-1:0] ts_inc_reg = '0;
@@ -236,7 +236,7 @@ for (genvar n = 0; n < 8; n = n + 1) begin : crc
.data_in(s_tdata_reg[0 +: 8*(n+1)]),
.state_in(crc_state_reg[7]),
.data_out(),
.state_out(crc_state_next[n])
.state_out(crc_state[n])
);
end
@@ -266,49 +266,49 @@ end
always_comb begin
casez (s_empty_reg)
3'd7: begin
fcs_output_txd_0 = {{2{XGMII_IDLE}}, XGMII_TERM, ~crc_state_next[0][31:0], s_tdata_reg[7:0]};
fcs_output_txd_0 = {{2{XGMII_IDLE}}, XGMII_TERM, ~crc_state[0][31:0], s_tdata_reg[7:0]};
fcs_output_txd_1 = {8{XGMII_IDLE}};
fcs_output_txc_0 = 8'b11100000;
fcs_output_txc_1 = 8'b11111111;
ifg_offset = 8'd3;
end
3'd6: begin
fcs_output_txd_0 = {XGMII_IDLE, XGMII_TERM, ~crc_state_next[1][31:0], s_tdata_reg[15:0]};
fcs_output_txd_0 = {XGMII_IDLE, XGMII_TERM, ~crc_state[1][31:0], s_tdata_reg[15:0]};
fcs_output_txd_1 = {8{XGMII_IDLE}};
fcs_output_txc_0 = 8'b11000000;
fcs_output_txc_1 = 8'b11111111;
ifg_offset = 8'd2;
end
3'd5: begin
fcs_output_txd_0 = {XGMII_TERM, ~crc_state_next[2][31:0], s_tdata_reg[23:0]};
fcs_output_txd_0 = {XGMII_TERM, ~crc_state[2][31:0], s_tdata_reg[23:0]};
fcs_output_txd_1 = {8{XGMII_IDLE}};
fcs_output_txc_0 = 8'b10000000;
fcs_output_txc_1 = 8'b11111111;
ifg_offset = 8'd1;
end
3'd4: begin
fcs_output_txd_0 = {~crc_state_next[3][31:0], s_tdata_reg[31:0]};
fcs_output_txd_0 = {~crc_state[3][31:0], s_tdata_reg[31:0]};
fcs_output_txd_1 = {{7{XGMII_IDLE}}, XGMII_TERM};
fcs_output_txc_0 = 8'b00000000;
fcs_output_txc_1 = 8'b11111111;
ifg_offset = 8'd8;
end
3'd3: begin
fcs_output_txd_0 = {~crc_state_next[4][23:0], s_tdata_reg[39:0]};
fcs_output_txd_0 = {~crc_state[4][23:0], s_tdata_reg[39:0]};
fcs_output_txd_1 = {{6{XGMII_IDLE}}, XGMII_TERM, ~crc_state_reg[4][31:24]};
fcs_output_txc_0 = 8'b00000000;
fcs_output_txc_1 = 8'b11111110;
ifg_offset = 8'd7;
end
3'd2: begin
fcs_output_txd_0 = {~crc_state_next[5][15:0], s_tdata_reg[47:0]};
fcs_output_txd_0 = {~crc_state[5][15:0], s_tdata_reg[47:0]};
fcs_output_txd_1 = {{5{XGMII_IDLE}}, XGMII_TERM, ~crc_state_reg[5][31:16]};
fcs_output_txc_0 = 8'b00000000;
fcs_output_txc_1 = 8'b11111100;
ifg_offset = 8'd6;
end
3'd1: begin
fcs_output_txd_0 = {~crc_state_next[6][7:0], s_tdata_reg[55:0]};
fcs_output_txd_0 = {~crc_state[6][7:0], s_tdata_reg[55:0]};
fcs_output_txd_1 = {{4{XGMII_IDLE}}, XGMII_TERM, ~crc_state_reg[6][31:8]};
fcs_output_txc_0 = 8'b00000000;
fcs_output_txc_1 = 8'b11111000;
@@ -771,23 +771,23 @@ always_ff @(posedge clk) begin
end
for (integer i = 0; i < 7; i = i + 1) begin
crc_state_reg[i] <= crc_state_next[i];
crc_state_reg[i] <= crc_state[i];
end
if (update_crc) begin
crc_state_reg[7] <= crc_state_next[7];
crc_state_reg[7] <= crc_state[7];
end
if (reset_crc) begin
crc_state_reg[7] <= '1;
end
swap_txd <= xgmii_txd_next[63:32];
swap_txc <= xgmii_txc_next[7:4];
swap_txd_reg <= xgmii_txd_next[63:32];
swap_txc_reg <= xgmii_txc_next[7:4];
if (swap_lanes_reg) begin
xgmii_txd_reg <= {xgmii_txd_next[31:0], swap_txd};
xgmii_txc_reg <= {xgmii_txc_next[3:0], swap_txc};
xgmii_txd_reg <= {xgmii_txd_next[31:0], swap_txd_reg};
xgmii_txc_reg <= {xgmii_txc_next[3:0], swap_txc_reg};
end else begin
xgmii_txd_reg <= xgmii_txd_next;
xgmii_txc_reg <= xgmii_txc_next;