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eth: Minor example design cleanup

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2026-04-14 22:46:47 -07:00
parent 198b12247d
commit 59a420b412
2 changed files with 8 additions and 8 deletions
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2
src/eth/example/HTG940/fpga/rtl/fpga.sv
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@@ -22,7 +22,7 @@ module fpga #
// vendor ("GENERIC", "XILINX", "ALTERA")
parameter string VENDOR = "XILINX",
// device family
parameter string FAMILY = "zynquplus",
parameter string FAMILY = "virtexuplus",
// Use 90 degree clock for RGMII transmit
parameter logic USE_CLK90 = 1'b0
)

2
src/eth/example/HTG940/fpga/rtl/fpga_core.sv
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@@ -22,7 +22,7 @@ module fpga_core #
// vendor ("GENERIC", "XILINX", "ALTERA")
parameter string VENDOR = "XILINX",
// device family
parameter string FAMILY = "zynquplus",
parameter string FAMILY = "virtexuplus",
// Use 90 degree clock for RGMII transmit
parameter logic USE_CLK90 = 1'b1
)