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axi: Clean up user signal width handling in AXI RAM IF modules

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2026-03-20 00:06:23 -07:00
parent a94460c7a7
commit 5b14329483
3 changed files with 14 additions and 4 deletions
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8
src/axi/rtl/taxi_axi_ram_if_rd.sv
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@@ -81,6 +81,12 @@ if (2**$clog2(BYTE_LANES) != BYTE_LANES)
if (s_axi_rd.ADDR_W < ADDR_W)
$fatal(0, "Error: AXI address width is insufficient (instance %m)");
if (s_axi_rd.ARUSER_EN && s_axi_rd.ARUSER_W > AUSER_W)
$fatal(0, "Error: AUESR_W setting is insufficient (instance %m)");
if (s_axi_rd.RUSER_EN && s_axi_rd.RUSER_W > RUSER_W)
$fatal(0, "Error: RUESR_W setting is insufficient (instance %m)");
typedef enum logic [0:0] {
STATE_IDLE,
STATE_BURST
@@ -161,7 +167,7 @@ always_comb begin
read_prot_next = s_axi_rd.arprot;
read_qos_next = s_axi_rd.arqos;
read_region_next = s_axi_rd.arregion;
read_auser_next = s_axi_rd.aruser;
read_auser_next = AUSER_W'(s_axi_rd.aruser);
read_count_next = s_axi_rd.arlen;
read_size_next = s_axi_rd.arsize <= 3'($clog2(STRB_W)) ? s_axi_rd.arsize : 3'($clog2(STRB_W));
read_burst_next = s_axi_rd.arburst;