bslathi19/taxi
1
0
Fork 0
mirror of https://github.com/fpganinja/taxi.git synced 2026-04-09 05:18:44 -07:00
Code Issues Packages Projects Releases Wiki Activity

axi: Clean up user signal width handling in AXI RAM IF modules

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-03-20 00:06:23 -07:00
parent a94460c7a7
commit 5b14329483
3 changed files with 14 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/axi/rtl/taxi_axi_ram_if_wr.sv
View File

@@ -76,6 +76,12 @@ if (2**$clog2(BYTE_LANES) != BYTE_LANES)
if (s_axi_wr.ADDR_W < ADDR_W)
$fatal(0, "Error: AXI address width is insufficient (instance %m)");
if (s_axi_wr.AWUSER_EN && s_axi_wr.AWUSER_W > AUSER_W)
$fatal(0, "Error: AUESR_W setting is insufficient (instance %m)");
if (s_axi_wr.WUSER_EN && s_axi_wr.WUSER_W > WUSER_W)
$fatal(0, "Error: WUESR_W setting is insufficient (instance %m)");
typedef enum logic [1:0] {
STATE_IDLE,
STATE_BURST,
@@ -156,7 +162,7 @@ always_comb begin
write_prot_next = s_axi_wr.awprot;
write_qos_next = s_axi_wr.awqos;
write_region_next = s_axi_wr.awregion;
write_auser_next = s_axi_wr.awuser;
write_auser_next = AUSER_W'(s_axi_wr.awuser);
write_count_next = s_axi_wr.awlen;
write_size_next = s_axi_wr.awsize <= 3'($clog2(STRB_W)) ? s_axi_wr.awsize : 3'($clog2(STRB_W));
write_burst_next = s_axi_wr.awburst;