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axi: Clean up user signal width handling in AXI RAM IF modules

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-03-20 00:06:23 -07:00
parent a94460c7a7
commit 5b14329483
3 changed files with 14 additions and 4 deletions
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8
src/axi/rtl/taxi_axi_ram_if_rd.sv
View File

@@ -81,6 +81,12 @@ if (2**$clog2(BYTE_LANES) != BYTE_LANES)
if (s_axi_rd.ADDR_W < ADDR_W) if (s_axi_rd.ADDR_W < ADDR_W)
$fatal(0, "Error: AXI address width is insufficient (instance %m)"); $fatal(0, "Error: AXI address width is insufficient (instance %m)");
if (s_axi_rd.ARUSER_EN && s_axi_rd.ARUSER_W > AUSER_W)
$fatal(0, "Error: AUESR_W setting is insufficient (instance %m)");
if (s_axi_rd.RUSER_EN && s_axi_rd.RUSER_W > RUSER_W)
$fatal(0, "Error: RUESR_W setting is insufficient (instance %m)");
typedef enum logic [0:0] { typedef enum logic [0:0] {
STATE_IDLE, STATE_IDLE,
STATE_BURST STATE_BURST
@@ -161,7 +167,7 @@ always_comb begin
read_prot_next = s_axi_rd.arprot; read_prot_next = s_axi_rd.arprot;
read_qos_next = s_axi_rd.arqos; read_qos_next = s_axi_rd.arqos;
read_region_next = s_axi_rd.arregion; read_region_next = s_axi_rd.arregion;
read_auser_next = s_axi_rd.aruser; read_auser_next = AUSER_W'(s_axi_rd.aruser);
read_count_next = s_axi_rd.arlen; read_count_next = s_axi_rd.arlen;
read_size_next = s_axi_rd.arsize <= 3'($clog2(STRB_W)) ? s_axi_rd.arsize : 3'($clog2(STRB_W)); read_size_next = s_axi_rd.arsize <= 3'($clog2(STRB_W)) ? s_axi_rd.arsize : 3'($clog2(STRB_W));
read_burst_next = s_axi_rd.arburst; read_burst_next = s_axi_rd.arburst;

2
src/axi/rtl/taxi_axi_ram_if_rdwr.sv
View File

@@ -31,8 +31,6 @@ module taxi_axi_ram_if_rdwr #
parameter WUSER_W = 1, parameter WUSER_W = 1,
// Width of ruser signal // Width of ruser signal
parameter RUSER_W = 1, parameter RUSER_W = 1,
// Width of auser output
// parameter AUSER_W = (ARUSER_EN && (!AWUSER_EN || ARUSER_W > AWUSER_W)) ? ARUSER_W : AWUSER_W,
// Extra pipeline register on output // Extra pipeline register on output
parameter logic PIPELINE_OUTPUT = 1'b0, parameter logic PIPELINE_OUTPUT = 1'b0,
// Interleave read and write burst cycles // Interleave read and write burst cycles

8
src/axi/rtl/taxi_axi_ram_if_wr.sv
View File

@@ -76,6 +76,12 @@ if (2**$clog2(BYTE_LANES) != BYTE_LANES)
if (s_axi_wr.ADDR_W < ADDR_W) if (s_axi_wr.ADDR_W < ADDR_W)
$fatal(0, "Error: AXI address width is insufficient (instance %m)"); $fatal(0, "Error: AXI address width is insufficient (instance %m)");
if (s_axi_wr.AWUSER_EN && s_axi_wr.AWUSER_W > AUSER_W)
$fatal(0, "Error: AUESR_W setting is insufficient (instance %m)");
if (s_axi_wr.WUSER_EN && s_axi_wr.WUSER_W > WUSER_W)
$fatal(0, "Error: WUESR_W setting is insufficient (instance %m)");
typedef enum logic [1:0] { typedef enum logic [1:0] {
STATE_IDLE, STATE_IDLE,
STATE_BURST, STATE_BURST,
@@ -156,7 +162,7 @@ always_comb begin
write_prot_next = s_axi_wr.awprot; write_prot_next = s_axi_wr.awprot;
write_qos_next = s_axi_wr.awqos; write_qos_next = s_axi_wr.awqos;
write_region_next = s_axi_wr.awregion; write_region_next = s_axi_wr.awregion;
write_auser_next = s_axi_wr.awuser; write_auser_next = AUSER_W'(s_axi_wr.awuser);
write_count_next = s_axi_wr.awlen; write_count_next = s_axi_wr.awlen;
write_size_next = s_axi_wr.awsize <= 3'($clog2(STRB_W)) ? s_axi_wr.awsize : 3'($clog2(STRB_W)); write_size_next = s_axi_wr.awsize <= 3'($clog2(STRB_W)) ? s_axi_wr.awsize : 3'($clog2(STRB_W));
write_burst_next = s_axi_wr.awburst; write_burst_next = s_axi_wr.awburst;