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axi: Add SV interface for AXI
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
257
rtl/axi/taxi_axi_if.sv
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257
rtl/axi/taxi_axi_if.sv
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// SPDX-License-Identifier: MIT
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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interface taxi_axi_if #(
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// Width of data bus in bits
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parameter DATA_W = 32,
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// Width of address bus in bits
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parameter ADDR_W = 32,
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// Width of wstrb (width of data bus in words)
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parameter STRB_W = (DATA_W/8),
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// Width of ID signal
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parameter ID_W = 8,
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// Use awuser signal
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parameter logic AWUSER_EN = 1'b0,
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// Width of awuser signal
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parameter AWUSER_W = 1,
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// Use wuser signal
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parameter logic WUSER_EN = 1'b0,
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// Width of wuser signal
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parameter WUSER_W = 1,
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// Use buser signal
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parameter logic BUSER_EN = 1'b0,
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// Width of buser signal
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parameter BUSER_W = 1,
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// Use aruser signal
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parameter logic ARUSER_EN = 1'b0,
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// Width of aruser signal
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parameter ARUSER_W = 1,
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// Use ruser signal
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parameter logic RUSER_EN = 1'b0,
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// Width of ruser signal
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parameter RUSER_W = 1
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)
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();
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// AW
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logic [ID_W-1:0] awid;
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logic [ADDR_W-1:0] awaddr;
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logic [7:0] awlen;
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logic [2:0] awsize;
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logic [1:0] awburst;
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logic awlock;
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logic [3:0] awcache;
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logic [2:0] awprot;
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logic [3:0] awqos;
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logic [3:0] awregion;
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logic [AWUSER_W-1:0] awuser;
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logic awvalid;
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logic awready;
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// W
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logic [DATA_W-1:0] wdata;
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logic [STRB_W-1:0] wstrb;
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logic wlast;
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logic [WUSER_W-1:0] wuser;
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logic wvalid;
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logic wready;
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// B
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logic [ID_W-1:0] bid;
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logic [1:0] bresp;
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logic [BUSER_W-1:0] buser;
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logic bvalid;
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logic bready;
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// AR
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logic [ID_W-1:0] arid;
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logic [ADDR_W-1:0] araddr;
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logic [7:0] arlen;
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logic [2:0] arsize;
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logic [1:0] arburst;
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logic arlock;
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logic [3:0] arcache;
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logic [2:0] arprot;
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logic [3:0] arqos;
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logic [3:0] arregion;
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logic [ARUSER_W-1:0] aruser;
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logic arvalid;
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logic arready;
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// R
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logic [ID_W-1:0] rid;
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logic [DATA_W-1:0] rdata;
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logic [1:0] rresp;
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logic rlast;
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logic [RUSER_W-1:0] ruser;
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logic rvalid;
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logic rready;
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modport wr_mst (
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// AW
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output awid,
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output awaddr,
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output awlen,
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output awsize,
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output awburst,
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output awlock,
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output awcache,
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output awprot,
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output awqos,
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output awregion,
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output awuser,
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output awvalid,
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input awready,
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// W
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output wdata,
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output wstrb,
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output wlast,
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output wuser,
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output wvalid,
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input wready,
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// B
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input bid,
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input bresp,
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input buser,
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input bvalid,
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output bready
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);
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modport rd_mst (
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// AR
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output arid,
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output araddr,
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output arlen,
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output arsize,
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output arburst,
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output arlock,
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output arcache,
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output arprot,
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output arqos,
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output arregion,
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output aruser,
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output arvalid,
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input arready,
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// R
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input rid,
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input rdata,
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input rresp,
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input rlast,
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input ruser,
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input rvalid,
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output rready
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);
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modport wr_slv (
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// AW
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input awid,
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input awaddr,
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input awlen,
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input awsize,
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input awburst,
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input awlock,
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input awcache,
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input awprot,
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input awqos,
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input awregion,
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input awuser,
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input awvalid,
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output awready,
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// W
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input wdata,
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input wstrb,
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input wlast,
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input wuser,
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input wvalid,
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output wready,
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// B
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output bid,
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output bresp,
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output buser,
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output bvalid,
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input bready
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);
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modport rd_slv (
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// AR
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input arid,
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input araddr,
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input arlen,
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input arsize,
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input arburst,
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input arlock,
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input arcache,
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input arprot,
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input arqos,
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input arregion,
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input aruser,
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input arvalid,
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output arready,
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// R
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output rid,
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output rdata,
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output rresp,
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output rlast,
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output ruser,
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output rvalid,
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input rready
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);
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modport wr_mon (
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// AW
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input awid,
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input awaddr,
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input awlen,
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input awsize,
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input awburst,
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input awlock,
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input awcache,
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input awprot,
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input awqos,
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input awregion,
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input awuser,
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input awvalid,
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input awready,
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// W
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input wdata,
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input wstrb,
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input wlast,
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input wuser,
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input wvalid,
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input wready,
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// B
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input bid,
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input bresp,
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input buser,
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input bvalid,
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input bready
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);
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modport rd_mon (
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// AR
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input arid,
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input araddr,
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input arlen,
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input arsize,
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input arburst,
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input arlock,
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input arcache,
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input arprot,
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input arqos,
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input arregion,
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input aruser,
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input arvalid,
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input arready,
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// R
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input rid,
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input rdata,
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input rresp,
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input rlast,
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input ruser,
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input rvalid,
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input rready
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);
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endinterface
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