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zircon: Clean up parametrization

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2026-04-07 15:37:38 -07:00
parent 488558aac5
commit 6c840332e3
1 changed files with 19 additions and 19 deletions
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38
src/zircon/rtl/zircon_ip_len_cksum.sv
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@@ -52,8 +52,8 @@ localparam USER_W = s_axis_pkt.USER_W;
localparam USER_EN = s_axis_pkt.USER_EN && m_axis_pkt.USER_EN;
localparam META_USER_EN = s_axis_pkt.USER_EN && m_axis_meta.USER_EN;
parameter LEVELS = $clog2(DATA_W/8);
parameter OFFSET_W = START_OFFSET/KEEP_W > 1 ? $clog2(START_OFFSET/KEEP_W) : 1;
parameter LEVELS = $clog2(BYTE_LANES);
parameter OFFSET_W = START_OFFSET/BYTE_LANES > 1 ? $clog2(START_OFFSET/BYTE_LANES) : 1;
// check configuration
if (KEEP_W * 8 != DATA_W)
@@ -65,11 +65,11 @@ if (META_W != 32)
if (m_axis_meta.KEEP_W * 8 != META_W)
$fatal(0, "Error: Interface requires byte (8-bit) granularity (instance %m)");
logic [OFFSET_W-1:0] offset_reg = OFFSET_W'(START_OFFSET/KEEP_W);
logic [KEEP_W-1:0] mask_reg = {KEEP_W{1'b1}} << START_OFFSET;
logic [OFFSET_W-1:0] offset_reg = OFFSET_W'(START_OFFSET/BYTE_LANES);
logic [BYTE_LANES-1:0] mask_reg = {BYTE_LANES{1'b1}} << START_OFFSET;
logic [DATA_W-1:0] sum_reg[LEVELS-2:0];
logic [(LEVELS-1)*4-1:0] len_reg[LEVELS-2:0];
logic [(BYTE_LANES/4)*17-1:0] sum_reg[LEVELS-2:0];
logic [(BYTE_LANES/4)*3-1:0] len_reg[LEVELS-2:0];
logic [ID_W-1:0] id_reg[LEVELS-2:0];
logic [DEST_W-1:0] dest_reg[LEVELS-2:0];
logic [USER_W-1:0] user_reg[LEVELS-2:0];
@@ -117,7 +117,7 @@ assign m_axis_meta.tvalid = m_axis_meta_valid_reg;
// Mask input data
wire [BYTE_LANES-1:0][BYTE_W-1:0] pkt_data_masked;
for (genvar j = 0; j < KEEP_W; j = j + 1) begin
for (genvar j = 0; j < BYTE_LANES; j = j + 1) begin
assign pkt_data_masked[j] = (s_axis_pkt.tkeep[j] && mask_reg[j]) ? s_axis_pkt.tdata[j*8 +: 8] : 8'd0;
end
@@ -125,7 +125,7 @@ always_ff @(posedge clk) begin
sum_valid_reg[0] <= 1'b0;
if (s_axis_pkt.tvalid && s_axis_pkt.tready) begin
for (integer i = 0; i < DATA_W/8/4; i = i + 1) begin
for (integer i = 0; i < BYTE_LANES/4; i = i + 1) begin
sum_reg[0][i*17 +: 17] <= {pkt_data_masked[4*i+0], pkt_data_masked[4*i+1]} + {pkt_data_masked[4*i+2], pkt_data_masked[4*i+3]};
len_reg[0][i*3 +: 3] <= 3'(s_axis_pkt.tkeep[4*i+0]) + 3'(s_axis_pkt.tkeep[4*i+1]) + 3'(s_axis_pkt.tkeep[4*i+2]) + 3'(s_axis_pkt.tkeep[4*i+3]);
end
@@ -136,23 +136,23 @@ always_ff @(posedge clk) begin
user_reg[0] <= s_axis_pkt.tuser;
if (s_axis_pkt.tlast) begin
offset_reg <= OFFSET_W'(START_OFFSET/KEEP_W);
mask_reg <= {KEEP_W{1'b1}} << START_OFFSET;
end else if (START_OFFSET < KEEP_W || offset_reg == 0) begin
mask_reg <= {KEEP_W{1'b1}};
offset_reg <= OFFSET_W'(START_OFFSET/BYTE_LANES);
mask_reg <= {BYTE_LANES{1'b1}} << START_OFFSET;
end else if (START_OFFSET < BYTE_LANES || offset_reg == 0) begin
mask_reg <= {BYTE_LANES{1'b1}};
end else begin
offset_reg <= offset_reg - 1;
if (offset_reg == 1) begin
mask_reg <= {KEEP_W{1'b1}} << (START_OFFSET%KEEP_W);
mask_reg <= {BYTE_LANES{1'b1}} << (START_OFFSET%BYTE_LANES);
end else begin
mask_reg <= {KEEP_W{1'b0}};
mask_reg <= {BYTE_LANES{1'b0}};
end
end
end
if (rst) begin
offset_reg <= OFFSET_W'(START_OFFSET/KEEP_W);
mask_reg <= {KEEP_W{1'b1}} << START_OFFSET;
offset_reg <= OFFSET_W'(START_OFFSET/BYTE_LANES);
mask_reg <= {BYTE_LANES{1'b1}} << START_OFFSET;
sum_valid_reg[0] <= 1'b0;
end
end
@@ -163,7 +163,7 @@ for (genvar l = 1; l < LEVELS-1; l = l + 1) begin
sum_valid_reg[l] <= 1'b0;
if (sum_valid_reg[l-1]) begin
for (integer i = 0; i < DATA_W/8/4/2**l; i = i + 1) begin
for (integer i = 0; i < BYTE_LANES/4/2**l; i = i + 1) begin
sum_reg[l][i*(17+l) +: (17+l)] <= sum_reg[l-1][(i*2+0)*(17+l-1) +: (17+l-1)] + sum_reg[l-1][(i*2+1)*(17+l-1) +: (17+l-1)];
len_reg[l][i*(3+l) +: (3+l)] <= len_reg[l-1][(i*2+0)*(3+l-1) +: (3+l-1)] + len_reg[l-1][(i*2+1)*(3+l-1) +: (3+l-1)];
end
@@ -188,7 +188,7 @@ always_ff @(posedge clk) begin
sum_acc_temp = (16+LEVELS)'(sum_acc_temp[15:0] + 16'(sum_acc_temp >> 16));
sum_acc_temp = (16+LEVELS)'(sum_acc_temp[15:0] + 16'(sum_acc_temp[16]));
m_axis_meta_len_reg <= len_acc_reg + 16'(len_reg[LEVELS-2][3+LEVELS-1-1:0]);
m_axis_meta_len_reg <= len_acc_reg + 16'(len_reg[LEVELS-2][3+LEVELS-2-1:0]);
m_axis_meta_csum_reg <= sum_acc_temp[15:0];
m_axis_meta_id_reg <= id_reg[LEVELS-2];
m_axis_meta_dest_reg <= dest_reg[LEVELS-2];
@@ -201,7 +201,7 @@ always_ff @(posedge clk) begin
len_acc_reg <= '0;
end else begin
sum_acc_reg <= sum_acc_temp[15:0];
len_acc_reg <= len_acc_reg + 16'(len_reg[LEVELS-2][3+LEVELS-1-1:0]);
len_acc_reg <= len_acc_reg + 16'(len_reg[LEVELS-2][3+LEVELS-2-1:0]);
end
end