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xfcp: Add XFCP AXI lite module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
675
rtl/xfcp/taxi_xfcp_mod_axil.sv
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675
rtl/xfcp/taxi_xfcp_mod_axil.sv
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@@ -0,0 +1,675 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2019-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* XFCP AXI lite module
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*/
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module taxi_xfcp_mod_axil #
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(
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parameter logic [15:0] XFCP_ID_TYPE = 16'h8001,
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parameter XFCP_ID_STR = "AXIL Master",
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parameter logic [8*16-1:0] XFCP_EXT_ID = 0,
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parameter XFCP_EXT_ID_STR = "",
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parameter COUNT_SIZE = 16
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* XFCP upstream port
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*/
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taxi_axis_if.snk up_xfcp_in,
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taxi_axis_if.src up_xfcp_out,
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/*
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* AXI lite master interface
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*/
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taxi_axil_if.wr_mst m_axil_wr,
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taxi_axil_if.rd_mst m_axil_rd
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);
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// TODO various refactoring to fix width issues, among other things
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// verilator lint_off WIDTH
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localparam DATA_W = m_axil_wr.DATA_W;
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localparam ADDR_W = m_axil_wr.ADDR_W;
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localparam STRB_W = m_axil_wr.STRB_W;
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// for interfaces that are more than one word wide, disable address lines
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localparam VALID_ADDR_W = ADDR_W - $clog2(STRB_W);
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// width of data port in words
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localparam BYTE_LANES = STRB_W;
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// size of words
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localparam BYTE_W = DATA_W/BYTE_LANES;
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localparam BYTE_AW = $clog2((BYTE_W+7)/8);
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localparam WORD_AW = BYTE_AW + $clog2(STRB_W);
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localparam BYTE_AM = {1'b0, {BYTE_AW{1'b1}}};
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localparam WORD_AM = {1'b0, {WORD_AW{1'b1}}};
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localparam ADDR_W_ADJ = ADDR_W+BYTE_AW;
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localparam COUNT_BYTE_LANES = (COUNT_SIZE+8-1)/8;
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localparam ADDR_BYTE_LANES = (ADDR_W_ADJ+8-1)/8;
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// check configuration
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if (BYTE_LANES * BYTE_W != DATA_W)
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$fatal(0, "Error: AXI data width not evenly divisible (instance %m)");
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if (2**$clog2(BYTE_LANES) != BYTE_LANES)
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$fatal(0, "Error: AXI word width must be even power of two (instance %m)");
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if (8*2**$clog2(BYTE_W/8) != BYTE_W)
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$fatal(0, "Error: AXI word size must be a power of two multiple of 8 (instance %m)");
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localparam START_TAG = 8'hFF;
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localparam RPATH_TAG = 8'hFE;
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localparam READ_REQ = 8'h10;
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localparam READ_RESP = 8'h11;
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localparam WRITE_REQ = 8'h12;
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localparam WRITE_RESP = 8'h13;
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localparam ID_REQ = 8'hFE;
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localparam ID_RESP = 8'hFF;
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// ID ROM
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localparam ID_PTR_W = (XFCP_EXT_ID != 0 || XFCP_EXT_ID_STR != 0) ? 6 : 5;
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localparam ID_ROM_SIZE = 2**ID_PTR_W;
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reg [7:0] id_rom[ID_ROM_SIZE];
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reg [ID_PTR_W-1:0] id_ptr_reg = '0, id_ptr_next;
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integer j;
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initial begin
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// init ID ROM
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for (integer i = 0; i < ID_ROM_SIZE; i = i + 1) begin
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id_rom[i] = 0;
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end
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// binary part
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{id_rom[1], id_rom[0]} = 16'h8000 | XFCP_ID_TYPE; // module type
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{id_rom[3], id_rom[2]} = 16'(ADDR_W); // address bus width
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{id_rom[5], id_rom[4]} = 16'(DATA_W); // data bus width
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{id_rom[7], id_rom[6]} = 16'(BYTE_W); // word size
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{id_rom[9], id_rom[8]} = 16'(COUNT_SIZE); // count size
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// string part
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// find string length
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j = 0;
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for (integer i = 1; i <= 16; i = i + 1) begin
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if (j == i-1 && (XFCP_ID_STR >> (i*8)) > 0) begin
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j = i;
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end
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end
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// pack string
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for (integer i = 0; i <= j; i = i + 1) begin
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id_rom[i+16] = XFCP_ID_STR[8*(j-i) +: 8];
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end
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if (XFCP_EXT_ID != 0 || XFCP_EXT_ID_STR != 0) begin
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// extended ID
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// binary part
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for (integer i = 0; i < 16; i = i + 1) begin
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id_rom[i+32] = XFCP_EXT_ID[8*i +: 8];
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end
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// string part
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// find string length
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j = 0;
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for (integer i = 1; i <= 16; i = i + 1) begin
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if (j == i-1 && (XFCP_EXT_ID_STR >> (i*8)) > 0) begin
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j = i;
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end
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end
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// pack string
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for (integer i = 0; i <= j; i = i + 1) begin
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id_rom[i+48] = XFCP_EXT_ID_STR[8*(j-i) +: 8];
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end
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end
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end
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localparam [3:0]
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STATE_IDLE = 4'd0,
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STATE_HEADER_1 = 4'd1,
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STATE_HEADER_2 = 4'd2,
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STATE_HEADER_3 = 4'd3,
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STATE_READ_1 = 4'd4,
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STATE_READ_2 = 4'd5,
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STATE_WRITE_1 = 4'd6,
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STATE_WRITE_2 = 4'd7,
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STATE_WAIT_LAST = 4'd8,
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STATE_ID = 4'd9;
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logic [3:0] state_reg = STATE_IDLE, state_next;
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logic [COUNT_SIZE-1:0] ptr_reg = '0, ptr_next;
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logic [7:0] count_reg = 8'd0, count_next;
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logic last_cycle_reg = 1'b0;
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logic write_reg = 1'b0, write_next;
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logic [ADDR_W_ADJ-1:0] addr_reg = '0, addr_next;
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logic [DATA_W-1:0] data_reg = '0, data_next;
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logic up_xfcp_in_tready_reg = 1'b0, up_xfcp_in_tready_next;
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logic m_axil_awvalid_reg = 1'b0, m_axil_awvalid_next;
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logic [STRB_W-1:0] m_axil_wstrb_reg = '0, m_axil_wstrb_next;
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logic m_axil_wvalid_reg = 1'b0, m_axil_wvalid_next;
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logic m_axil_bready_reg = 1'b0, m_axil_bready_next;
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logic m_axil_arvalid_reg = 1'b0, m_axil_arvalid_next;
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logic m_axil_rready_reg = 1'b0, m_axil_rready_next;
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// internal datapath
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logic [7:0] up_xfcp_out_tdata_int;
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logic up_xfcp_out_tvalid_int;
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logic up_xfcp_out_tready_int_reg = 1'b0;
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logic up_xfcp_out_tlast_int;
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logic up_xfcp_out_tuser_int;
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wire up_xfcp_out_tready_int_early;
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assign up_xfcp_in.tready = up_xfcp_in_tready_reg;
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assign m_axil_wr.awaddr = addr_reg;
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assign m_axil_wr.awprot = 3'b010;
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assign m_axil_wr.awuser = '0;
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assign m_axil_wr.awvalid = m_axil_awvalid_reg;
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assign m_axil_wr.wdata = data_reg;
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assign m_axil_wr.wstrb = m_axil_wstrb_reg;
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assign m_axil_wr.wuser = '0;
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assign m_axil_wr.wvalid = m_axil_wvalid_reg;
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assign m_axil_wr.bready = m_axil_bready_reg;
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assign m_axil_rd.araddr = addr_reg;
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assign m_axil_rd.arprot = 3'b010;
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assign m_axil_rd.aruser = '0;
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assign m_axil_rd.arvalid = m_axil_arvalid_reg;
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assign m_axil_rd.rready = m_axil_rready_reg;
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always_comb begin
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state_next = STATE_IDLE;
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ptr_next = ptr_reg;
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count_next = count_reg;
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write_next = write_reg;
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id_ptr_next = id_ptr_reg;
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up_xfcp_in_tready_next = 1'b0;
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up_xfcp_out_tdata_int = '0;
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up_xfcp_out_tvalid_int = 1'b0;
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up_xfcp_out_tlast_int = 1'b0;
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up_xfcp_out_tuser_int = 1'b0;
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addr_next = addr_reg;
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data_next = data_reg;
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m_axil_awvalid_next = m_axil_awvalid_reg && !m_axil_wr.awready;
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m_axil_wstrb_next = m_axil_wstrb_reg;
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m_axil_wvalid_next = m_axil_wvalid_reg && !m_axil_wr.wready;
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m_axil_bready_next = 1'b0;
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m_axil_arvalid_next = m_axil_arvalid_reg && !m_axil_rd.arready;
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m_axil_rready_next = 1'b0;
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case (state_reg)
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STATE_IDLE: begin
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// idle, wait for start of packet
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up_xfcp_in_tready_next = up_xfcp_out_tready_int_early;
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id_ptr_next = '0;
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if (up_xfcp_in.tready && up_xfcp_in.tvalid) begin
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if (up_xfcp_in.tlast) begin
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// last asserted, ignore cycle
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state_next = STATE_IDLE;
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end else if (up_xfcp_in.tdata == RPATH_TAG) begin
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// need to pass through rpath
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up_xfcp_out_tdata_int = up_xfcp_in.tdata;
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up_xfcp_out_tvalid_int = 1'b1;
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up_xfcp_out_tlast_int = 1'b0;
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up_xfcp_out_tuser_int = 1'b0;
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state_next = STATE_HEADER_1;
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end else if (up_xfcp_in.tdata == START_TAG) begin
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// process header
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up_xfcp_out_tdata_int = up_xfcp_in.tdata;
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up_xfcp_out_tvalid_int = 1'b1;
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up_xfcp_out_tlast_int = 1'b0;
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up_xfcp_out_tuser_int = 1'b0;
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state_next = STATE_HEADER_2;
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end else begin
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// bad start byte, drop packet
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state_next = STATE_WAIT_LAST;
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end
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end else begin
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state_next = STATE_IDLE;
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end
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end
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STATE_HEADER_1: begin
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// transfer through header
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up_xfcp_in_tready_next = up_xfcp_out_tready_int_early;
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if (up_xfcp_in.tready && up_xfcp_in.tvalid) begin
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// transfer through
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up_xfcp_out_tdata_int = up_xfcp_in.tdata;
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up_xfcp_out_tvalid_int = 1'b1;
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up_xfcp_out_tlast_int = 1'b0;
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up_xfcp_out_tuser_int = 1'b0;
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if (up_xfcp_in.tlast) begin
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// last asserted in header, mark as such and drop
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up_xfcp_out_tuser_int = 1'b1;
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state_next = STATE_IDLE;
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end else if (up_xfcp_in.tdata == START_TAG) begin
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// process header
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state_next = STATE_HEADER_2;
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end else begin
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state_next = STATE_HEADER_1;
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end
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end else begin
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state_next = STATE_HEADER_1;
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end
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end
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STATE_HEADER_2: begin
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// read packet type
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up_xfcp_in_tready_next = up_xfcp_out_tready_int_early;
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if (up_xfcp_in.tready && up_xfcp_in.tvalid) begin
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if (up_xfcp_in.tdata == READ_REQ && !up_xfcp_in.tlast) begin
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// start of read
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up_xfcp_out_tdata_int = READ_RESP;
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up_xfcp_out_tvalid_int = 1'b1;
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up_xfcp_out_tlast_int = 1'b0;
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up_xfcp_out_tuser_int = 1'b0;
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write_next = 1'b0;
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count_next = 8'(COUNT_BYTE_LANES+ADDR_BYTE_LANES-1);
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state_next = STATE_HEADER_3;
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end else if (up_xfcp_in.tdata == WRITE_REQ && !up_xfcp_in.tlast) begin
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// start of write
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up_xfcp_out_tdata_int = WRITE_RESP;
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up_xfcp_out_tvalid_int = 1'b1;
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up_xfcp_out_tlast_int = 1'b0;
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up_xfcp_out_tuser_int = 1'b0;
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write_next = 1'b1;
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count_next = 8'(COUNT_BYTE_LANES+ADDR_BYTE_LANES-1);
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state_next = STATE_HEADER_3;
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end else if (up_xfcp_in.tdata == ID_REQ) begin
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// identify
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up_xfcp_out_tdata_int = ID_RESP;
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up_xfcp_out_tvalid_int = 1'b1;
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up_xfcp_out_tlast_int = 1'b0;
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up_xfcp_out_tuser_int = 1'b0;
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state_next = STATE_ID;
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end else begin
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// invalid start of packet
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up_xfcp_out_tvalid_int = 1'b1;
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up_xfcp_out_tlast_int = 1'b1;
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up_xfcp_out_tuser_int = 1'b1;
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if (up_xfcp_in.tlast) begin
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state_next = STATE_IDLE;
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end else begin
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state_next = STATE_WAIT_LAST;
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end
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end
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end else begin
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state_next = STATE_HEADER_2;
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end
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end
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STATE_HEADER_3: begin
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// store address and length
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up_xfcp_in_tready_next = up_xfcp_out_tready_int_early;
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if (up_xfcp_in.tready && up_xfcp_in.tvalid) begin
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// pass through
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up_xfcp_out_tdata_int = up_xfcp_in.tdata;
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up_xfcp_out_tvalid_int = 1'b1;
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up_xfcp_out_tlast_int = 1'b0;
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up_xfcp_out_tuser_int = 1'b0;
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// store pointers
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if (count_reg < COUNT_BYTE_LANES) begin
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ptr_next[8*(COUNT_BYTE_LANES-count_reg-1) +: 8] = up_xfcp_in.tdata;
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end else begin
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addr_next[8*(ADDR_BYTE_LANES-(count_reg-COUNT_BYTE_LANES)-1) +: 8] = up_xfcp_in.tdata;
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end
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count_next = count_reg - 1;
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if (count_reg == 0) begin
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// end of header
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// set initial word offset
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count_next = addr_reg & WORD_AM;
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m_axil_wstrb_next = '0;
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data_next = '0;
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if (write_reg) begin
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// start writing
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if (up_xfcp_in.tlast) begin
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// end of frame in header
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up_xfcp_out_tlast_int = 1'b1;
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up_xfcp_out_tuser_int = 1'b1;
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state_next = STATE_IDLE;
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end else begin
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up_xfcp_out_tlast_int = 1'b1;
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state_next = STATE_WRITE_1;
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end
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end else begin
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// start reading
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up_xfcp_in_tready_next = !(last_cycle_reg || (up_xfcp_in.tvalid && up_xfcp_in.tlast));
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m_axil_arvalid_next = 1'b1;
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m_axil_rready_next = 1'b1;
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state_next = STATE_READ_1;
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end
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end else begin
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if (up_xfcp_in.tlast) begin
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// end of frame in header
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up_xfcp_out_tlast_int = 1'b1;
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up_xfcp_out_tuser_int = 1'b1;
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state_next = STATE_IDLE;
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end else begin
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state_next = STATE_HEADER_3;
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end
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end
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end else begin
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state_next = STATE_HEADER_3;
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end
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end
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STATE_READ_1: begin
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// wait for data
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m_axil_rready_next = 1'b1;
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// drop padding
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up_xfcp_in_tready_next = !(last_cycle_reg || (up_xfcp_in.tvalid && up_xfcp_in.tlast));
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if (m_axil_rd.rready && m_axil_rd.rvalid) begin
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// read cycle complete, store result
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m_axil_rready_next = 1'b0;
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data_next = m_axil_rd.rdata;
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addr_next = addr_reg + (1 << (ADDR_W-VALID_ADDR_W+BYTE_AW));
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state_next = STATE_READ_2;
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end else begin
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state_next = STATE_READ_1;
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end
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end
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STATE_READ_2: begin
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// send data
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// drop padding
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up_xfcp_in_tready_next = !(last_cycle_reg || (up_xfcp_in.tvalid && up_xfcp_in.tlast));
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||||
if (up_xfcp_out_tready_int_reg) begin
|
||||
// transfer word and update pointers
|
||||
up_xfcp_out_tdata_int = data_reg[8*count_reg +: 8];
|
||||
up_xfcp_out_tvalid_int = 1'b1;
|
||||
up_xfcp_out_tlast_int = 1'b0;
|
||||
up_xfcp_out_tuser_int = 1'b0;
|
||||
count_next = count_reg + 1;
|
||||
ptr_next = ptr_reg - 1;
|
||||
if (ptr_reg == 1) begin
|
||||
// last word of read
|
||||
up_xfcp_out_tlast_int = 1'b1;
|
||||
if (!(last_cycle_reg || (up_xfcp_in.tvalid && up_xfcp_in.tlast))) begin
|
||||
state_next = STATE_WAIT_LAST;
|
||||
end else begin
|
||||
up_xfcp_in_tready_next = up_xfcp_out_tready_int_early;
|
||||
state_next = STATE_IDLE;
|
||||
end
|
||||
end else if (count_reg == (STRB_W*BYTE_W/8)-1) begin
|
||||
// end of stored data word; read the next one
|
||||
count_next = 0;
|
||||
m_axil_arvalid_next = 1'b1;
|
||||
m_axil_rready_next = 1'b1;
|
||||
state_next = STATE_READ_1;
|
||||
end else begin
|
||||
state_next = STATE_READ_2;
|
||||
end
|
||||
end else begin
|
||||
state_next = STATE_READ_2;
|
||||
end
|
||||
end
|
||||
STATE_WRITE_1: begin
|
||||
// write data
|
||||
up_xfcp_in_tready_next = 1'b1;
|
||||
|
||||
if (up_xfcp_in.tready && up_xfcp_in.tvalid) begin
|
||||
// store word
|
||||
data_next[8*count_reg +: 8] = up_xfcp_in.tdata;
|
||||
count_next = count_reg + 1;
|
||||
ptr_next = ptr_reg - 1;
|
||||
m_axil_wstrb_next[count_reg >> ((BYTE_W/8)-1)] = 1'b1;
|
||||
if (count_reg == (STRB_W*BYTE_W/8)-1 || ptr_reg == 1) begin
|
||||
// have full word or at end of block, start write operation
|
||||
count_next = 0;
|
||||
up_xfcp_in_tready_next = 1'b0;
|
||||
m_axil_awvalid_next = 1'b1;
|
||||
m_axil_wvalid_next = 1'b1;
|
||||
m_axil_bready_next = 1'b1;
|
||||
state_next = STATE_WRITE_2;
|
||||
if (up_xfcp_in.tlast) begin
|
||||
// last asserted, nothing further to write
|
||||
ptr_next = 0;
|
||||
end
|
||||
end else if (up_xfcp_in.tlast) begin
|
||||
// last asserted, return to idle
|
||||
state_next = STATE_IDLE;
|
||||
end else begin
|
||||
state_next = STATE_WRITE_1;
|
||||
end
|
||||
end else begin
|
||||
state_next = STATE_WRITE_1;
|
||||
end
|
||||
end
|
||||
STATE_WRITE_2: begin
|
||||
// wait for write completion
|
||||
m_axil_bready_next = 1'b1;
|
||||
|
||||
if (m_axil_wr.bready && m_axil_wr.bvalid) begin
|
||||
// end of write operation
|
||||
data_next = '0;
|
||||
addr_next = addr_reg + (1 << (ADDR_W-VALID_ADDR_W+BYTE_AW));
|
||||
m_axil_bready_next = 1'b0;
|
||||
m_axil_wstrb_next = '0;
|
||||
if (ptr_reg == 0) begin
|
||||
// done writing
|
||||
if (!last_cycle_reg) begin
|
||||
up_xfcp_in_tready_next = 1'b1;
|
||||
state_next = STATE_WAIT_LAST;
|
||||
end else begin
|
||||
up_xfcp_in_tready_next = up_xfcp_out_tready_int_early;
|
||||
state_next = STATE_IDLE;
|
||||
end
|
||||
end else begin
|
||||
// more to write
|
||||
state_next = STATE_WRITE_1;
|
||||
end
|
||||
end else begin
|
||||
state_next = STATE_WRITE_2;
|
||||
end
|
||||
end
|
||||
STATE_ID: begin
|
||||
// send ID
|
||||
|
||||
// drop padding
|
||||
up_xfcp_in_tready_next = !(last_cycle_reg || (up_xfcp_in.tvalid && up_xfcp_in.tlast));
|
||||
|
||||
up_xfcp_out_tdata_int = id_rom[id_ptr_reg];
|
||||
up_xfcp_out_tvalid_int = 1'b1;
|
||||
up_xfcp_out_tlast_int = 1'b0;
|
||||
up_xfcp_out_tuser_int = 1'b0;
|
||||
|
||||
if (up_xfcp_out_tready_int_reg) begin
|
||||
// increment pointer
|
||||
id_ptr_next = id_ptr_reg + 1;
|
||||
if (id_ptr_reg == ID_PTR_W'(ID_ROM_SIZE-1)) begin
|
||||
// read out whole ID
|
||||
up_xfcp_out_tlast_int = 1'b1;
|
||||
if (!(last_cycle_reg || (up_xfcp_in.tvalid && up_xfcp_in.tlast))) begin
|
||||
state_next = STATE_WAIT_LAST;
|
||||
end else begin
|
||||
up_xfcp_in_tready_next = up_xfcp_out_tready_int_early;
|
||||
state_next = STATE_IDLE;
|
||||
end
|
||||
end else begin
|
||||
state_next = STATE_ID;
|
||||
end
|
||||
end else begin
|
||||
state_next = STATE_ID;
|
||||
end
|
||||
end
|
||||
STATE_WAIT_LAST: begin
|
||||
// wait for end of frame
|
||||
up_xfcp_in_tready_next = 1'b1;
|
||||
|
||||
if (up_xfcp_in.tready && up_xfcp_in.tvalid) begin
|
||||
// wait for tlast
|
||||
if (up_xfcp_in.tlast) begin
|
||||
up_xfcp_in_tready_next = up_xfcp_out_tready_int_early;
|
||||
state_next = STATE_IDLE;
|
||||
end else begin
|
||||
state_next = STATE_WAIT_LAST;
|
||||
end
|
||||
end else begin
|
||||
state_next = STATE_WAIT_LAST;
|
||||
end
|
||||
end
|
||||
default: begin
|
||||
// return to idle
|
||||
state_next = STATE_IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
state_reg <= state_next;
|
||||
|
||||
id_ptr_reg <= id_ptr_next;
|
||||
|
||||
ptr_reg <= ptr_next;
|
||||
count_reg <= count_next;
|
||||
write_reg <= write_next;
|
||||
|
||||
if (up_xfcp_in.tready && up_xfcp_in.tvalid) begin
|
||||
last_cycle_reg <= up_xfcp_in.tlast;
|
||||
end
|
||||
|
||||
addr_reg <= addr_next;
|
||||
data_reg <= data_next;
|
||||
|
||||
up_xfcp_in_tready_reg <= up_xfcp_in_tready_next;
|
||||
|
||||
m_axil_awvalid_reg <= m_axil_awvalid_next;
|
||||
m_axil_wstrb_reg <= m_axil_wstrb_next;
|
||||
m_axil_wvalid_reg <= m_axil_wvalid_next;
|
||||
m_axil_bready_reg <= m_axil_bready_next;
|
||||
m_axil_arvalid_reg <= m_axil_arvalid_next;
|
||||
m_axil_rready_reg <= m_axil_rready_next;
|
||||
|
||||
if (rst) begin
|
||||
state_reg <= STATE_IDLE;
|
||||
up_xfcp_in_tready_reg <= 1'b0;
|
||||
m_axil_awvalid_reg <= 1'b0;
|
||||
m_axil_wvalid_reg <= 1'b0;
|
||||
m_axil_bready_reg <= 1'b0;
|
||||
m_axil_arvalid_reg <= 1'b0;
|
||||
m_axil_rready_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// output datapath logic
|
||||
logic [7:0] up_xfcp_out_tdata_reg = '0;
|
||||
logic up_xfcp_out_tvalid_reg = 1'b0, up_xfcp_out_tvalid_next;
|
||||
logic up_xfcp_out_tlast_reg = 1'b0;
|
||||
logic up_xfcp_out_tuser_reg = 1'b0;
|
||||
|
||||
logic [7:0] temp_up_xfcp_tdata_reg = '0;
|
||||
logic temp_up_xfcp_tvalid_reg = 1'b0, temp_up_xfcp_tvalid_next;
|
||||
logic temp_up_xfcp_tlast_reg = 1'b0;
|
||||
logic temp_up_xfcp_tuser_reg = 1'b0;
|
||||
|
||||
// datapath control
|
||||
reg store_up_xfcp_int_to_output;
|
||||
reg store_up_xfcp_int_to_temp;
|
||||
reg store_up_xfcp_temp_to_output;
|
||||
|
||||
assign up_xfcp_out.tdata = up_xfcp_out_tdata_reg;
|
||||
assign up_xfcp_out.tkeep = '1;
|
||||
assign up_xfcp_out.tstrb = up_xfcp_out.tkeep;
|
||||
assign up_xfcp_out.tvalid = up_xfcp_out_tvalid_reg;
|
||||
assign up_xfcp_out.tlast = up_xfcp_out_tlast_reg;
|
||||
assign up_xfcp_out.tid = '0;
|
||||
assign up_xfcp_out.tdest = '0;
|
||||
assign up_xfcp_out.tuser = up_xfcp_out_tuser_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
assign up_xfcp_out_tready_int_early = up_xfcp_out.tready || (!temp_up_xfcp_tvalid_reg && (!up_xfcp_out_tvalid_reg || !up_xfcp_out_tvalid_int));
|
||||
|
||||
always_comb begin
|
||||
// transfer sink ready state to source
|
||||
up_xfcp_out_tvalid_next = up_xfcp_out_tvalid_reg;
|
||||
temp_up_xfcp_tvalid_next = temp_up_xfcp_tvalid_reg;
|
||||
|
||||
store_up_xfcp_int_to_output = 1'b0;
|
||||
store_up_xfcp_int_to_temp = 1'b0;
|
||||
store_up_xfcp_temp_to_output = 1'b0;
|
||||
|
||||
if (up_xfcp_out_tready_int_reg) begin
|
||||
// input is ready
|
||||
if (up_xfcp_out.tready || !up_xfcp_out_tvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
up_xfcp_out_tvalid_next = up_xfcp_out_tvalid_int;
|
||||
store_up_xfcp_int_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_up_xfcp_tvalid_next = up_xfcp_out_tvalid_int;
|
||||
store_up_xfcp_int_to_temp = 1'b1;
|
||||
end
|
||||
end else if (up_xfcp_out.tready) begin
|
||||
// input is not ready, but output is ready
|
||||
up_xfcp_out_tvalid_next = temp_up_xfcp_tvalid_reg;
|
||||
temp_up_xfcp_tvalid_next = 1'b0;
|
||||
store_up_xfcp_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
up_xfcp_out_tvalid_reg <= up_xfcp_out_tvalid_next;
|
||||
up_xfcp_out_tready_int_reg <= up_xfcp_out_tready_int_early;
|
||||
temp_up_xfcp_tvalid_reg <= temp_up_xfcp_tvalid_next;
|
||||
|
||||
// datapath
|
||||
if (store_up_xfcp_int_to_output) begin
|
||||
up_xfcp_out_tdata_reg <= up_xfcp_out_tdata_int;
|
||||
up_xfcp_out_tlast_reg <= up_xfcp_out_tlast_int;
|
||||
up_xfcp_out_tuser_reg <= up_xfcp_out_tuser_int;
|
||||
end else if (store_up_xfcp_temp_to_output) begin
|
||||
up_xfcp_out_tdata_reg <= temp_up_xfcp_tdata_reg;
|
||||
up_xfcp_out_tlast_reg <= temp_up_xfcp_tlast_reg;
|
||||
up_xfcp_out_tuser_reg <= temp_up_xfcp_tuser_reg;
|
||||
end
|
||||
|
||||
if (store_up_xfcp_int_to_temp) begin
|
||||
temp_up_xfcp_tdata_reg <= up_xfcp_out_tdata_int;
|
||||
temp_up_xfcp_tlast_reg <= up_xfcp_out_tlast_int;
|
||||
temp_up_xfcp_tuser_reg <= up_xfcp_out_tuser_int;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
up_xfcp_out_tvalid_reg <= 1'b0;
|
||||
up_xfcp_out_tready_int_reg <= 1'b0;
|
||||
temp_up_xfcp_tvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user