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eth: Use unpacked arrays for multidimensional ports

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-03-07 11:05:58 -08:00
parent 6e4988f010
commit ed9e8ffab3
40 changed files with 408 additions and 440 deletions
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11
example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv
View File

@@ -205,12 +205,11 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
/*
* PTP clock
*/
.tx_ptp_ts('0),
.tx_ptp_ts('{CNT{'0}}),
.tx_ptp_ts_step('0),
.rx_ptp_ts('0),
.rx_ptp_ts('{CNT{'0}}),
.rx_ptp_ts_step('0),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
@@ -223,11 +222,11 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req('0),
.tx_pfc_req('{CNT{'0}}),
.tx_pfc_resend('0),
.rx_pfc_en('0),
.rx_pfc_en('{CNT{'0}}),
.rx_pfc_req(),
.rx_pfc_ack('0),
.rx_pfc_ack('{CNT{'0}}),
/*
* Pause interface

11
example/Alveo/fpga/rtl/fpga_core.sv
View File

@@ -255,12 +255,11 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
/*
* PTP clock
*/
.tx_ptp_ts('0),
.tx_ptp_ts('{CNT{'0}}),
.tx_ptp_ts_step('0),
.rx_ptp_ts('0),
.rx_ptp_ts('{CNT{'0}}),
.rx_ptp_ts_step('0),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
@@ -273,11 +272,11 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req('0),
.tx_pfc_req('{CNT{'0}}),
.tx_pfc_resend('0),
.rx_pfc_en('0),
.rx_pfc_en('{CNT{'0}}),
.rx_pfc_req(),
.rx_pfc_ack('0),
.rx_pfc_ack('{CNT{'0}}),
/*
* Pause interface

11
example/KCU105/fpga/rtl/fpga_core.sv
View File

@@ -484,12 +484,11 @@ end else begin : sfp_mac
/*
* PTP clock
*/
.tx_ptp_ts('0),
.tx_ptp_ts('{2{'0}}),
.tx_ptp_ts_step('0),
.rx_ptp_ts('0),
.rx_ptp_ts('{2{'0}}),
.rx_ptp_ts_step('0),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
@@ -502,11 +501,11 @@ end else begin : sfp_mac
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req('0),
.tx_pfc_req('{2{'0}}),
.tx_pfc_resend('0),
.rx_pfc_en('0),
.rx_pfc_en('{2{'0}}),
.rx_pfc_req(),
.rx_pfc_ack('0),
.rx_pfc_ack('{2{'0}}),
/*
* Pause interface

11
example/KR260/fpga/rtl/fpga_core.sv
View File

@@ -429,12 +429,11 @@ end else begin : sfp_mac
/*
* PTP clock
*/
.tx_ptp_ts('0),
.tx_ptp_ts('{1{'0}}),
.tx_ptp_ts_step('0),
.rx_ptp_ts('0),
.rx_ptp_ts('{1{'0}}),
.rx_ptp_ts_step('0),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
@@ -447,11 +446,11 @@ end else begin : sfp_mac
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req('0),
.tx_pfc_req('{1{'0}}),
.tx_pfc_resend('0),
.rx_pfc_en('0),
.rx_pfc_en('{1{'0}}),
.rx_pfc_req(),
.rx_pfc_ack('0),
.rx_pfc_ack('{1{'0}}),
/*
* Pause interface

11
example/Nexus_K3P_Q/fpga/rtl/fpga_core.sv
View File

@@ -224,12 +224,11 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
/*
* PTP clock
*/
.tx_ptp_ts('0),
.tx_ptp_ts('{CNT{'0}}),
.tx_ptp_ts_step('0),
.rx_ptp_ts('0),
.rx_ptp_ts('{CNT{'0}}),
.rx_ptp_ts_step('0),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
@@ -242,11 +241,11 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req('0),
.tx_pfc_req('{CNT{'0}}),
.tx_pfc_resend('0),
.rx_pfc_en('0),
.rx_pfc_en('{CNT{'0}}),
.rx_pfc_req(),
.rx_pfc_ack('0),
.rx_pfc_ack('{CNT{'0}}),
/*
* Pause interface

11
example/Nexus_K3P_S/fpga/rtl/fpga_core.sv
View File

@@ -205,12 +205,11 @@ sfp_mac_inst (
/*
* PTP clock
*/
.tx_ptp_ts('0),
.tx_ptp_ts('{2{'0}}),
.tx_ptp_ts_step('0),
.rx_ptp_ts('0),
.rx_ptp_ts('{2{'0}}),
.rx_ptp_ts_step('0),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
@@ -223,11 +222,11 @@ sfp_mac_inst (
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req('0),
.tx_pfc_req('{2{'0}}),
.tx_pfc_resend('0),
.rx_pfc_en('0),
.rx_pfc_en('{2{'0}}),
.rx_pfc_req(),
.rx_pfc_ack('0),
.rx_pfc_ack('{2{'0}}),
/*
* Pause interface

11
example/VCU108/fpga/rtl/fpga_core.sv
View File

@@ -328,12 +328,11 @@ qsfp_mac_inst (
/*
* PTP clock
*/
.tx_ptp_ts('0),
.tx_ptp_ts('{4{'0}}),
.tx_ptp_ts_step('0),
.rx_ptp_ts('0),
.rx_ptp_ts('{4{'0}}),
.rx_ptp_ts_step('0),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
@@ -346,11 +345,11 @@ qsfp_mac_inst (
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req('0),
.tx_pfc_req('{4{'0}}),
.tx_pfc_resend('0),
.rx_pfc_en('0),
.rx_pfc_en('{4{'0}}),
.rx_pfc_req(),
.rx_pfc_ack('0),
.rx_pfc_ack('{4{'0}}),
/*
* Pause interface

11
example/VCU118/fpga/rtl/fpga_core.sv
View File

@@ -523,12 +523,11 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
/*
* PTP clock
*/
.tx_ptp_ts('0),
.tx_ptp_ts('{CNT{'0}}),
.tx_ptp_ts_step('0),
.rx_ptp_ts('0),
.rx_ptp_ts('{CNT{'0}}),
.rx_ptp_ts_step('0),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
@@ -541,11 +540,11 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req('0),
.tx_pfc_req('{CNT{'0}}),
.tx_pfc_resend('0),
.rx_pfc_en('0),
.rx_pfc_en('{CNT{'0}}),
.rx_pfc_req(),
.rx_pfc_ack('0),
.rx_pfc_ack('{CNT{'0}}),
/*
* Pause interface

11
example/ZCU102/fpga/rtl/fpga_core.sv
View File

@@ -555,12 +555,11 @@ end else begin : sfp_mac
/*
* PTP clock
*/
.tx_ptp_ts('0),
.tx_ptp_ts('{4{'0}}),
.tx_ptp_ts_step('0),
.rx_ptp_ts('0),
.rx_ptp_ts('{4{'0}}),
.rx_ptp_ts_step('0),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
@@ -573,11 +572,11 @@ end else begin : sfp_mac
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req('0),
.tx_pfc_req('{4{'0}}),
.tx_pfc_resend('0),
.rx_pfc_en('0),
.rx_pfc_en('{4{'0}}),
.rx_pfc_req(),
.rx_pfc_ack('0),
.rx_pfc_ack('{4{'0}}),
/*
* Pause interface

11
example/ZCU106/fpga/rtl/fpga_core.sv
View File

@@ -397,12 +397,11 @@ end else begin : sfp_mac
/*
* PTP clock
*/
.tx_ptp_ts('0),
.tx_ptp_ts('{2{'0}}),
.tx_ptp_ts_step('0),
.rx_ptp_ts('0),
.rx_ptp_ts('{2{'0}}),
.rx_ptp_ts_step('0),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
@@ -415,11 +414,11 @@ end else begin : sfp_mac
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req('0),
.tx_pfc_req('{2{'0}}),
.tx_pfc_resend('0),
.rx_pfc_en('0),
.rx_pfc_en('{2{'0}}),
.rx_pfc_req(),
.rx_pfc_ack('0),
.rx_pfc_ack('{2{'0}}),
/*
* Pause interface

11
example/ZCU111/fpga/rtl/fpga_core.sv
View File

@@ -233,12 +233,11 @@ sfp_mac_inst (
/*
* PTP clock
*/
.tx_ptp_ts('0),
.tx_ptp_ts('{4{'0}}),
.tx_ptp_ts_step('0),
.rx_ptp_ts('0),
.rx_ptp_ts('{4{'0}}),
.rx_ptp_ts_step('0),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
@@ -251,11 +250,11 @@ sfp_mac_inst (
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req('0),
.tx_pfc_req('{4{'0}}),
.tx_pfc_resend('0),
.rx_pfc_en('0),
.rx_pfc_en('{4{'0}}),
.rx_pfc_req(),
.rx_pfc_ack('0),
.rx_pfc_ack('{4{'0}}),
/*
* Pause interface

11
example/fb2CG/fpga/rtl/fpga_core.sv
View File

@@ -245,12 +245,11 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
/*
* PTP clock
*/
.tx_ptp_ts('0),
.tx_ptp_ts('{CNT{'0}}),
.tx_ptp_ts_step('0),
.rx_ptp_ts('0),
.rx_ptp_ts('{CNT{'0}}),
.rx_ptp_ts_step('0),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
@@ -263,11 +262,11 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req('0),
.tx_pfc_req('{CNT{'0}}),
.tx_pfc_resend('0),
.rx_pfc_en('0),
.rx_pfc_en('{CNT{'0}}),
.rx_pfc_req(),
.rx_pfc_ack('0),
.rx_pfc_ack('{CNT{'0}}),
/*
* Pause interface

4
rtl/eth/taxi_eth_mac_10g.sv
View File

@@ -142,8 +142,8 @@ module taxi_eth_mac_10g #
input wire logic [15:0] cfg_tx_pfc_eth_type = 16'h8808,
input wire logic [15:0] cfg_tx_pfc_opcode = 16'h0101,
input wire logic cfg_tx_pfc_en = 1'b0,
input wire logic [7:0][15:0] cfg_tx_pfc_quanta = '{8{16'hffff}},
input wire logic [7:0][15:0] cfg_tx_pfc_refresh = '{8{16'h7fff}},
input wire logic [15:0] cfg_tx_pfc_quanta[8] = '{8{16'hffff}},
input wire logic [15:0] cfg_tx_pfc_refresh[8] = '{8{16'h7fff}},
input wire logic [15:0] cfg_rx_lfc_opcode = 16'h0001,
input wire logic cfg_rx_lfc_en = 1'b0,
input wire logic [15:0] cfg_rx_pfc_opcode = 16'h0101,

62
rtl/eth/taxi_eth_mac_10g_fifo.sv
View File

@@ -326,37 +326,37 @@ eth_mac_10g_inst (
.cfg_ifg(cfg_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_enable(cfg_rx_enable),
.cfg_mcf_rx_eth_dst_mcast(0),
.cfg_mcf_rx_check_eth_dst_mcast(0),
.cfg_mcf_rx_eth_dst_ucast(0),
.cfg_mcf_rx_check_eth_dst_ucast(0),
.cfg_mcf_rx_eth_src(0),
.cfg_mcf_rx_check_eth_src(0),
.cfg_mcf_rx_eth_type(0),
.cfg_mcf_rx_opcode_lfc(0),
.cfg_mcf_rx_check_opcode_lfc(0),
.cfg_mcf_rx_opcode_pfc(0),
.cfg_mcf_rx_check_opcode_pfc(0),
.cfg_mcf_rx_forward(0),
.cfg_mcf_rx_enable(0),
.cfg_tx_lfc_eth_dst(0),
.cfg_tx_lfc_eth_src(0),
.cfg_tx_lfc_eth_type(0),
.cfg_tx_lfc_opcode(0),
.cfg_tx_lfc_en(0),
.cfg_tx_lfc_quanta(0),
.cfg_tx_lfc_refresh(0),
.cfg_tx_pfc_eth_dst(0),
.cfg_tx_pfc_eth_src(0),
.cfg_tx_pfc_eth_type(0),
.cfg_tx_pfc_opcode(0),
.cfg_tx_pfc_en(0),
.cfg_tx_pfc_quanta(0),
.cfg_tx_pfc_refresh(0),
.cfg_rx_lfc_opcode(0),
.cfg_rx_lfc_en(0),
.cfg_rx_pfc_opcode(0),
.cfg_rx_pfc_en(0)
.cfg_mcf_rx_eth_dst_mcast('0),
.cfg_mcf_rx_check_eth_dst_mcast('0),
.cfg_mcf_rx_eth_dst_ucast('0),
.cfg_mcf_rx_check_eth_dst_ucast('0),
.cfg_mcf_rx_eth_src('0),
.cfg_mcf_rx_check_eth_src('0),
.cfg_mcf_rx_eth_type('0),
.cfg_mcf_rx_opcode_lfc('0),
.cfg_mcf_rx_check_opcode_lfc('0),
.cfg_mcf_rx_opcode_pfc('0),
.cfg_mcf_rx_check_opcode_pfc('0),
.cfg_mcf_rx_forward('0),
.cfg_mcf_rx_enable('0),
.cfg_tx_lfc_eth_dst('0),
.cfg_tx_lfc_eth_src('0),
.cfg_tx_lfc_eth_type('0),
.cfg_tx_lfc_opcode('0),
.cfg_tx_lfc_en('0),
.cfg_tx_lfc_quanta('0),
.cfg_tx_lfc_refresh('0),
.cfg_tx_pfc_eth_dst('0),
.cfg_tx_pfc_eth_src('0),
.cfg_tx_pfc_eth_type('0),
.cfg_tx_pfc_opcode('0),
.cfg_tx_pfc_en('0),
.cfg_tx_pfc_quanta('{8{'0}}),
.cfg_tx_pfc_refresh('{8{'0}}),
.cfg_rx_lfc_opcode('0),
.cfg_rx_lfc_en('0),
.cfg_rx_pfc_opcode('0),
.cfg_rx_pfc_en('0)
);
taxi_axis_async_fifo_adapter #(

4
rtl/eth/taxi_eth_mac_1g.sv
View File

@@ -149,8 +149,8 @@ module taxi_eth_mac_1g #
input wire logic [15:0] cfg_tx_pfc_eth_type = 16'h8808,
input wire logic [15:0] cfg_tx_pfc_opcode = 16'h0101,
input wire logic cfg_tx_pfc_en = 1'b0,
input wire logic [7:0][15:0] cfg_tx_pfc_quanta = '{8{16'hffff}},
input wire logic [7:0][15:0] cfg_tx_pfc_refresh = '{8{16'h7fff}},
input wire logic [15:0] cfg_tx_pfc_quanta[8] = '{8{16'hffff}},
input wire logic [15:0] cfg_tx_pfc_refresh[8] = '{8{16'h7fff}},
input wire logic [15:0] cfg_rx_lfc_opcode = 16'h0001,
input wire logic cfg_rx_lfc_en = 1'b0,
input wire logic [15:0] cfg_rx_pfc_opcode = 16'h0101,

62
rtl/eth/taxi_eth_mac_1g_fifo.sv
View File

@@ -271,37 +271,37 @@ eth_mac_1g_inst (
.cfg_ifg(cfg_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_enable(cfg_rx_enable),
.cfg_mcf_rx_eth_dst_mcast(0),
.cfg_mcf_rx_check_eth_dst_mcast(0),
.cfg_mcf_rx_eth_dst_ucast(0),
.cfg_mcf_rx_check_eth_dst_ucast(0),
.cfg_mcf_rx_eth_src(0),
.cfg_mcf_rx_check_eth_src(0),
.cfg_mcf_rx_eth_type(0),
.cfg_mcf_rx_opcode_lfc(0),
.cfg_mcf_rx_check_opcode_lfc(0),
.cfg_mcf_rx_opcode_pfc(0),
.cfg_mcf_rx_check_opcode_pfc(0),
.cfg_mcf_rx_forward(0),
.cfg_mcf_rx_enable(0),
.cfg_tx_lfc_eth_dst(0),
.cfg_tx_lfc_eth_src(0),
.cfg_tx_lfc_eth_type(0),
.cfg_tx_lfc_opcode(0),
.cfg_tx_lfc_en(0),
.cfg_tx_lfc_quanta(0),
.cfg_tx_lfc_refresh(0),
.cfg_tx_pfc_eth_dst(0),
.cfg_tx_pfc_eth_src(0),
.cfg_tx_pfc_eth_type(0),
.cfg_tx_pfc_opcode(0),
.cfg_tx_pfc_en(0),
.cfg_tx_pfc_quanta(0),
.cfg_tx_pfc_refresh(0),
.cfg_rx_lfc_opcode(0),
.cfg_rx_lfc_en(0),
.cfg_rx_pfc_opcode(0),
.cfg_rx_pfc_en(0)
.cfg_mcf_rx_eth_dst_mcast('0),
.cfg_mcf_rx_check_eth_dst_mcast('0),
.cfg_mcf_rx_eth_dst_ucast('0),
.cfg_mcf_rx_check_eth_dst_ucast('0),
.cfg_mcf_rx_eth_src('0),
.cfg_mcf_rx_check_eth_src('0),
.cfg_mcf_rx_eth_type('0),
.cfg_mcf_rx_opcode_lfc('0),
.cfg_mcf_rx_check_opcode_lfc('0),
.cfg_mcf_rx_opcode_pfc('0),
.cfg_mcf_rx_check_opcode_pfc('0),
.cfg_mcf_rx_forward('0),
.cfg_mcf_rx_enable('0),
.cfg_tx_lfc_eth_dst('0),
.cfg_tx_lfc_eth_src('0),
.cfg_tx_lfc_eth_type('0),
.cfg_tx_lfc_opcode('0),
.cfg_tx_lfc_en('0),
.cfg_tx_lfc_quanta('0),
.cfg_tx_lfc_refresh('0),
.cfg_tx_pfc_eth_dst('0),
.cfg_tx_pfc_eth_src('0),
.cfg_tx_pfc_eth_type('0),
.cfg_tx_pfc_opcode('0),
.cfg_tx_pfc_en('0),
.cfg_tx_pfc_quanta('{8{'0}}),
.cfg_tx_pfc_refresh('{8{'0}}),
.cfg_rx_lfc_opcode('0),
.cfg_rx_lfc_en('0),
.cfg_rx_pfc_opcode('0),
.cfg_rx_pfc_en('0)
);
taxi_axis_async_fifo_adapter #(

4
rtl/eth/taxi_eth_mac_1g_gmii.sv
View File

@@ -149,8 +149,8 @@ module taxi_eth_mac_1g_gmii #
input wire logic [15:0] cfg_tx_pfc_eth_type = 16'h8808,
input wire logic [15:0] cfg_tx_pfc_opcode = 16'h0101,
input wire logic cfg_tx_pfc_en = 1'b0,
input wire logic [7:0][15:0] cfg_tx_pfc_quanta = '{8{16'hffff}},
input wire logic [7:0][15:0] cfg_tx_pfc_refresh = '{8{16'h7fff}},
input wire logic [15:0] cfg_tx_pfc_quanta[8] = '{8{16'hffff}},
input wire logic [15:0] cfg_tx_pfc_refresh[8] = '{8{16'h7fff}},
input wire logic [15:0] cfg_rx_lfc_opcode = 16'h0001,
input wire logic cfg_rx_lfc_en = 1'b0,
input wire logic [15:0] cfg_rx_pfc_opcode = 16'h0101,

62
rtl/eth/taxi_eth_mac_1g_gmii_fifo.sv
View File

@@ -284,37 +284,37 @@ eth_mac_1g_gmii_inst (
.cfg_ifg(cfg_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_enable(cfg_rx_enable),
.cfg_mcf_rx_eth_dst_mcast(0),
.cfg_mcf_rx_check_eth_dst_mcast(0),
.cfg_mcf_rx_eth_dst_ucast(0),
.cfg_mcf_rx_check_eth_dst_ucast(0),
.cfg_mcf_rx_eth_src(0),
.cfg_mcf_rx_check_eth_src(0),
.cfg_mcf_rx_eth_type(0),
.cfg_mcf_rx_opcode_lfc(0),
.cfg_mcf_rx_check_opcode_lfc(0),
.cfg_mcf_rx_opcode_pfc(0),
.cfg_mcf_rx_check_opcode_pfc(0),
.cfg_mcf_rx_forward(0),
.cfg_mcf_rx_enable(0),
.cfg_tx_lfc_eth_dst(0),
.cfg_tx_lfc_eth_src(0),
.cfg_tx_lfc_eth_type(0),
.cfg_tx_lfc_opcode(0),
.cfg_tx_lfc_en(0),
.cfg_tx_lfc_quanta(0),
.cfg_tx_lfc_refresh(0),
.cfg_tx_pfc_eth_dst(0),
.cfg_tx_pfc_eth_src(0),
.cfg_tx_pfc_eth_type(0),
.cfg_tx_pfc_opcode(0),
.cfg_tx_pfc_en(0),
.cfg_tx_pfc_quanta(0),
.cfg_tx_pfc_refresh(0),
.cfg_rx_lfc_opcode(0),
.cfg_rx_lfc_en(0),
.cfg_rx_pfc_opcode(0),
.cfg_rx_pfc_en(0)
.cfg_mcf_rx_eth_dst_mcast('0),
.cfg_mcf_rx_check_eth_dst_mcast('0),
.cfg_mcf_rx_eth_dst_ucast('0),
.cfg_mcf_rx_check_eth_dst_ucast('0),
.cfg_mcf_rx_eth_src('0),
.cfg_mcf_rx_check_eth_src('0),
.cfg_mcf_rx_eth_type('0),
.cfg_mcf_rx_opcode_lfc('0),
.cfg_mcf_rx_check_opcode_lfc('0),
.cfg_mcf_rx_opcode_pfc('0),
.cfg_mcf_rx_check_opcode_pfc('0),
.cfg_mcf_rx_forward('0),
.cfg_mcf_rx_enable('0),
.cfg_tx_lfc_eth_dst('0),
.cfg_tx_lfc_eth_src('0),
.cfg_tx_lfc_eth_type('0),
.cfg_tx_lfc_opcode('0),
.cfg_tx_lfc_en('0),
.cfg_tx_lfc_quanta('0),
.cfg_tx_lfc_refresh('0),
.cfg_tx_pfc_eth_dst('0),
.cfg_tx_pfc_eth_src('0),
.cfg_tx_pfc_eth_type('0),
.cfg_tx_pfc_opcode('0),
.cfg_tx_pfc_en('0),
.cfg_tx_pfc_quanta('{8{'0}}),
.cfg_tx_pfc_refresh('{8{'0}}),
.cfg_rx_lfc_opcode('0),
.cfg_rx_lfc_en('0),
.cfg_rx_pfc_opcode('0),
.cfg_rx_pfc_en('0)
);
taxi_axis_async_fifo_adapter #(

4
rtl/eth/taxi_eth_mac_1g_rgmii.sv
View File

@@ -148,8 +148,8 @@ module taxi_eth_mac_1g_rgmii #
input wire logic [15:0] cfg_tx_pfc_eth_type = 16'h8808,
input wire logic [15:0] cfg_tx_pfc_opcode = 16'h0101,
input wire logic cfg_tx_pfc_en = 1'b0,
input wire logic [7:0][15:0] cfg_tx_pfc_quanta = '{8{16'hffff}},
input wire logic [7:0][15:0] cfg_tx_pfc_refresh = '{8{16'h7fff}},
input wire logic [15:0] cfg_tx_pfc_quanta[8] = '{8{16'hffff}},
input wire logic [15:0] cfg_tx_pfc_refresh[8] = '{8{16'h7fff}},
input wire logic [15:0] cfg_rx_lfc_opcode = 16'h0001,
input wire logic cfg_rx_lfc_en = 1'b0,
input wire logic [15:0] cfg_rx_pfc_opcode = 16'h0101,

62
rtl/eth/taxi_eth_mac_1g_rgmii_fifo.sv
View File

@@ -282,37 +282,37 @@ eth_mac_1g_rgmii_inst (
.cfg_ifg(cfg_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_enable(cfg_rx_enable),
.cfg_mcf_rx_eth_dst_mcast(0),
.cfg_mcf_rx_check_eth_dst_mcast(0),
.cfg_mcf_rx_eth_dst_ucast(0),
.cfg_mcf_rx_check_eth_dst_ucast(0),
.cfg_mcf_rx_eth_src(0),
.cfg_mcf_rx_check_eth_src(0),
.cfg_mcf_rx_eth_type(0),
.cfg_mcf_rx_opcode_lfc(0),
.cfg_mcf_rx_check_opcode_lfc(0),
.cfg_mcf_rx_opcode_pfc(0),
.cfg_mcf_rx_check_opcode_pfc(0),
.cfg_mcf_rx_forward(0),
.cfg_mcf_rx_enable(0),
.cfg_tx_lfc_eth_dst(0),
.cfg_tx_lfc_eth_src(0),
.cfg_tx_lfc_eth_type(0),
.cfg_tx_lfc_opcode(0),
.cfg_tx_lfc_en(0),
.cfg_tx_lfc_quanta(0),
.cfg_tx_lfc_refresh(0),
.cfg_tx_pfc_eth_dst(0),
.cfg_tx_pfc_eth_src(0),
.cfg_tx_pfc_eth_type(0),
.cfg_tx_pfc_opcode(0),
.cfg_tx_pfc_en(0),
.cfg_tx_pfc_quanta(0),
.cfg_tx_pfc_refresh(0),
.cfg_rx_lfc_opcode(0),
.cfg_rx_lfc_en(0),
.cfg_rx_pfc_opcode(0),
.cfg_rx_pfc_en(0)
.cfg_mcf_rx_eth_dst_mcast('0),
.cfg_mcf_rx_check_eth_dst_mcast('0),
.cfg_mcf_rx_eth_dst_ucast('0),
.cfg_mcf_rx_check_eth_dst_ucast('0),
.cfg_mcf_rx_eth_src('0),
.cfg_mcf_rx_check_eth_src('0),
.cfg_mcf_rx_eth_type('0),
.cfg_mcf_rx_opcode_lfc('0),
.cfg_mcf_rx_check_opcode_lfc('0),
.cfg_mcf_rx_opcode_pfc('0),
.cfg_mcf_rx_check_opcode_pfc('0),
.cfg_mcf_rx_forward('0),
.cfg_mcf_rx_enable('0),
.cfg_tx_lfc_eth_dst('0),
.cfg_tx_lfc_eth_src('0),
.cfg_tx_lfc_eth_type('0),
.cfg_tx_lfc_opcode('0),
.cfg_tx_lfc_en('0),
.cfg_tx_lfc_quanta('0),
.cfg_tx_lfc_refresh('0),
.cfg_tx_pfc_eth_dst('0),
.cfg_tx_pfc_eth_src('0),
.cfg_tx_pfc_eth_type('0),
.cfg_tx_pfc_opcode('0),
.cfg_tx_pfc_en('0),
.cfg_tx_pfc_quanta('{8{'0}}),
.cfg_tx_pfc_refresh('{8{'0}}),
.cfg_rx_lfc_opcode('0),
.cfg_rx_lfc_en('0),
.cfg_rx_pfc_opcode('0),
.cfg_rx_pfc_en('0)
);
taxi_axis_async_fifo_adapter #(

4
rtl/eth/taxi_eth_mac_mii.sv
View File

@@ -146,8 +146,8 @@ module taxi_eth_mac_mii #
input wire logic [15:0] cfg_tx_pfc_eth_type = 16'h8808,
input wire logic [15:0] cfg_tx_pfc_opcode = 16'h0101,
input wire logic cfg_tx_pfc_en = 1'b0,
input wire logic [7:0][15:0] cfg_tx_pfc_quanta = '{8{16'hffff}},
input wire logic [7:0][15:0] cfg_tx_pfc_refresh = '{8{16'h7fff}},
input wire logic [15:0] cfg_tx_pfc_quanta[8] = '{8{16'hffff}},
input wire logic [15:0] cfg_tx_pfc_refresh[8] = '{8{16'h7fff}},
input wire logic [15:0] cfg_rx_lfc_opcode = 16'h0001,
input wire logic cfg_rx_lfc_en = 1'b0,
input wire logic [15:0] cfg_rx_pfc_opcode = 16'h0101,

62
rtl/eth/taxi_eth_mac_mii_fifo.sv
View File

@@ -266,37 +266,37 @@ eth_mac_mii_inst (
.cfg_ifg(cfg_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_enable(cfg_rx_enable),
.cfg_mcf_rx_eth_dst_mcast(0),
.cfg_mcf_rx_check_eth_dst_mcast(0),
.cfg_mcf_rx_eth_dst_ucast(0),
.cfg_mcf_rx_check_eth_dst_ucast(0),
.cfg_mcf_rx_eth_src(0),
.cfg_mcf_rx_check_eth_src(0),
.cfg_mcf_rx_eth_type(0),
.cfg_mcf_rx_opcode_lfc(0),
.cfg_mcf_rx_check_opcode_lfc(0),
.cfg_mcf_rx_opcode_pfc(0),
.cfg_mcf_rx_check_opcode_pfc(0),
.cfg_mcf_rx_forward(0),
.cfg_mcf_rx_enable(0),
.cfg_tx_lfc_eth_dst(0),
.cfg_tx_lfc_eth_src(0),
.cfg_tx_lfc_eth_type(0),
.cfg_tx_lfc_opcode(0),
.cfg_tx_lfc_en(0),
.cfg_tx_lfc_quanta(0),
.cfg_tx_lfc_refresh(0),
.cfg_tx_pfc_eth_dst(0),
.cfg_tx_pfc_eth_src(0),
.cfg_tx_pfc_eth_type(0),
.cfg_tx_pfc_opcode(0),
.cfg_tx_pfc_en(0),
.cfg_tx_pfc_quanta(0),
.cfg_tx_pfc_refresh(0),
.cfg_rx_lfc_opcode(0),
.cfg_rx_lfc_en(0),
.cfg_rx_pfc_opcode(0),
.cfg_rx_pfc_en(0)
.cfg_mcf_rx_eth_dst_mcast('0),
.cfg_mcf_rx_check_eth_dst_mcast('0),
.cfg_mcf_rx_eth_dst_ucast('0),
.cfg_mcf_rx_check_eth_dst_ucast('0),
.cfg_mcf_rx_eth_src('0),
.cfg_mcf_rx_check_eth_src('0),
.cfg_mcf_rx_eth_type('0),
.cfg_mcf_rx_opcode_lfc('0),
.cfg_mcf_rx_check_opcode_lfc('0),
.cfg_mcf_rx_opcode_pfc('0),
.cfg_mcf_rx_check_opcode_pfc('0),
.cfg_mcf_rx_forward('0),
.cfg_mcf_rx_enable('0),
.cfg_tx_lfc_eth_dst('0),
.cfg_tx_lfc_eth_src('0),
.cfg_tx_lfc_eth_type('0),
.cfg_tx_lfc_opcode('0),
.cfg_tx_lfc_en('0),
.cfg_tx_lfc_quanta('0),
.cfg_tx_lfc_refresh('0),
.cfg_tx_pfc_eth_dst('0),
.cfg_tx_pfc_eth_src('0),
.cfg_tx_pfc_eth_type('0),
.cfg_tx_pfc_opcode('0),
.cfg_tx_pfc_en('0),
.cfg_tx_pfc_quanta('{8{'0}}),
.cfg_tx_pfc_refresh('{8{'0}}),
.cfg_rx_lfc_opcode('0),
.cfg_rx_lfc_en('0),
.cfg_rx_pfc_opcode('0),
.cfg_rx_pfc_en('0)
);
taxi_axis_async_fifo_adapter #(

4
rtl/eth/taxi_eth_mac_phy_10g.sv
View File

@@ -160,8 +160,8 @@ module taxi_eth_mac_phy_10g #
input wire logic [15:0] cfg_tx_pfc_eth_type = 16'h8808,
input wire logic [15:0] cfg_tx_pfc_opcode = 16'h0101,
input wire logic cfg_tx_pfc_en = 1'b0,
input wire logic [7:0][15:0] cfg_tx_pfc_quanta = '{8{16'hffff}},
input wire logic [7:0][15:0] cfg_tx_pfc_refresh = '{8{16'h7fff}},
input wire logic [15:0] cfg_tx_pfc_quanta[8] = '{8{16'hffff}},
input wire logic [15:0] cfg_tx_pfc_refresh[8] = '{8{16'h7fff}},
input wire logic [15:0] cfg_rx_lfc_opcode = 16'h0001,
input wire logic cfg_rx_lfc_en = 1'b0,
input wire logic [15:0] cfg_rx_pfc_opcode = 16'h0101,

62
rtl/eth/taxi_eth_mac_phy_10g_fifo.sv
View File

@@ -371,37 +371,37 @@ eth_mac_phy_10g_inst (
.cfg_rx_enable(cfg_rx_enable),
.cfg_tx_prbs31_enable(cfg_tx_prbs31_enable),
.cfg_rx_prbs31_enable(cfg_rx_prbs31_enable),
.cfg_mcf_rx_eth_dst_mcast(0),
.cfg_mcf_rx_check_eth_dst_mcast(0),
.cfg_mcf_rx_eth_dst_ucast(0),
.cfg_mcf_rx_check_eth_dst_ucast(0),
.cfg_mcf_rx_eth_src(0),
.cfg_mcf_rx_check_eth_src(0),
.cfg_mcf_rx_eth_type(0),
.cfg_mcf_rx_opcode_lfc(0),
.cfg_mcf_rx_check_opcode_lfc(0),
.cfg_mcf_rx_opcode_pfc(0),
.cfg_mcf_rx_check_opcode_pfc(0),
.cfg_mcf_rx_forward(0),
.cfg_mcf_rx_enable(0),
.cfg_tx_lfc_eth_dst(0),
.cfg_tx_lfc_eth_src(0),
.cfg_tx_lfc_eth_type(0),
.cfg_tx_lfc_opcode(0),
.cfg_tx_lfc_en(0),
.cfg_tx_lfc_quanta(0),
.cfg_tx_lfc_refresh(0),
.cfg_tx_pfc_eth_dst(0),
.cfg_tx_pfc_eth_src(0),
.cfg_tx_pfc_eth_type(0),
.cfg_tx_pfc_opcode(0),
.cfg_tx_pfc_en(0),
.cfg_tx_pfc_quanta(0),
.cfg_tx_pfc_refresh(0),
.cfg_rx_lfc_opcode(0),
.cfg_rx_lfc_en(0),
.cfg_rx_pfc_opcode(0),
.cfg_rx_pfc_en(0)
.cfg_mcf_rx_eth_dst_mcast('0),
.cfg_mcf_rx_check_eth_dst_mcast('0),
.cfg_mcf_rx_eth_dst_ucast('0),
.cfg_mcf_rx_check_eth_dst_ucast('0),
.cfg_mcf_rx_eth_src('0),
.cfg_mcf_rx_check_eth_src('0),
.cfg_mcf_rx_eth_type('0),
.cfg_mcf_rx_opcode_lfc('0),
.cfg_mcf_rx_check_opcode_lfc('0),
.cfg_mcf_rx_opcode_pfc('0),
.cfg_mcf_rx_check_opcode_pfc('0),
.cfg_mcf_rx_forward('0),
.cfg_mcf_rx_enable('0),
.cfg_tx_lfc_eth_dst('0),
.cfg_tx_lfc_eth_src('0),
.cfg_tx_lfc_eth_type('0),
.cfg_tx_lfc_opcode('0),
.cfg_tx_lfc_en('0),
.cfg_tx_lfc_quanta('0),
.cfg_tx_lfc_refresh('0),
.cfg_tx_pfc_eth_dst('0),
.cfg_tx_pfc_eth_src('0),
.cfg_tx_pfc_eth_type('0),
.cfg_tx_pfc_opcode('0),
.cfg_tx_pfc_en('0),
.cfg_tx_pfc_quanta('{8{'0}}),
.cfg_tx_pfc_refresh('{8{'0}}),
.cfg_rx_lfc_opcode('0),
.cfg_rx_lfc_en('0),
.cfg_rx_pfc_opcode('0),
.cfg_rx_pfc_en('0)
);
taxi_axis_async_fifo_adapter #(

4
rtl/eth/taxi_mac_pause_ctrl_tx.sv
View File

@@ -62,8 +62,8 @@ module taxi_mac_pause_ctrl_tx #
input wire logic [15:0] cfg_tx_pfc_eth_type = 16'h8808,
input wire logic [15:0] cfg_tx_pfc_opcode = 16'h0101,
input wire logic cfg_tx_pfc_en = 1'b0,
input wire logic [7:0][15:0] cfg_tx_pfc_quanta = '{8{16'hffff}},
input wire logic [7:0][15:0] cfg_tx_pfc_refresh = '{8{16'h7fff}},
input wire logic [15:0] cfg_tx_pfc_quanta[8] = '{8{16'hffff}},
input wire logic [15:0] cfg_tx_pfc_refresh[8] = '{8{16'h7fff}},
input wire logic [9:0] cfg_quanta_step,
input wire logic cfg_quanta_clk_en = 1'b1,

206
rtl/eth/us/taxi_eth_mac_25g_us.sv
View File

@@ -45,153 +45,153 @@ module taxi_eth_mac_25g_us #
parameter COUNT_125US = 125000/6.4
)
(
input wire logic xcvr_ctrl_clk,
input wire logic xcvr_ctrl_rst,
input wire logic xcvr_ctrl_clk,
input wire logic xcvr_ctrl_rst,
/*
* Common
*/
output wire logic xcvr_gtpowergood_out,
input wire logic xcvr_gtrefclk00_in,
output wire logic xcvr_qpll0lock_out,
output wire logic xcvr_qpll0clk_out,
output wire logic xcvr_qpll0refclk_out,
output wire logic xcvr_gtpowergood_out,
input wire logic xcvr_gtrefclk00_in,
output wire logic xcvr_qpll0lock_out,
output wire logic xcvr_qpll0clk_out,
output wire logic xcvr_qpll0refclk_out,
/*
* Serial data
*/
output wire logic [CNT-1:0] xcvr_txp,
output wire logic [CNT-1:0] xcvr_txn,
input wire logic [CNT-1:0] xcvr_rxp,
input wire logic [CNT-1:0] xcvr_rxn,
output wire logic [CNT-1:0] xcvr_txp,
output wire logic [CNT-1:0] xcvr_txn,
input wire logic [CNT-1:0] xcvr_rxp,
input wire logic [CNT-1:0] xcvr_rxn,
/*
* MAC clocks
*/
output wire logic [CNT-1:0] rx_clk,
input wire logic [CNT-1:0] rx_rst_in,
output wire logic [CNT-1:0] rx_rst_out,
output wire logic [CNT-1:0] tx_clk,
input wire logic [CNT-1:0] tx_rst_in,
output wire logic [CNT-1:0] tx_rst_out,
input wire logic [CNT-1:0] ptp_sample_clk,
output wire logic [CNT-1:0] rx_clk,
input wire logic [CNT-1:0] rx_rst_in,
output wire logic [CNT-1:0] rx_rst_out,
output wire logic [CNT-1:0] tx_clk,
input wire logic [CNT-1:0] tx_rst_in,
output wire logic [CNT-1:0] tx_rst_out,
input wire logic [CNT-1:0] ptp_sample_clk,
/*
* Transmit interface (AXI stream)
*/
taxi_axis_if.snk s_axis_tx[CNT-1:0],
taxi_axis_if.src m_axis_tx_cpl[CNT-1:0],
taxi_axis_if.snk s_axis_tx[CNT],
taxi_axis_if.src m_axis_tx_cpl[CNT],
/*
* Receive interface (AXI stream)
*/
taxi_axis_if.src m_axis_rx[CNT-1:0],
taxi_axis_if.src m_axis_rx[CNT],
/*
* PTP clock
*/
input wire logic [CNT-1:0][PTP_TS_W-1:0] tx_ptp_ts = '0,
input wire logic [CNT-1:0] tx_ptp_ts_step = '0,
input wire logic [CNT-1:0][PTP_TS_W-1:0] rx_ptp_ts = '0,
input wire logic [CNT-1:0] rx_ptp_ts_step = '0,
input wire logic [PTP_TS_W-1:0] tx_ptp_ts[CNT] = '{CNT{'0}},
input wire logic [CNT-1:0] tx_ptp_ts_step = '0,
input wire logic [PTP_TS_W-1:0] rx_ptp_ts[CNT] = '{CNT{'0}},
input wire logic [CNT-1:0] rx_ptp_ts_step = '0,
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
input wire logic [CNT-1:0] tx_lfc_req = '0,
input wire logic [CNT-1:0] tx_lfc_resend = '0,
input wire logic [CNT-1:0] rx_lfc_en = '0,
output wire logic [CNT-1:0] rx_lfc_req,
input wire logic [CNT-1:0] rx_lfc_ack = '0,
input wire logic [CNT-1:0] tx_lfc_req = '0,
input wire logic [CNT-1:0] tx_lfc_resend = '0,
input wire logic [CNT-1:0] rx_lfc_en = '0,
output wire logic [CNT-1:0] rx_lfc_req,
input wire logic [CNT-1:0] rx_lfc_ack = '0,
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
input wire logic [CNT-1:0][7:0] tx_pfc_req = '0,
input wire logic [CNT-1:0] tx_pfc_resend = '0,
input wire logic [CNT-1:0][7:0] rx_pfc_en = '0,
output wire logic [CNT-1:0][7:0] rx_pfc_req,
input wire logic [CNT-1:0][7:0] rx_pfc_ack = '0,
input wire logic [7:0] tx_pfc_req[CNT] = '{CNT{'0}},
input wire logic [CNT-1:0] tx_pfc_resend = '0,
input wire logic [7:0] rx_pfc_en[CNT] = '{CNT{'0}},
output wire logic [7:0] rx_pfc_req[CNT],
input wire logic [7:0] rx_pfc_ack[CNT] = '{CNT{'0}},
/*
* Pause interface
*/
input wire logic [CNT-1:0] tx_lfc_pause_en = '0,
input wire logic [CNT-1:0] tx_pause_req = '0,
output wire logic [CNT-1:0] tx_pause_ack,
input wire logic [CNT-1:0] tx_lfc_pause_en = '0,
input wire logic [CNT-1:0] tx_pause_req = '0,
output wire logic [CNT-1:0] tx_pause_ack,
/*
* Status
*/
output wire logic [CNT-1:0][1:0] tx_start_packet,
output wire logic [CNT-1:0] tx_error_underflow,
output wire logic [CNT-1:0][1:0] rx_start_packet,
output wire logic [CNT-1:0][6:0] rx_error_count,
output wire logic [CNT-1:0] rx_error_bad_frame,
output wire logic [CNT-1:0] rx_error_bad_fcs,
output wire logic [CNT-1:0] rx_bad_block,
output wire logic [CNT-1:0] rx_sequence_error,
output wire logic [CNT-1:0] rx_block_lock,
output wire logic [CNT-1:0] rx_high_ber,
output wire logic [CNT-1:0] rx_status,
output wire logic [CNT-1:0] stat_tx_mcf,
output wire logic [CNT-1:0] stat_rx_mcf,
output wire logic [CNT-1:0] stat_tx_lfc_pkt,
output wire logic [CNT-1:0] stat_tx_lfc_xon,
output wire logic [CNT-1:0] stat_tx_lfc_xoff,
output wire logic [CNT-1:0] stat_tx_lfc_paused,
output wire logic [CNT-1:0] stat_tx_pfc_pkt,
output wire logic [CNT-1:0][7:0] stat_tx_pfc_xon,
output wire logic [CNT-1:0][7:0] stat_tx_pfc_xoff,
output wire logic [CNT-1:0][7:0] stat_tx_pfc_paused,
output wire logic [CNT-1:0] stat_rx_lfc_pkt,
output wire logic [CNT-1:0] stat_rx_lfc_xon,
output wire logic [CNT-1:0] stat_rx_lfc_xoff,
output wire logic [CNT-1:0] stat_rx_lfc_paused,
output wire logic [CNT-1:0] stat_rx_pfc_pkt,
output wire logic [CNT-1:0][7:0] stat_rx_pfc_xon,
output wire logic [CNT-1:0][7:0] stat_rx_pfc_xoff,
output wire logic [CNT-1:0][7:0] stat_rx_pfc_paused,
output wire logic [1:0] tx_start_packet[CNT],
output wire logic [CNT-1:0] tx_error_underflow,
output wire logic [1:0] rx_start_packet[CNT],
output wire logic [6:0] rx_error_count[CNT],
output wire logic [CNT-1:0] rx_error_bad_frame,
output wire logic [CNT-1:0] rx_error_bad_fcs,
output wire logic [CNT-1:0] rx_bad_block,
output wire logic [CNT-1:0] rx_sequence_error,
output wire logic [CNT-1:0] rx_block_lock,
output wire logic [CNT-1:0] rx_high_ber,
output wire logic [CNT-1:0] rx_status,
output wire logic [CNT-1:0] stat_tx_mcf,
output wire logic [CNT-1:0] stat_rx_mcf,
output wire logic [CNT-1:0] stat_tx_lfc_pkt,
output wire logic [CNT-1:0] stat_tx_lfc_xon,
output wire logic [CNT-1:0] stat_tx_lfc_xoff,
output wire logic [CNT-1:0] stat_tx_lfc_paused,
output wire logic [CNT-1:0] stat_tx_pfc_pkt,
output wire logic [7:0] stat_tx_pfc_xon[CNT],
output wire logic [7:0] stat_tx_pfc_xoff[CNT],
output wire logic [7:0] stat_tx_pfc_paused[CNT],
output wire logic [CNT-1:0] stat_rx_lfc_pkt,
output wire logic [CNT-1:0] stat_rx_lfc_xon,
output wire logic [CNT-1:0] stat_rx_lfc_xoff,
output wire logic [CNT-1:0] stat_rx_lfc_paused,
output wire logic [CNT-1:0] stat_rx_pfc_pkt,
output wire logic [7:0] stat_rx_pfc_xon[CNT],
output wire logic [7:0] stat_rx_pfc_xoff[CNT],
output wire logic [7:0] stat_rx_pfc_paused[CNT],
/*
* Configuration
*/
input wire logic [CNT-1:0][7:0] cfg_ifg = '{CNT{8'd12}},
input wire logic [CNT-1:0] cfg_tx_enable = '1,
input wire logic [CNT-1:0] cfg_rx_enable = '1,
input wire logic [CNT-1:0] cfg_tx_prbs31_enable = '0,
input wire logic [CNT-1:0] cfg_rx_prbs31_enable = '0,
input wire logic [CNT-1:0][47:0] cfg_mcf_rx_eth_dst_mcast = '{CNT{48'h01_80_C2_00_00_01}},
input wire logic [CNT-1:0] cfg_mcf_rx_check_eth_dst_mcast = '1,
input wire logic [CNT-1:0][47:0] cfg_mcf_rx_eth_dst_ucast = '{CNT{48'd0}},
input wire logic [CNT-1:0] cfg_mcf_rx_check_eth_dst_ucast = '0,
input wire logic [CNT-1:0][47:0] cfg_mcf_rx_eth_src = '{CNT{48'd0}},
input wire logic [CNT-1:0] cfg_mcf_rx_check_eth_src = '0,
input wire logic [CNT-1:0][15:0] cfg_mcf_rx_eth_type = '{CNT{16'h8808}},
input wire logic [CNT-1:0][15:0] cfg_mcf_rx_opcode_lfc = '{CNT{16'h0001}},
input wire logic [CNT-1:0] cfg_mcf_rx_check_opcode_lfc = '1,
input wire logic [CNT-1:0][15:0] cfg_mcf_rx_opcode_pfc = '{CNT{16'h0101}},
input wire logic [CNT-1:0] cfg_mcf_rx_check_opcode_pfc = '1,
input wire logic [CNT-1:0] cfg_mcf_rx_forward = '0,
input wire logic [CNT-1:0] cfg_mcf_rx_enable = '0,
input wire logic [CNT-1:0][47:0] cfg_tx_lfc_eth_dst = '{CNT{48'h01_80_C2_00_00_01}},
input wire logic [CNT-1:0][47:0] cfg_tx_lfc_eth_src = '{CNT{48'h80_23_31_43_54_4C}},
input wire logic [CNT-1:0][15:0] cfg_tx_lfc_eth_type = '{CNT{16'h8808}},
input wire logic [CNT-1:0][15:0] cfg_tx_lfc_opcode = '{CNT{16'h0001}},
input wire logic [CNT-1:0] cfg_tx_lfc_en = '0,
input wire logic [CNT-1:0][15:0] cfg_tx_lfc_quanta = '{CNT{16'hffff}},
input wire logic [CNT-1:0][15:0] cfg_tx_lfc_refresh = '{CNT{16'h7fff}},
input wire logic [CNT-1:0][47:0] cfg_tx_pfc_eth_dst = '{CNT{48'h01_80_C2_00_00_01}},
input wire logic [CNT-1:0][47:0] cfg_tx_pfc_eth_src = '{CNT{48'h80_23_31_43_54_4C}},
input wire logic [CNT-1:0][15:0] cfg_tx_pfc_eth_type = '{CNT{16'h8808}},
input wire logic [CNT-1:0][15:0] cfg_tx_pfc_opcode = '{CNT{16'h0101}},
input wire logic [CNT-1:0] cfg_tx_pfc_en = '0,
input wire logic [CNT-1:0][7:0][15:0] cfg_tx_pfc_quanta = '{CNT{'{8{16'hffff}}}},
input wire logic [CNT-1:0][7:0][15:0] cfg_tx_pfc_refresh = '{CNT{'{8{16'h7fff}}}},
input wire logic [CNT-1:0][15:0] cfg_rx_lfc_opcode = '{CNT{16'h0001}},
input wire logic [CNT-1:0] cfg_rx_lfc_en = '0,
input wire logic [CNT-1:0][15:0] cfg_rx_pfc_opcode = '{CNT{16'h0101}},
input wire logic [CNT-1:0] cfg_rx_pfc_en = '0
input wire logic [7:0] cfg_ifg[CNT] = '{CNT{8'd12}},
input wire logic [CNT-1:0] cfg_tx_enable = '1,
input wire logic [CNT-1:0] cfg_rx_enable = '1,
input wire logic [CNT-1:0] cfg_tx_prbs31_enable = '0,
input wire logic [CNT-1:0] cfg_rx_prbs31_enable = '0,
input wire logic [47:0] cfg_mcf_rx_eth_dst_mcast[CNT] = '{CNT{48'h01_80_C2_00_00_01}},
input wire logic [CNT-1:0] cfg_mcf_rx_check_eth_dst_mcast = '1,
input wire logic [47:0] cfg_mcf_rx_eth_dst_ucast[CNT] = '{CNT{48'd0}},
input wire logic [CNT-1:0] cfg_mcf_rx_check_eth_dst_ucast = '0,
input wire logic [47:0] cfg_mcf_rx_eth_src[CNT] = '{CNT{48'd0}},
input wire logic [CNT-1:0] cfg_mcf_rx_check_eth_src = '0,
input wire logic [15:0] cfg_mcf_rx_eth_type[CNT] = '{CNT{16'h8808}},
input wire logic [15:0] cfg_mcf_rx_opcode_lfc[CNT] = '{CNT{16'h0001}},
input wire logic [CNT-1:0] cfg_mcf_rx_check_opcode_lfc = '1,
input wire logic [15:0] cfg_mcf_rx_opcode_pfc[CNT] = '{CNT{16'h0101}},
input wire logic [CNT-1:0] cfg_mcf_rx_check_opcode_pfc = '1,
input wire logic [CNT-1:0] cfg_mcf_rx_forward = '0,
input wire logic [CNT-1:0] cfg_mcf_rx_enable = '0,
input wire logic [47:0] cfg_tx_lfc_eth_dst[CNT] = '{CNT{48'h01_80_C2_00_00_01}},
input wire logic [47:0] cfg_tx_lfc_eth_src[CNT] = '{CNT{48'h80_23_31_43_54_4C}},
input wire logic [15:0] cfg_tx_lfc_eth_type[CNT] = '{CNT{16'h8808}},
input wire logic [15:0] cfg_tx_lfc_opcode[CNT] = '{CNT{16'h0001}},
input wire logic [CNT-1:0] cfg_tx_lfc_en = '0,
input wire logic [15:0] cfg_tx_lfc_quanta[CNT] = '{CNT{16'hffff}},
input wire logic [15:0] cfg_tx_lfc_refresh[CNT] = '{CNT{16'h7fff}},
input wire logic [47:0] cfg_tx_pfc_eth_dst[CNT] = '{CNT{48'h01_80_C2_00_00_01}},
input wire logic [47:0] cfg_tx_pfc_eth_src[CNT] = '{CNT{48'h80_23_31_43_54_4C}},
input wire logic [15:0] cfg_tx_pfc_eth_type[CNT] = '{CNT{16'h8808}},
input wire logic [15:0] cfg_tx_pfc_opcode[CNT] = '{CNT{16'h0101}},
input wire logic [CNT-1:0] cfg_tx_pfc_en = '0,
input wire logic [15:0] cfg_tx_pfc_quanta[CNT][8] = '{CNT{'{8{16'hffff}}}},
input wire logic [15:0] cfg_tx_pfc_refresh[CNT][8] = '{CNT{'{8{16'h7fff}}}},
input wire logic [15:0] cfg_rx_lfc_opcode[CNT] = '{CNT{16'h0001}},
input wire logic [CNT-1:0] cfg_rx_lfc_en = '0,
input wire logic [15:0] cfg_rx_pfc_opcode[CNT] = '{CNT{16'h0101}},
input wire logic [CNT-1:0] cfg_rx_pfc_en = '0
);
for (genvar n = 0; n < CNT; n = n + 1) begin : ch

4
rtl/eth/us/taxi_eth_mac_25g_us_ch.sv
View File

@@ -198,8 +198,8 @@ module taxi_eth_mac_25g_us_ch #
input wire logic [15:0] cfg_tx_pfc_eth_type = 16'h8808,
input wire logic [15:0] cfg_tx_pfc_opcode = 16'h0101,
input wire logic cfg_tx_pfc_en = 1'b0,
input wire logic [7:0][15:0] cfg_tx_pfc_quanta = '{8{16'hffff}},
input wire logic [7:0][15:0] cfg_tx_pfc_refresh = '{8{16'h7fff}},
input wire logic [15:0] cfg_tx_pfc_quanta[8] = '{8{16'hffff}},
input wire logic [15:0] cfg_tx_pfc_refresh[8] = '{8{16'h7fff}},
input wire logic [15:0] cfg_rx_lfc_opcode = 16'h0001,
input wire logic cfg_rx_lfc_en = 1'b0,
input wire logic [15:0] cfg_rx_pfc_opcode = 16'h0101,

8
tb/eth/taxi_eth_mac_10g/test_taxi_eth_mac_10g.py
View File

@@ -95,8 +95,8 @@ class TB:
dut.cfg_tx_pfc_eth_type.setimmediatevalue(0)
dut.cfg_tx_pfc_opcode.setimmediatevalue(0)
dut.cfg_tx_pfc_en.setimmediatevalue(0)
dut.cfg_tx_pfc_quanta.setimmediatevalue(0)
dut.cfg_tx_pfc_refresh.setimmediatevalue(0)
dut.cfg_tx_pfc_quanta.setimmediatevalue([0]*8)
dut.cfg_tx_pfc_refresh.setimmediatevalue([0]*8)
dut.cfg_rx_lfc_opcode.setimmediatevalue(0)
dut.cfg_rx_lfc_en.setimmediatevalue(0)
dut.cfg_rx_pfc_opcode.setimmediatevalue(0)
@@ -554,8 +554,8 @@ async def run_test_pfc(dut, ifg=12):
dut.cfg_tx_pfc_eth_type.value = 0x8808
dut.cfg_tx_pfc_opcode.value = 0x0101
dut.cfg_tx_pfc_en.value = 1
dut.cfg_tx_pfc_quanta.value = 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
dut.cfg_tx_pfc_refresh.value = 0x7F007F007F007F007F007F007F007F00
dut.cfg_tx_pfc_quanta.value = [0xFFFF]*8
dut.cfg_tx_pfc_refresh.value = [0x7F00]*8
dut.cfg_rx_pfc_opcode.value = 0x0101
dut.cfg_rx_pfc_en.value = 1

4
tb/eth/taxi_eth_mac_10g/test_taxi_eth_mac_10g.sv
View File

@@ -121,8 +121,8 @@ logic [47:0] cfg_tx_pfc_eth_src;
logic [15:0] cfg_tx_pfc_eth_type;
logic [15:0] cfg_tx_pfc_opcode;
logic cfg_tx_pfc_en;
logic [7:0][15:0] cfg_tx_pfc_quanta;
logic [7:0][15:0] cfg_tx_pfc_refresh;
logic [15:0] cfg_tx_pfc_quanta[8];
logic [15:0] cfg_tx_pfc_refresh[8];
logic [15:0] cfg_rx_lfc_opcode;
logic cfg_rx_lfc_en;
logic [15:0] cfg_rx_pfc_opcode;

8
tb/eth/taxi_eth_mac_1g/test_taxi_eth_mac_1g.py
View File

@@ -102,8 +102,8 @@ class TB:
dut.cfg_tx_pfc_eth_type.setimmediatevalue(0)
dut.cfg_tx_pfc_opcode.setimmediatevalue(0)
dut.cfg_tx_pfc_en.setimmediatevalue(0)
dut.cfg_tx_pfc_quanta.setimmediatevalue(0)
dut.cfg_tx_pfc_refresh.setimmediatevalue(0)
dut.cfg_tx_pfc_quanta.setimmediatevalue([0]*8)
dut.cfg_tx_pfc_refresh.setimmediatevalue([0]*8)
dut.cfg_rx_lfc_opcode.setimmediatevalue(0)
dut.cfg_rx_lfc_en.setimmediatevalue(0)
dut.cfg_rx_pfc_opcode.setimmediatevalue(0)
@@ -541,8 +541,8 @@ async def run_test_pfc(dut, ifg=12, enable_gen=None, mii_sel=True):
dut.cfg_tx_pfc_eth_type.value = 0x8808
dut.cfg_tx_pfc_opcode.value = 0x0101
dut.cfg_tx_pfc_en.value = 1
dut.cfg_tx_pfc_quanta.value = 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
dut.cfg_tx_pfc_refresh.value = 0x7F007F007F007F007F007F007F007F00
dut.cfg_tx_pfc_quanta.value = [0xFFFF]*8
dut.cfg_tx_pfc_refresh.value = [0x7F00]*8
dut.cfg_rx_pfc_opcode.value = 0x0101
dut.cfg_rx_pfc_en.value = 1

4
tb/eth/taxi_eth_mac_1g/test_taxi_eth_mac_1g.sv
View File

@@ -125,8 +125,8 @@ logic [47:0] cfg_tx_pfc_eth_src;
logic [15:0] cfg_tx_pfc_eth_type;
logic [15:0] cfg_tx_pfc_opcode;
logic cfg_tx_pfc_en;
logic [7:0][15:0] cfg_tx_pfc_quanta;
logic [7:0][15:0] cfg_tx_pfc_refresh;
logic [15:0] cfg_tx_pfc_quanta[8];
logic [15:0] cfg_tx_pfc_refresh[8];
logic [15:0] cfg_rx_lfc_opcode;
logic cfg_rx_lfc_en;
logic [15:0] cfg_rx_pfc_opcode;

8
tb/eth/taxi_eth_mac_1g_gmii/test_taxi_eth_mac_1g_gmii.py
View File

@@ -94,8 +94,8 @@ class TB:
dut.cfg_tx_pfc_eth_type.setimmediatevalue(0)
dut.cfg_tx_pfc_opcode.setimmediatevalue(0)
dut.cfg_tx_pfc_en.setimmediatevalue(0)
dut.cfg_tx_pfc_quanta.setimmediatevalue(0)
dut.cfg_tx_pfc_refresh.setimmediatevalue(0)
dut.cfg_tx_pfc_quanta.setimmediatevalue([0]*8)
dut.cfg_tx_pfc_refresh.setimmediatevalue([0]*8)
dut.cfg_rx_lfc_opcode.setimmediatevalue(0)
dut.cfg_rx_lfc_en.setimmediatevalue(0)
dut.cfg_rx_pfc_opcode.setimmediatevalue(0)
@@ -494,8 +494,8 @@ async def run_test_pfc(dut, ifg=12, speed=1000e6):
dut.cfg_tx_pfc_eth_type.value = 0x8808
dut.cfg_tx_pfc_opcode.value = 0x0101
dut.cfg_tx_pfc_en.value = 1
dut.cfg_tx_pfc_quanta.value = 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
dut.cfg_tx_pfc_refresh.value = 0x7F007F007F007F007F007F007F007F00
dut.cfg_tx_pfc_quanta.value = [0xFFFF]*8
dut.cfg_tx_pfc_refresh.value = [0x7F00]*8
dut.cfg_rx_pfc_opcode.value = 0x0101
dut.cfg_rx_pfc_en.value = 1

4
tb/eth/taxi_eth_mac_1g_gmii/test_taxi_eth_mac_1g_gmii.sv
View File

@@ -129,8 +129,8 @@ logic [47:0] cfg_tx_pfc_eth_src;
logic [15:0] cfg_tx_pfc_eth_type;
logic [15:0] cfg_tx_pfc_opcode;
logic cfg_tx_pfc_en;
logic [7:0][15:0] cfg_tx_pfc_quanta;
logic [7:0][15:0] cfg_tx_pfc_refresh;
logic [15:0] cfg_tx_pfc_quanta[8];
logic [15:0] cfg_tx_pfc_refresh[8];
logic [15:0] cfg_rx_lfc_opcode;
logic cfg_rx_lfc_en;
logic [15:0] cfg_rx_pfc_opcode;

8
tb/eth/taxi_eth_mac_1g_rgmii/test_taxi_eth_mac_1g_rgmii.py
View File

@@ -87,8 +87,8 @@ class TB:
dut.cfg_tx_pfc_eth_type.setimmediatevalue(0)
dut.cfg_tx_pfc_opcode.setimmediatevalue(0)
dut.cfg_tx_pfc_en.setimmediatevalue(0)
dut.cfg_tx_pfc_quanta.setimmediatevalue(0)
dut.cfg_tx_pfc_refresh.setimmediatevalue(0)
dut.cfg_tx_pfc_quanta.setimmediatevalue([0]*8)
dut.cfg_tx_pfc_refresh.setimmediatevalue([0]*8)
dut.cfg_rx_lfc_opcode.setimmediatevalue(0)
dut.cfg_rx_lfc_en.setimmediatevalue(0)
dut.cfg_rx_pfc_opcode.setimmediatevalue(0)
@@ -495,8 +495,8 @@ async def run_test_pfc(dut, ifg=12, speed=1000e6):
dut.cfg_tx_pfc_eth_type.value = 0x8808
dut.cfg_tx_pfc_opcode.value = 0x0101
dut.cfg_tx_pfc_en.value = 1
dut.cfg_tx_pfc_quanta.value = 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
dut.cfg_tx_pfc_refresh.value = 0x7F007F007F007F007F007F007F007F00
dut.cfg_tx_pfc_quanta.value = [0xFFFF]*8
dut.cfg_tx_pfc_refresh.value = [0x7F00]*8
dut.cfg_rx_pfc_opcode.value = 0x0101
dut.cfg_rx_pfc_en.value = 1

4
tb/eth/taxi_eth_mac_1g_rgmii/test_taxi_eth_mac_1g_rgmii.sv
View File

@@ -128,8 +128,8 @@ logic [47:0] cfg_tx_pfc_eth_src;
logic [15:0] cfg_tx_pfc_eth_type;
logic [15:0] cfg_tx_pfc_opcode;
logic cfg_tx_pfc_en;
logic [7:0][15:0] cfg_tx_pfc_quanta;
logic [7:0][15:0] cfg_tx_pfc_refresh;
logic [15:0] cfg_tx_pfc_quanta[8];
logic [15:0] cfg_tx_pfc_refresh[8];
logic [15:0] cfg_rx_lfc_opcode;
logic cfg_rx_lfc_en;
logic [15:0] cfg_rx_pfc_opcode;

8
tb/eth/taxi_eth_mac_mii/test_taxi_eth_mac_mii.py
View File

@@ -87,8 +87,8 @@ class TB:
dut.cfg_tx_pfc_eth_type.setimmediatevalue(0)
dut.cfg_tx_pfc_opcode.setimmediatevalue(0)
dut.cfg_tx_pfc_en.setimmediatevalue(0)
dut.cfg_tx_pfc_quanta.setimmediatevalue(0)
dut.cfg_tx_pfc_refresh.setimmediatevalue(0)
dut.cfg_tx_pfc_quanta.setimmediatevalue([0]*8)
dut.cfg_tx_pfc_refresh.setimmediatevalue([0]*8)
dut.cfg_rx_lfc_opcode.setimmediatevalue(0)
dut.cfg_rx_lfc_en.setimmediatevalue(0)
dut.cfg_rx_pfc_opcode.setimmediatevalue(0)
@@ -456,8 +456,8 @@ async def run_test_pfc(dut, ifg=12, speed=1000e6):
dut.cfg_tx_pfc_eth_type.value = 0x8808
dut.cfg_tx_pfc_opcode.value = 0x0101
dut.cfg_tx_pfc_en.value = 1
dut.cfg_tx_pfc_quanta.value = 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
dut.cfg_tx_pfc_refresh.value = 0x7F007F007F007F007F007F007F007F00
dut.cfg_tx_pfc_quanta.value = [0xFFFF]*8
dut.cfg_tx_pfc_refresh.value = [0x7F00]*8
dut.cfg_rx_pfc_opcode.value = 0x0101
dut.cfg_rx_pfc_en.value = 1

4
tb/eth/taxi_eth_mac_mii/test_taxi_eth_mac_mii.sv
View File

@@ -126,8 +126,8 @@ logic [47:0] cfg_tx_pfc_eth_src;
logic [15:0] cfg_tx_pfc_eth_type;
logic [15:0] cfg_tx_pfc_opcode;
logic cfg_tx_pfc_en;
logic [7:0][15:0] cfg_tx_pfc_quanta;
logic [7:0][15:0] cfg_tx_pfc_refresh;
logic [15:0] cfg_tx_pfc_quanta[8];
logic [15:0] cfg_tx_pfc_refresh[8];
logic [15:0] cfg_rx_lfc_opcode;
logic cfg_rx_lfc_en;
logic [15:0] cfg_rx_pfc_opcode;

8
tb/eth/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.py
View File

@@ -95,8 +95,8 @@ class TB:
dut.cfg_tx_pfc_eth_type.setimmediatevalue(0)
dut.cfg_tx_pfc_opcode.setimmediatevalue(0)
dut.cfg_tx_pfc_en.setimmediatevalue(0)
dut.cfg_tx_pfc_quanta.setimmediatevalue(0)
dut.cfg_tx_pfc_refresh.setimmediatevalue(0)
dut.cfg_tx_pfc_quanta.setimmediatevalue([0]*8)
dut.cfg_tx_pfc_refresh.setimmediatevalue([0]*8)
dut.cfg_rx_lfc_opcode.setimmediatevalue(0)
dut.cfg_rx_lfc_en.setimmediatevalue(0)
dut.cfg_rx_pfc_opcode.setimmediatevalue(0)
@@ -614,8 +614,8 @@ async def run_test_pfc(dut, ifg=12):
dut.cfg_tx_pfc_eth_type.value = 0x8808
dut.cfg_tx_pfc_opcode.value = 0x0101
dut.cfg_tx_pfc_en.value = 1
dut.cfg_tx_pfc_quanta.value = 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
dut.cfg_tx_pfc_refresh.value = 0x7F007F007F007F007F007F007F007F00
dut.cfg_tx_pfc_quanta.value = [0xFFFF]*8
dut.cfg_tx_pfc_refresh.value = [0x7F00]*8
dut.cfg_rx_pfc_opcode.value = 0x0101
dut.cfg_rx_pfc_en.value = 1

4
tb/eth/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.sv
View File

@@ -139,8 +139,8 @@ logic [47:0] cfg_tx_pfc_eth_src;
logic [15:0] cfg_tx_pfc_eth_type;
logic [15:0] cfg_tx_pfc_opcode;
logic cfg_tx_pfc_en;
logic [7:0][15:0] cfg_tx_pfc_quanta;
logic [7:0][15:0] cfg_tx_pfc_refresh;
logic [15:0] cfg_tx_pfc_quanta[8];
logic [15:0] cfg_tx_pfc_refresh[8];
logic [15:0] cfg_rx_lfc_opcode;
logic cfg_rx_lfc_en;
logic [15:0] cfg_rx_pfc_opcode;

34
tb/eth/taxi_mac_pause_ctrl_tx/test_taxi_mac_pause_ctrl_tx.py
View File

@@ -61,8 +61,8 @@ class TB:
dut.cfg_tx_pfc_eth_type.setimmediatevalue(0)
dut.cfg_tx_pfc_opcode.setimmediatevalue(0)
dut.cfg_tx_pfc_en.setimmediatevalue(0)
dut.cfg_tx_pfc_quanta.setimmediatevalue(0)
dut.cfg_tx_pfc_refresh.setimmediatevalue(0)
dut.cfg_tx_pfc_quanta.setimmediatevalue([0]*8)
dut.cfg_tx_pfc_refresh.setimmediatevalue([0]*8)
dut.cfg_quanta_step.setimmediatevalue(256)
dut.cfg_quanta_clk_en.setimmediatevalue(1)
@@ -113,9 +113,6 @@ async def run_test_lfc(dut):
dut.tx_lfc_req.value = 0
dut.tx_lfc_resend.value = 0
dut.tx_pfc_req.value = 0x00
dut.tx_pfc_resend.value = 0
dut.cfg_tx_lfc_eth_dst.value = 0x0180C2000001
dut.cfg_tx_lfc_eth_src.value = 0x5A5152535455
dut.cfg_tx_lfc_eth_type.value = 0x8808
@@ -123,13 +120,6 @@ async def run_test_lfc(dut):
dut.cfg_tx_lfc_en.value = 1
dut.cfg_tx_lfc_quanta.value = 0xFFFF
dut.cfg_tx_lfc_refresh.value = 0x7F00
dut.cfg_tx_pfc_eth_dst.value = 0x0180C2000001
dut.cfg_tx_pfc_eth_src.value = 0x5A5152535455
dut.cfg_tx_pfc_eth_type.value = 0x8808
dut.cfg_tx_pfc_opcode.value = 0x0101
dut.cfg_tx_pfc_en.value = 0
dut.cfg_tx_pfc_quanta.value = 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
dut.cfg_tx_pfc_refresh.value = 0x7F007F007F007F007F007F007F007F00
dut.cfg_quanta_step.value = int(10000*256 / (512*156.25))
dut.cfg_quanta_clk_en.value = 1
@@ -193,32 +183,22 @@ async def run_test_pfc(dut):
await tb.reset()
dut.tx_lfc_req.value = 0
dut.tx_lfc_resend.value = 0
dut.tx_pfc_req.value = 0x00
dut.tx_pfc_resend.value = 0
dut.cfg_tx_lfc_eth_dst.value = 0x0180C2000001
dut.cfg_tx_lfc_eth_src.value = 0x5A5152535455
dut.cfg_tx_lfc_eth_type.value = 0x8808
dut.cfg_tx_lfc_opcode.value = 0x0001
dut.cfg_tx_lfc_en.value = 0
dut.cfg_tx_lfc_quanta.value = 0xFFFF
dut.cfg_tx_lfc_refresh.value = 0x7F00
dut.cfg_tx_pfc_eth_dst.value = 0x0180C2000001
dut.cfg_tx_pfc_eth_src.value = 0x5A5152535455
dut.cfg_tx_pfc_eth_type.value = 0x8808
dut.cfg_tx_pfc_opcode.value = 0x0101
dut.cfg_tx_pfc_en.value = 1
dut.cfg_tx_pfc_quanta.value = 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
dut.cfg_tx_pfc_refresh.value = 0x7F007F007F007F007F007F007F007F00
dut.cfg_tx_pfc_quanta.value = [0xFFFF]*8
dut.cfg_tx_pfc_refresh.value = [0x7F00]*8
dut.cfg_quanta_step.value = int(10000*256 / (512*156.25))
dut.cfg_quanta_clk_en.value = 1
tb.log.info("Test pause")
dut.cfg_tx_pfc_refresh.value = 0x00640064006400640064006400640064
dut.cfg_tx_pfc_refresh.value = [0x0064]*8
dut.tx_pfc_req.value = 0x01
start_time = None
@@ -248,7 +228,7 @@ async def run_test_pfc(dut):
tb.log.info("Test all channels")
dut.cfg_tx_pfc_refresh.value = 0x00640064006400640064006400640064
dut.cfg_tx_pfc_refresh.value = [0x0064]*8
for ch in range(8):
@@ -280,7 +260,7 @@ async def run_test_pfc(dut):
tb.log.info("Test isolation")
dut.cfg_tx_pfc_refresh.value = 0x00640064006400640064006400640064
dut.cfg_tx_pfc_refresh.value = [0x0064]*8
dut.tx_pfc_req.value = 0x01
start_time = None