xfcp: Add XFCP AXI lite module and testbench

Signed-off-by: Alex Forencich <alex@alexforencich.com>

tb/xfcp/taxi_xfcp_mod_axil/Makefile

@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+DUT      = taxi_xfcp_mod_axil
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += ../../../rtl/xfcp/$(DUT).sv
+VERILOG_SOURCES += ../../../rtl/axi/taxi_axil_if.sv
+VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_COUNT_SIZE := 16
+export PARAM_AXIL_DATA_W := 32
+export PARAM_AXIL_ADDR_W := 32
+export PARAM_AXIL_STRB_W := $(shell expr $(PARAM_AXIL_DATA_W) / 8 )
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

tb/xfcp/taxi_xfcp_mod_axil/test_taxi_xfcp_mod_axil.py

@@ -0,0 +1,260 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import struct
+import sys
+
+import cocotb_test.simulator
+import pytest
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.regression import TestFactory
+
+from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink
+from cocotbext.axi import AxiLiteBus, AxiLiteRam
+
+try:
+    from xfcp import XfcpFrame
+except ImportError:
+    # attempt import from current directory
+    sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
+    try:
+        from xfcp import XfcpFrame
+    finally:
+        del sys.path[0]
+
+
+class TB(object):
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 8, units="ns").start())
+
+        self.axis_source = AxiStreamSource(AxiStreamBus.from_entity(dut.up_xfcp_in), dut.clk, dut.rst)
+        self.axis_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.up_xfcp_out), dut.clk, dut.rst)
+
+        self.axil_ram = AxiLiteRam(AxiLiteBus.from_entity(dut.m_axil), dut.clk, dut.rst, size=2**16)
+
+    def set_idle_generator(self, generator=None):
+        if generator:
+            self.axis_source.set_pause_generator(generator())
+            self.axil_ram.write_if.b_channel.set_pause_generator(generator())
+            self.axil_ram.read_if.r_channel.set_pause_generator(generator())
+
+    def set_backpressure_generator(self, generator=None):
+        if generator:
+            self.axis_sink.set_pause_generator(generator())
+            self.axil_ram.write_if.aw_channel.set_pause_generator(generator())
+            self.axil_ram.write_if.w_channel.set_pause_generator(generator())
+            self.axil_ram.read_if.ar_channel.set_pause_generator(generator())
+
+    async def reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+
+async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
+
+    tb = TB(dut)
+
+    byte_lanes = tb.axil_ram.write_if.byte_lanes
+
+    await tb.reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    for length in range(1, byte_lanes*4):
+        for offset in range(byte_lanes):
+            tb.log.info("length %d, offset %d", length, offset)
+            addr = offset+0x1000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            tb.axil_ram.write(addr-128, b'\xaa'*(length+256))
+
+            pkt = XfcpFrame()
+            pkt.ptype = 0x12
+            pkt.payload = bytearray(struct.pack('<IH', addr, length)+test_data)
+
+            tb.log.debug("TX packet: %s", pkt)
+
+            await tb.axis_source.send(pkt.build())
+
+            rx_frame = await tb.axis_sink.recv()
+            rx_pkt = XfcpFrame.parse(rx_frame.tdata)
+
+            tb.log.debug("RX packet: %s", rx_pkt)
+
+            for k in range(100):
+                await RisingEdge(dut.clk)
+
+            tb.log.debug("%s", tb.axil_ram.hexdump_str((addr & ~0xf)-16, (((addr & 0xf)+length-1) & ~0xf)+48))
+
+            assert tb.axil_ram.read(addr, length) == test_data
+            assert tb.axil_ram.read(addr-1, 1) == b'\xaa'
+            assert tb.axil_ram.read(addr+length, 1) == b'\xaa'
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
+
+    tb = TB(dut)
+
+    byte_lanes = tb.axil_ram.write_if.byte_lanes
+
+    await tb.reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    for length in range(1, byte_lanes*4):
+        for offset in range(byte_lanes):
+            tb.log.info("length %d, offset %d", length, offset)
+            addr = offset+0x1000
+            test_data = bytearray([x % 256 for x in range(length)])
+
+            tb.axil_ram.write(addr, test_data)
+
+            pkt = XfcpFrame()
+            pkt.ptype = 0x10
+            pkt.payload = bytearray(struct.pack('<IH', addr, length))
+
+            tb.log.debug("TX packet: %s", pkt)
+
+            await tb.axis_source.send(pkt.build())
+
+            rx_frame = await tb.axis_sink.recv()
+            rx_pkt = XfcpFrame.parse(rx_frame.tdata)
+
+            tb.log.debug("RX packet: %s", rx_pkt)
+
+            assert rx_pkt.payload[6:] == test_data
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_test_id(dut, idle_inserter=None, backpressure_inserter=None):
+
+    tb = TB(dut)
+
+    await tb.reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    pkt = XfcpFrame()
+    pkt.ptype = 0xFE
+    pkt.payload = b''
+
+    tb.log.debug("TX packet: %s", pkt)
+
+    await tb.axis_source.send(pkt.build())
+
+    rx_frame = await tb.axis_sink.recv()
+    rx_pkt = XfcpFrame.parse(rx_frame.tdata)
+
+    tb.log.debug("RX packet: %s", rx_pkt)
+
+    assert len(rx_pkt.payload) == 32
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+def cycle_pause():
+    return itertools.cycle([1, 1, 1, 0])
+
+
+if cocotb.SIM_NAME:
+
+    for test in [run_test_write, run_test_read, run_test_id]:
+
+        factory = TestFactory(test)
+        factory.add_option("idle_inserter", [None, cycle_pause])
+        factory.add_option("backpressure_inserter", [None, cycle_pause])
+        factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.dirname(__file__)
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+@pytest.mark.parametrize("data_w", [8, 16, 32])
+def test_taxi_xfcp_mod_axil(request, data_w):
+
+    dut = "taxi_xfcp_mod_axil"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, "xfcp", f"{dut}.sv"),
+        os.path.join(rtl_dir, "axi", "taxi_axil_if.sv"),
+        os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['COUNT_SIZE'] = 16
+    parameters['AXIL_DATA_W'] = data_w
+    parameters['AXIL_ADDR_W'] = 32
+    parameters['AXIL_STRB_W'] = parameters['AXIL_DATA_W'] // 8
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

tb/xfcp/taxi_xfcp_mod_axil/test_taxi_xfcp_mod_axil.sv

@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * XFCP AXI lite module testbench
+ */
+module test_taxi_xfcp_mod_axil #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter COUNT_SIZE = 16,
+    parameter AXIL_DATA_W = 32,
+    parameter AXIL_ADDR_W = 32,
+    parameter AXIL_STRB_W = (AXIL_DATA_W/8)
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+logic clk;
+logic rst;
+
+taxi_axis_if #(.DATA_W(8), .LAST_EN(1), .USER_EN(1), .USER_W(1)) up_xfcp_in(), up_xfcp_out();
+
+taxi_axil_if #(
+    .DATA_W(AXIL_DATA_W),
+    .ADDR_W(AXIL_ADDR_W),
+    .STRB_W(AXIL_STRB_W)
+) m_axil();
+
+taxi_xfcp_mod_axil #(
+    .COUNT_SIZE(COUNT_SIZE)
+)
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * XFCP upstream port
+     */
+    .up_xfcp_in(up_xfcp_in),
+    .up_xfcp_out(up_xfcp_out),
+
+    /*
+     * AXI lite master interface
+     */
+    .m_axil_wr(m_axil),
+    .m_axil_rd(m_axil)
+);
+
+endmodule
+
+`resetall

tb/xfcp/taxi_xfcp_mod_axil/xfcp.py

@@ -0,0 +1,159 @@
+# SPDX-License-Identifier: MIT
+"""
+
+Copyright (c) 2017-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import struct
+
+
+def cobs_encode(block):
+    block = bytes(block)
+    enc = bytearray()
+
+    seg = bytearray()
+    code = 1
+
+    new_data = True
+
+    for b in block:
+        if b == 0:
+            enc.append(code)
+            enc.extend(seg)
+            code = 1
+            seg = bytearray()
+            new_data = True
+        else:
+            code += 1
+            seg.append(b)
+            new_data = True
+            if code == 255:
+                enc.append(code)
+                enc.extend(seg)
+                code = 1
+                seg = bytearray()
+                new_data = False
+
+    if new_data:
+        enc.append(code)
+        enc.extend(seg)
+
+    return bytes(enc)
+
+
+def cobs_decode(block):
+    block = bytes(block)
+    dec = bytearray()
+
+    code = 0
+
+    i = 0
+
+    if 0 in block:
+        return None
+
+    while i < len(block):
+        code = block[i]
+        i += 1
+        if i+code-1 > len(block):
+            return None
+        dec.extend(block[i:i+code-1])
+        i += code-1
+        if code < 255 and i < len(block):
+            dec.append(0)
+
+    return bytes(dec)
+
+
+class XfcpFrame(object):
+    def __init__(self, payload=b'', path=[], rpath=[], ptype=0):
+        self._payload = b''
+        self.path = path
+        self.rpath = rpath
+        self.ptype = ptype
+
+        if type(payload) is bytes:
+            self.payload = payload
+        if type(payload) is XfcpFrame:
+            self.payload = payload.payload
+            self.path = list(payload.path)
+            self.rpath = list(payload.rpath)
+            self.ptype = payload.ptype
+
+    @property
+    def payload(self):
+        return self._payload
+
+    @payload.setter
+    def payload(self, value):
+        self._payload = bytes(value)
+
+    def build(self):
+        data = bytearray()
+
+        for p in self.path:
+            data.extend(struct.pack('B', p))
+
+        if self.rpath:
+            data.extend(struct.pack('B', 0xFE))
+            for p in self.rpath:
+                data.extend(struct.pack('B', p))
+
+        data.extend(struct.pack('B', 0xFF))
+
+        data.extend(struct.pack('B', self.ptype))
+
+        data.extend(self.payload)
+
+        return data
+
+    def build_cobs(self):
+        return cobs_encode(self.build())+b'\x00'
+
+    @classmethod
+    def parse(cls, data):
+        data = bytes(data)
+
+        i = 0
+
+        path = []
+        rpath = []
+
+        while i < len(data) and data[i] < 0xFE:
+            path.append(data[i])
+            i += 1
+
+        if data[i] == 0xFE:
+            i += 1
+            while i < len(data) and data[i] < 0xFE:
+                rpath.append(data[i])
+                i += 1
+
+        assert data[i] == 0xFF
+        i += 1
+
+        ptype = data[i]
+        i += 1
+
+        payload = data[i:]
+
+        return cls(payload, path, rpath, ptype)
+
+    @classmethod
+    def parse_cobs(cls, data):
+        return cls.parse(cobs_decode(bytes(data)))
+
+    def __eq__(self, other):
+        if type(other) is XfcpFrame:
+            return (self.path == other.path and
+                self.rpath == other.rpath and
+                self.ptype == other.ptype and
+                self.payload == other.payload)
+        return False
+
+    def __repr__(self):
+        return f"XfcpFrame(payload={self.payload!r}, path={self.path!r}, rpath={self.rpath!r}, ptype={self.ptype})"