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Update readme

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-02-22 23:36:13 -08:00
parent b6be624bdb
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example/VCU108/fpga/README.md
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@@ -11,7 +11,7 @@ The design places looped-back MACs on the BASE-T and QSFP28 ports as well as a l
* RJ-45 Ethernet port with Marvell 88E1111 PHY
* Looped-back MAC via SGMII via Xilinx PCS/PMA core and LVDS IOSERDES
* QSFP28
* Looped-back 10G or 25G MACs via GTY transceivers
* Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers
## Board details