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Update readme

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-02-22 23:36:13 -08:00
parent b6be624bdb
commit 75a746333e
2 changed files with 7 additions and 6 deletions
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11
README.md
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@@ -44,14 +44,15 @@ To facilitate the dual-license model, contributions to the project can only be a
* 10/100/1000 RGMII MAC + FIFO * 10/100/1000 RGMII MAC + FIFO
* 1G MAC * 1G MAC
* 1G MAC + FIFO * 1G MAC + FIFO
* 10G MAC * 10G/25G MAC
* 10G MAC + FIFO * 10G/25G MAC + FIFO
* 10G MAC/PHY * 10G/25G MAC/PHY
* 10G MAC/PHY + FIFO * 10G/25G MAC/PHY + FIFO
* 10G PHY * 10G/25G PHY
* MII PHY interface * MII PHY interface
* GMII PHY interface * GMII PHY interface
* RGMII PHY interface * RGMII PHY interface
* 10G/25G MAC/PHY/GT wrapper for UltraScale/UltraScale+
* General input/output * General input/output
* Switch debouncer * Switch debouncer
* Generic IDDR * Generic IDDR

2
example/VCU108/fpga/README.md
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@@ -11,7 +11,7 @@ The design places looped-back MACs on the BASE-T and QSFP28 ports as well as a l
* RJ-45 Ethernet port with Marvell 88E1111 PHY * RJ-45 Ethernet port with Marvell 88E1111 PHY
* Looped-back MAC via SGMII via Xilinx PCS/PMA core and LVDS IOSERDES * Looped-back MAC via SGMII via Xilinx PCS/PMA core and LVDS IOSERDES
* QSFP28 * QSFP28
* Looped-back 10G or 25G MACs via GTY transceivers * Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers
## Board details ## Board details