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eth: Support ordered sets in AXI stream-BASE-R encode/decode logic

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-06-19 22:58:27 -07:00
parent 67078fd39e
commit 771e4de9eb
14 changed files with 357 additions and 3 deletions
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47
src/eth/rtl/taxi_axis_baser_rx_32.sv
View File

@@ -40,6 +40,13 @@ module taxi_axis_baser_rx_32 #
*/
taxi_axis_if.src m_axis_rx,
/*
* Ordered sets
*/
output wire logic [23:0] rx_os = '0,
output wire logic rx_os_sig = 1'b0,
output wire logic rx_os_valid = 1'b0,
/*
* PTP
*/
@@ -189,6 +196,12 @@ logic m_axis_rx_tvalid_reg = 1'b0, m_axis_rx_tvalid_next;
logic m_axis_rx_tlast_reg = 1'b0, m_axis_rx_tlast_next;
logic m_axis_rx_tuser_reg = 1'b0, m_axis_rx_tuser_next;
logic [23:0] rx_os_reg = '0;
logic rx_os_0_reg = 1'b0;
logic rx_os_4_reg = 1'b0;
logic rx_os_sig_reg = 1'b0;
logic rx_os_valid_reg = 1'b0;
logic start_packet_reg = 1'b0, start_packet_next;
logic frame_reg = 1'b0;
@@ -234,6 +247,10 @@ if (PTP_TS_EN) begin
assign m_axis_rx.tuser[1 +: PTP_TS_W] = ptp_ts_out_reg;
end
assign rx_os = rx_os_reg;
assign rx_os_sig = rx_os_sig_reg;
assign rx_os_valid = rx_os_valid_reg;
assign rx_start_packet = start_packet_reg;
assign stat_rx_byte = stat_rx_byte_reg;
@@ -557,6 +574,8 @@ always_ff @(posedge clk) begin
m_axis_rx_tlast_reg <= m_axis_rx_tlast_next;
m_axis_rx_tuser_reg <= m_axis_rx_tuser_next;
rx_os_valid_reg <= 1'b0;
ptp_ts_out_reg <= ptp_ts_out_next;
start_packet_reg <= start_packet_next;
@@ -583,6 +602,9 @@ always_ff @(posedge clk) begin
encoded_rx_hdr_reg <= encoded_rx_hdr;
encoded_rx_hdr_valid_reg <= encoded_rx_hdr_valid;
rx_os_0_reg <= 1'b0;
rx_os_4_reg <= 1'b0;
term_present_alt_reg <= 1'b0;
term_present_reg <= term_present_alt_reg;
term_first_cycle_alt_reg <= 1'b0;
@@ -618,6 +640,7 @@ always_ff @(posedge clk) begin
input_data_d0_reg <= encoded_rx_data_reg;
framing_error_reg <= frame_reg;
frame_reg <= 1'b0;
rx_os_4_reg <= 1'b1;
end
BLOCK_TYPE_START_4[7:4]: begin
input_data_d0_reg <= encoded_rx_data_reg;
@@ -630,11 +653,16 @@ always_ff @(posedge clk) begin
input_start_alt_reg <= 1'b1;
framing_error_reg <= frame_reg;
frame_reg <= 1'b1;
rx_os_0_reg <= 1'b1;
rx_os_reg[7:0] <= encoded_rx_data_reg[31:24];
rx_os_reg[15:8] <= encoded_rx_data_reg[23:16];
rx_os_reg[23:16] <= encoded_rx_data_reg[15:8];
end
BLOCK_TYPE_OS_04[7:4]: begin
input_data_d0_reg <= encoded_rx_data_reg;
framing_error_reg <= frame_reg;
frame_reg <= 1'b0;
rx_os_4_reg <= 1'b1;
end
BLOCK_TYPE_START_0[7:4]: begin
input_data_d0_reg <= encoded_rx_data_reg;
@@ -646,6 +674,10 @@ always_ff @(posedge clk) begin
input_data_d0_reg <= encoded_rx_data_reg;
framing_error_reg <= frame_reg;
frame_reg <= 1'b0;
rx_os_0_reg <= 1'b1;
rx_os_reg[7:0] <= encoded_rx_data_reg[31:24];
rx_os_reg[15:8] <= encoded_rx_data_reg[23:16];
rx_os_reg[23:16] <= encoded_rx_data_reg[15:8];
end
BLOCK_TYPE_TERM_0[7:4]: begin
input_data_d0_reg <= encoded_rx_data_reg; // don't care
@@ -754,6 +786,17 @@ always_ff @(posedge clk) begin
default: input_data_d0_reg <= encoded_rx_data_reg;
endcase
end
if (rx_os_0_reg) begin
rx_os_sig_reg <= encoded_rx_data_reg[3:0] == O_SIG_OS;
rx_os_valid_reg <= encoded_rx_data_reg[3:0] == O_SEQ_OS || encoded_rx_data_reg[3:0] == O_SIG_OS;
end else if (rx_os_4_reg) begin
rx_os_reg[7:0] <= encoded_rx_data_reg[31:24];
rx_os_reg[15:8] <= encoded_rx_data_reg[23:16];
rx_os_reg[23:16] <= encoded_rx_data_reg[15:8];
rx_os_sig_reg <= encoded_rx_data_reg[7:4] == O_SIG_OS;
rx_os_valid_reg <= encoded_rx_data_reg[7:4] == O_SEQ_OS || encoded_rx_data_reg[7:4] == O_SIG_OS;
end
end
if (reset_crc) begin
@@ -770,6 +813,10 @@ always_ff @(posedge clk) begin
m_axis_rx_tvalid_reg <= 1'b0;
rx_os_0_reg <= 1'b0;
rx_os_4_reg <= 1'b0;
rx_os_valid_reg <= 1'b0;
start_packet_reg <= 1'b0;
frame_reg <= 1'b0;

38
src/eth/rtl/taxi_axis_baser_rx_64.sv
View File

@@ -41,6 +41,13 @@ module taxi_axis_baser_rx_64 #
*/
taxi_axis_if.src m_axis_rx,
/*
* Ordered sets
*/
output wire logic [23:0] rx_os = '0,
output wire logic rx_os_sig = 1'b0,
output wire logic rx_os_valid = 1'b0,
/*
* PTP
*/
@@ -183,6 +190,10 @@ logic m_axis_rx_tvalid_reg = 1'b0, m_axis_rx_tvalid_next;
logic m_axis_rx_tlast_reg = 1'b0, m_axis_rx_tlast_next;
logic m_axis_rx_tuser_reg = 1'b0, m_axis_rx_tuser_next;
logic [23:0] rx_os_reg = '0;
logic rx_os_sig_reg = 1'b0;
logic rx_os_valid_reg = 1'b0;
logic [1:0] start_packet_reg = 2'b00;
logic frame_reg = 1'b0;
@@ -238,6 +249,10 @@ if (PTP_TS_EN) begin
assign m_axis_rx.tuser[1 +: PTP_TS_W] = ptp_ts_out_reg;
end
assign rx_os = rx_os_reg;
assign rx_os_sig = rx_os_sig_reg;
assign rx_os_valid = rx_os_valid_reg;
assign rx_start_packet = start_packet_reg;
assign stat_rx_byte = stat_rx_byte_reg;
@@ -561,6 +576,8 @@ always_ff @(posedge clk) begin
m_axis_rx_tlast_reg <= m_axis_rx_tlast_next;
m_axis_rx_tuser_reg <= m_axis_rx_tuser_next;
rx_os_valid_reg <= 1'b0;
ptp_ts_out_reg <= ptp_ts_out_next;
start_packet_reg <= 2'b00;
@@ -719,6 +736,25 @@ always_ff @(posedge clk) begin
crc_state_reg <= ~32'h6dd90a9d;
end
// ordered sets
if (encoded_rx_data[7:4] == BLOCK_TYPE_OS_4[7:4] || encoded_rx_data[7:4] == BLOCK_TYPE_OS_04[7:4]) begin
rx_os_reg[7:0] <= encoded_rx_data[63:56];
rx_os_reg[15:8] <= encoded_rx_data[55:48];
rx_os_reg[23:16] <= encoded_rx_data[47:40];
rx_os_sig_reg <= encoded_rx_data[39:36] == O_SIG_OS;
if ((encoded_rx_data[7:0] == BLOCK_TYPE_OS_4 || encoded_rx_data[7:0] == BLOCK_TYPE_OS_04) || (encoded_rx_data[39:36] == O_SEQ_OS || encoded_rx_data[39:36] == O_SIG_OS)) begin
rx_os_valid_reg <= 1'b1;
end
end else if (encoded_rx_data[7:4] == BLOCK_TYPE_OS_0[7:4] || encoded_rx_data[7:4] == BLOCK_TYPE_OS_START[7:4]) begin
rx_os_reg[7:0] <= encoded_rx_data[31:24];
rx_os_reg[15:8] <= encoded_rx_data[23:16];
rx_os_reg[23:16] <= encoded_rx_data[15:8];
rx_os_sig_reg <= encoded_rx_data[35:32] == O_SIG_OS;
if ((encoded_rx_data[7:0] == BLOCK_TYPE_OS_0 || encoded_rx_data[7:0] == BLOCK_TYPE_OS_START) || (encoded_rx_data[35:32] == O_SEQ_OS || encoded_rx_data[35:32] == O_SIG_OS)) begin
rx_os_valid_reg <= 1'b1;
end
end
// check for framing errors
framing_error_reg <= 1'b0;
framing_error_d0_reg <= framing_error_reg;
@@ -854,6 +890,8 @@ always_ff @(posedge clk) begin
m_axis_rx_tvalid_reg <= 1'b0;
rx_os_valid_reg <= 1'b0;
start_packet_reg <= 2'b00;
frame_reg <= 1'b0;

34
src/eth/rtl/taxi_axis_baser_tx_32.sv
View File

@@ -47,6 +47,14 @@ module taxi_axis_baser_tx_32 #
input wire logic tx_gbx_req_stall = '0,
output wire logic [GBX_CNT-1:0] tx_gbx_sync,
/*
* Ordered sets
*/
input wire logic [23:0] tx_os = '0,
input wire logic tx_os_sig = 1'b0,
input wire logic tx_os_valid = 1'b0,
output wire logic tx_os_ready,
/*
* PTP
*/
@@ -199,6 +207,8 @@ logic [PTP_TS_W-1:0] m_axis_tx_cpl_ts_reg = '0, m_axis_tx_cpl_ts_next;
logic [TX_TAG_W-1:0] m_axis_tx_cpl_tag_reg = '0, m_axis_tx_cpl_tag_next;
logic m_axis_tx_cpl_valid_reg = 1'b0, m_axis_tx_cpl_valid_next;
logic tx_os_ready_reg = 1'b0;
logic [DATA_W-1:0] encoded_tx_data_reg = {24'd0, BLOCK_TYPE_CTRL};
logic encoded_tx_data_valid_reg = 1'b0;
logic [HDR_W-1:0] encoded_tx_hdr_reg = SYNC_CTRL;
@@ -679,6 +689,8 @@ always_ff @(posedge clk) begin
m_axis_tx_cpl_tag_reg <= m_axis_tx_cpl_tag_next;
m_axis_tx_cpl_valid_reg <= m_axis_tx_cpl_valid_next;
tx_os_ready_reg <= 1'b0;
start_packet_reg <= start_packet_next;
stat_tx_byte_reg <= stat_tx_byte_next;
@@ -705,7 +717,14 @@ always_ff @(posedge clk) begin
if (phase_reg == 0) begin
case ({output_type_reg, output_type_next})
{OUTPUT_TYPE_IDLE, OUTPUT_TYPE_IDLE}: begin
encoded_tx_data_reg <= {24'd0, BLOCK_TYPE_CTRL};
if (tx_os_valid) begin
encoded_tx_data_reg[7:0] <= BLOCK_TYPE_OS_04;
encoded_tx_data_reg[15:8] <= tx_os[23:16];
encoded_tx_data_reg[23:16] <= tx_os[15:8];
encoded_tx_data_reg[31:24] <= tx_os[7:0];
end else begin
encoded_tx_data_reg <= {24'd0, BLOCK_TYPE_CTRL};
end
encoded_tx_hdr_reg <= SYNC_CTRL;
end
{OUTPUT_TYPE_ERROR, OUTPUT_TYPE_ERROR}: begin
@@ -764,7 +783,16 @@ always_ff @(posedge clk) begin
end else begin
case (output_type_reg)
OUTPUT_TYPE_IDLE: begin
encoded_tx_data_reg <= 32'd0;
if (tx_os_valid) begin
encoded_tx_data_reg[3:0] <= tx_os_sig ? O_SIG_OS : O_SEQ_OS;
encoded_tx_data_reg[7:4] <= tx_os_sig ? O_SIG_OS : O_SEQ_OS;
encoded_tx_data_reg[15:8] <= tx_os[23:16];
encoded_tx_data_reg[23:16] <= tx_os[15:8];
encoded_tx_data_reg[31:24] <= tx_os[7:0];
tx_os_ready_reg <= 1'b1;
end else begin
encoded_tx_data_reg <= 32'd0;
end
end
OUTPUT_TYPE_ERROR: begin
encoded_tx_data_reg <= 32'h3c78f1e3; // CTRL_ERROR
@@ -816,6 +844,8 @@ always_ff @(posedge clk) begin
m_axis_tx_cpl_valid_reg <= 1'b0;
tx_os_ready_reg <= 1'b0;
encoded_tx_data_reg <= {24'd0, BLOCK_TYPE_CTRL};
encoded_tx_data_valid_reg <= 1'b0;
encoded_tx_hdr_reg <= SYNC_CTRL;

29
src/eth/rtl/taxi_axis_baser_tx_64.sv
View File

@@ -48,6 +48,14 @@ module taxi_axis_baser_tx_64 #
input wire logic tx_gbx_req_stall = '0,
output wire logic [GBX_CNT-1:0] tx_gbx_sync,
/*
* Ordered sets
*/
input wire logic [23:0] tx_os = '0,
input wire logic tx_os_sig = 1'b0,
input wire logic tx_os_valid = 1'b0,
output wire logic tx_os_ready,
/*
* PTP
*/
@@ -213,6 +221,8 @@ logic m_axis_tx_cpl_valid_reg = 1'b0;
logic m_axis_tx_cpl_valid_int_reg = 1'b0;
logic m_axis_tx_cpl_ts_borrow_reg = 1'b0;
logic tx_os_ready_reg = 1'b0;
logic [DATA_W-1:0] encoded_tx_data_reg = {{8{CTRL_IDLE}}, BLOCK_TYPE_CTRL};
logic encoded_tx_data_valid_reg = 1'b0;
logic [HDR_W-1:0] encoded_tx_hdr_reg = SYNC_CTRL;
@@ -732,6 +742,8 @@ always_ff @(posedge clk) begin
m_axis_tx_cpl_valid_reg <= 1'b0;
m_axis_tx_cpl_valid_int_reg <= 1'b0;
tx_os_ready_reg <= 1'b0;
start_packet_reg <= 2'b00;
stat_tx_byte_reg <= stat_tx_byte_next;
@@ -897,7 +909,20 @@ always_ff @(posedge clk) begin
end else begin
case (output_type_reg)
OUTPUT_TYPE_IDLE: begin
encoded_tx_data_reg <= {{8{CTRL_IDLE}}, BLOCK_TYPE_CTRL};
if (tx_os_valid) begin
encoded_tx_data_reg[7:0] <= BLOCK_TYPE_OS_04;
encoded_tx_data_reg[15:8] <= tx_os[23:16];
encoded_tx_data_reg[23:16] <= tx_os[15:8];
encoded_tx_data_reg[31:24] <= tx_os[7:0];
encoded_tx_data_reg[35:32] <= tx_os_sig ? O_SIG_OS : O_SEQ_OS;
encoded_tx_data_reg[39:36] <= tx_os_sig ? O_SIG_OS : O_SEQ_OS;
encoded_tx_data_reg[47:40] <= tx_os[23:16];
encoded_tx_data_reg[55:48] <= tx_os[15:8];
encoded_tx_data_reg[63:56] <= tx_os[7:0];
tx_os_ready_reg <= 1'b1;
end else begin
encoded_tx_data_reg <= {{8{CTRL_IDLE}}, BLOCK_TYPE_CTRL};
end
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_ERROR: begin
@@ -977,6 +1002,8 @@ always_ff @(posedge clk) begin
m_axis_tx_cpl_valid_reg <= 1'b0;
m_axis_tx_cpl_valid_int_reg <= 1'b0;
tx_os_ready_reg <= 1'b0;
encoded_tx_data_reg <= {{8{CTRL_IDLE}}, BLOCK_TYPE_CTRL};
encoded_tx_data_valid_reg <= 1'b0;
encoded_tx_hdr_reg <= SYNC_CTRL;

14
src/eth/rtl/taxi_eth_mac_phy_10g_rx.sv
View File

@@ -169,6 +169,13 @@ if (DATA_W == 64) begin
*/
.m_axis_rx(m_axis_rx),
/*
* Ordered sets
*/
.rx_os(),
.rx_os_sig(),
.rx_os_valid(),
/*
* PTP
*/
@@ -227,6 +234,13 @@ end else begin
*/
.m_axis_rx(m_axis_rx),
/*
* Ordered sets
*/
.rx_os(),
.rx_os_sig(),
.rx_os_valid(),
/*
* PTP
*/

16
src/eth/rtl/taxi_eth_mac_phy_10g_tx.sv
View File

@@ -167,6 +167,14 @@ if (DATA_W == 64) begin
.tx_gbx_req_stall(tx_gbx_req_stall),
.tx_gbx_sync(tx_gbx_sync),
/*
* Ordered sets
*/
.tx_os('0),
.tx_os_sig(1'b0),
.tx_os_valid(1'b0),
.tx_os_ready(),
/*
* PTP
*/
@@ -229,6 +237,14 @@ end else begin
.tx_gbx_req_stall(tx_gbx_req_stall),
.tx_gbx_sync(tx_gbx_sync),
/*
* Ordered sets
*/
.tx_os('0),
.tx_os_sig(1'b0),
.tx_os_valid(1'b0),
.tx_os_ready(),
/*
* PTP
*/

31
src/eth/tb/taxi_axis_baser_rx_32/test_taxi_axis_baser_rx_32.py
View File

@@ -265,6 +265,33 @@ async def run_test_oversize(dut, gbx_cfg=None, ifg=12):
await RisingEdge(dut.clk)
async def run_test_os(dut, gbx_cfg=None):
tb = TB(dut, gbx_cfg)
await tb.reset()
for sig in [False, True]:
for k in range(24):
os = 1 << k
tb.source.set_os(os, sig)
for k in range(20):
await RisingEdge(dut.clk)
assert int(dut.rx_os.value) == os
assert int(dut.rx_os_sig.value) == sig
tb.source.set_os(None)
for k in range(20):
await RisingEdge(dut.clk)
for k in range(10):
await RisingEdge(dut.clk)
def size_list():
return list(range(60, 128)) + [512, 1514, 9214] + [60]*10 + [i for i in range(64, 73) for k in range(8)]
@@ -297,6 +324,10 @@ if getattr(cocotb, 'top', None) is not None:
factory.add_option("gbx_cfg", gbx_cfgs)
factory.generate_tests()
factory = TestFactory(run_test_os)
factory.add_option("gbx_cfg", gbx_cfgs)
factory.generate_tests()
# cocotb-test

11
src/eth/tb/taxi_axis_baser_rx_32/test_taxi_axis_baser_rx_32.sv
View File

@@ -40,6 +40,10 @@ logic encoded_rx_hdr_valid;
taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(USER_W)) m_axis_rx();
logic [23:0] rx_os;
logic rx_os_sig;
logic rx_os_valid;
logic [PTP_TS_W-1:0] ptp_ts;
logic [15:0] cfg_rx_max_pkt_len;
@@ -86,6 +90,13 @@ uut (
*/
.m_axis_rx(m_axis_rx),
/*
* Ordered sets
*/
.rx_os(rx_os),
.rx_os_sig(rx_os_sig),
.rx_os_valid(rx_os_valid),
/*
* PTP
*/

31
src/eth/tb/taxi_axis_baser_rx_64/test_taxi_axis_baser_rx_64.py
View File

@@ -265,6 +265,33 @@ async def run_test_oversize(dut, gbx_cfg=None, ifg=12):
await RisingEdge(dut.clk)
async def run_test_os(dut, gbx_cfg=None):
tb = TB(dut, gbx_cfg)
await tb.reset()
for sig in [False, True]:
for k in range(24):
os = 1 << k
tb.source.set_os(os, sig)
for k in range(20):
await RisingEdge(dut.clk)
assert int(dut.rx_os.value) == os
assert int(dut.rx_os_sig.value) == sig
tb.source.set_os(None)
for k in range(20):
await RisingEdge(dut.clk)
for k in range(10):
await RisingEdge(dut.clk)
def size_list():
return list(range(60, 128)) + [512, 1514, 9214] + [60]*10 + [i for i in range(64, 73) for k in range(8)]
@@ -297,6 +324,10 @@ if getattr(cocotb, 'top', None) is not None:
factory.add_option("gbx_cfg", gbx_cfgs)
factory.generate_tests()
factory = TestFactory(run_test_os)
factory.add_option("gbx_cfg", gbx_cfgs)
factory.generate_tests()
# cocotb-test

11
src/eth/tb/taxi_axis_baser_rx_64/test_taxi_axis_baser_rx_64.sv
View File

@@ -40,6 +40,10 @@ logic encoded_rx_hdr_valid;
taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(USER_W)) m_axis_rx();
logic [23:0] rx_os;
logic rx_os_sig;
logic rx_os_valid;
logic [PTP_TS_W-1:0] ptp_ts;
logic [15:0] cfg_rx_max_pkt_len;
@@ -87,6 +91,13 @@ uut (
*/
.m_axis_rx(m_axis_rx),
/*
* Ordered sets
*/
.rx_os(rx_os),
.rx_os_sig(rx_os_sig),
.rx_os_valid(rx_os_valid),
/*
* PTP
*/

36
src/eth/tb/taxi_axis_baser_tx_32/test_taxi_axis_baser_tx_32.py
View File

@@ -68,6 +68,10 @@ class TB:
self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts, clock=dut.clk)
self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.clk, dut.rst)
dut.tx_os.setimmediatevalue(0)
dut.tx_os_sig.setimmediatevalue(0)
dut.tx_os_valid.setimmediatevalue(0)
dut.cfg_tx_max_pkt_len.setimmediatevalue(0)
dut.cfg_tx_ifg.setimmediatevalue(0)
dut.cfg_tx_enable.setimmediatevalue(0)
@@ -379,6 +383,34 @@ async def run_test_oversize(dut, gbx_cfg=None, ifg=12):
await RisingEdge(dut.clk)
async def run_test_os(dut, gbx_cfg=None):
tb = TB(dut, gbx_cfg)
await tb.reset()
for sig in [False, True]:
for k in range(24):
os = 1 << k
dut.tx_os.value = os
dut.tx_os_sig.value = sig
dut.tx_os_valid.value = 1
for k in range(20):
await RisingEdge(dut.clk)
assert tb.sink.get_os() == (os, sig)
dut.tx_os_valid.value = 0
for k in range(20):
await RisingEdge(dut.clk)
for k in range(10):
await RisingEdge(dut.clk)
def size_list():
return list(range(16, 128)) + [512, 1514, 9214] + [60]*10 + [i for i in range(64, 73) for k in range(8)]
@@ -417,6 +449,10 @@ if getattr(cocotb, 'top', None) is not None:
factory.add_option("gbx_cfg", gbx_cfgs)
factory.generate_tests()
factory = TestFactory(run_test_os)
factory.add_option("gbx_cfg", gbx_cfgs)
factory.generate_tests()
# cocotb-test

13
src/eth/tb/taxi_axis_baser_tx_32/test_taxi_axis_baser_tx_32.sv
View File

@@ -48,6 +48,11 @@ logic [GBX_CNT-1:0] tx_gbx_req_sync;
logic tx_gbx_req_stall;
logic [GBX_CNT-1:0] tx_gbx_sync;
logic [23:0] tx_os;
logic tx_os_sig;
logic tx_os_valid;
logic tx_os_ready;
logic [PTP_TS_W-1:0] ptp_ts;
logic [15:0] cfg_tx_max_pkt_len;
@@ -98,6 +103,14 @@ uut (
.tx_gbx_req_stall(tx_gbx_req_stall),
.tx_gbx_sync(tx_gbx_sync),
/*
* Ordered sets
*/
.tx_os(tx_os),
.tx_os_sig(tx_os_sig),
.tx_os_valid(tx_os_valid),
.tx_os_ready(tx_os_ready),
/*
* PTP
*/

36
src/eth/tb/taxi_axis_baser_tx_64/test_taxi_axis_baser_tx_64.py
View File

@@ -68,6 +68,10 @@ class TB:
self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts, clock=dut.clk)
self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.clk, dut.rst)
dut.tx_os.setimmediatevalue(0)
dut.tx_os_sig.setimmediatevalue(0)
dut.tx_os_valid.setimmediatevalue(0)
dut.cfg_tx_max_pkt_len.setimmediatevalue(0)
dut.cfg_tx_ifg.setimmediatevalue(0)
dut.cfg_tx_enable.setimmediatevalue(0)
@@ -488,6 +492,34 @@ async def run_test_oversize(dut, gbx_cfg=None, ifg=12):
await RisingEdge(dut.clk)
async def run_test_os(dut, gbx_cfg=None):
tb = TB(dut, gbx_cfg)
await tb.reset()
for sig in [False, True]:
for k in range(24):
os = 1 << k
dut.tx_os.value = os
dut.tx_os_sig.value = sig
dut.tx_os_valid.value = 1
for k in range(20):
await RisingEdge(dut.clk)
assert tb.sink.get_os() == (os, sig)
dut.tx_os_valid.value = 0
for k in range(20):
await RisingEdge(dut.clk)
for k in range(10):
await RisingEdge(dut.clk)
def size_list():
return list(range(16, 128)) + [512, 1514, 9214] + [60]*10 + [i for i in range(64, 73) for k in range(8)]
@@ -532,6 +564,10 @@ if getattr(cocotb, 'top', None) is not None:
factory.add_option("gbx_cfg", gbx_cfgs)
factory.generate_tests()
factory = TestFactory(run_test_os)
factory.add_option("gbx_cfg", gbx_cfgs)
factory.generate_tests()
# cocotb-test

13
src/eth/tb/taxi_axis_baser_tx_64/test_taxi_axis_baser_tx_64.sv
View File

@@ -48,6 +48,11 @@ logic [GBX_CNT-1:0] tx_gbx_req_sync;
logic tx_gbx_req_stall;
logic [GBX_CNT-1:0] tx_gbx_sync;
logic [23:0] tx_os;
logic tx_os_sig;
logic tx_os_valid;
logic tx_os_ready;
logic [PTP_TS_W-1:0] ptp_ts;
logic [15:0] cfg_tx_max_pkt_len;
@@ -98,6 +103,14 @@ uut (
.tx_gbx_req_stall(tx_gbx_req_stall),
.tx_gbx_sync(tx_gbx_sync),
/*
* Ordered sets
*/
.tx_os(tx_os),
.tx_os_sig(tx_os_sig),
.tx_os_valid(tx_os_valid),
.tx_os_ready(tx_os_ready),
/*
* PTP
*/