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eth: Update KC705 pins

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-03-13 19:51:27 -07:00
parent 29fadb6b16
commit 7a9e9f3370
6 changed files with 8 additions and 0 deletions
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1
src/eth/example/KC705/fpga/fpga.xdc
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@@ -151,6 +151,7 @@ set_property -dict {LOC G7 } [get_ports sgmii_mgt_refclk_n] ;# MGTREFCLK0N_117
#set_property -dict {LOC AG24 IOSTANDARD LVCMOS25 PULLUP true} [get_ports si5324_int] #set_property -dict {LOC AG24 IOSTANDARD LVCMOS25 PULLUP true} [get_ports si5324_int]
set_property -dict {LOC Y20 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable_b}] set_property -dict {LOC Y20 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable_b}]
set_property -dict {LOC P19 IOSTANDARD LVCMOS25} [get_ports {sfp_rx_los}]
# 125 MHz MGT reference clock (SGMII, 1000BASE-X) # 125 MHz MGT reference clock (SGMII, 1000BASE-X)
#create_clock -period 8.000 -name sgmii_mgt_refclk [get_ports sgmii_mgt_refclk_p] #create_clock -period 8.000 -name sgmii_mgt_refclk [get_ports sgmii_mgt_refclk_p]

2
src/eth/example/KC705/fpga/rtl/fpga.sv
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@@ -80,6 +80,7 @@ module fpga #
input wire logic sgmii_mgt_refclk_n, input wire logic sgmii_mgt_refclk_n,
output wire logic sfp_tx_disable_b, output wire logic sfp_tx_disable_b,
input wire logic sfp_rx_los,
/* /*
* Ethernet: 1000BASE-T GMII, RGMII, or SGMII * Ethernet: 1000BASE-T GMII, RGMII, or SGMII
@@ -700,6 +701,7 @@ core_inst (
.sfp_gmii_tx_en(sfp_gmii_tx_en_int), .sfp_gmii_tx_en(sfp_gmii_tx_en_int),
.sfp_gmii_tx_er(sfp_gmii_tx_er_int), .sfp_gmii_tx_er(sfp_gmii_tx_er_int),
.sfp_tx_disable_b(sfp_tx_disable_b), .sfp_tx_disable_b(sfp_tx_disable_b),
.sfp_rx_los(sfp_rx_los),
/* /*
* Ethernet: 1000BASE-T GMII/RGMII/SGMII * Ethernet: 1000BASE-T GMII/RGMII/SGMII

1
src/eth/example/KC705/fpga/rtl/fpga_core.sv
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@@ -79,6 +79,7 @@ module fpga_core #
output wire logic sfp_gmii_tx_en, output wire logic sfp_gmii_tx_en,
output wire logic sfp_gmii_tx_er, output wire logic sfp_gmii_tx_er,
output wire logic sfp_tx_disable_b, output wire logic sfp_tx_disable_b,
input wire logic sfp_rx_los,
/* /*
* Ethernet: 1000BASE-T * Ethernet: 1000BASE-T

1
src/eth/example/KC705/fpga_10g/fpga.xdc
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@@ -151,6 +151,7 @@ set_property -dict {LOC AE20 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports
set_property -dict {LOC AG24 IOSTANDARD LVCMOS25 PULLUP true} [get_ports si5324_int] set_property -dict {LOC AG24 IOSTANDARD LVCMOS25 PULLUP true} [get_ports si5324_int]
set_property -dict {LOC Y20 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable_b}] set_property -dict {LOC Y20 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable_b}]
set_property -dict {LOC P19 IOSTANDARD LVCMOS25} [get_ports {sfp_rx_los}]
# 125 MHz MGT reference clock (SGMII, 1000BASE-X) # 125 MHz MGT reference clock (SGMII, 1000BASE-X)
#create_clock -period 8.000 -name sgmii_mgt_refclk [get_ports sgmii_mgt_refclk_p] #create_clock -period 8.000 -name sgmii_mgt_refclk [get_ports sgmii_mgt_refclk_p]

2
src/eth/example/KC705/fpga_10g/rtl/fpga.sv
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@@ -84,6 +84,7 @@ module fpga #
input wire logic si5324_int, input wire logic si5324_int,
output wire logic sfp_tx_disable_b, output wire logic sfp_tx_disable_b,
input wire logic sfp_rx_los,
/* /*
* Ethernet: 1000BASE-T GMII or RGMII * Ethernet: 1000BASE-T GMII or RGMII
@@ -526,6 +527,7 @@ core_inst (
.sfp_mgt_refclk_n(sfp_mgt_refclk_n), .sfp_mgt_refclk_n(sfp_mgt_refclk_n),
.sfp_tx_disable_b(sfp_tx_disable_b), .sfp_tx_disable_b(sfp_tx_disable_b),
.sfp_rx_los(sfp_rx_los),
/* /*
* Ethernet: 1000BASE-T GMII/RGMII/SGMII * Ethernet: 1000BASE-T GMII/RGMII/SGMII

1
src/eth/example/KC705/fpga_10g/rtl/fpga_core.sv
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@@ -81,6 +81,7 @@ module fpga_core #
input wire logic sfp_mgt_refclk_n, input wire logic sfp_mgt_refclk_n,
output wire logic sfp_tx_disable_b, output wire logic sfp_tx_disable_b,
input wire logic sfp_rx_los,
/* /*
* Ethernet: 1000BASE-T * Ethernet: 1000BASE-T