bslathi19/taxi
1
0
Fork 0
mirror of https://github.com/fpganinja/taxi.git synced 2025-12-07 16:28:40 -08:00
Code Issues Packages Projects Releases Wiki Activity

eth: Add term_first_cycle_reg to reduce fanin

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-10-04 17:01:53 -07:00
parent 879b65cc70
commit 7e08164e8d
2 changed files with 19 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
src/eth/rtl/taxi_axis_xgmii_rx_32.sv
View File

@@ -109,8 +109,9 @@ logic [1:0] state_reg = STATE_IDLE, state_next;
// datapath control signals // datapath control signals
logic reset_crc; logic reset_crc;
logic [1:0] term_lane_reg = 0, term_lane_d0_reg = 0;
logic term_present_reg = 1'b0; logic term_present_reg = 1'b0;
logic term_first_cycle_reg = 1'b0;
logic [1:0] term_lane_reg = 0, term_lane_d0_reg = 0;
logic framing_error_reg = 1'b0; logic framing_error_reg = 1'b0;
logic [DATA_W-1:0] xgmii_rxd_d0 = '0; logic [DATA_W-1:0] xgmii_rxd_d0 = '0;
@@ -396,11 +397,11 @@ always_comb begin
state_next = STATE_IDLE; state_next = STATE_IDLE;
end else if (term_present_reg) begin end else if (term_present_reg) begin
reset_crc = 1'b1; reset_crc = 1'b1;
if (term_lane_reg == 0) begin if (term_first_cycle_reg) begin
// end this cycle // end this cycle
m_axis_rx_tkeep_next = 4'b1111; m_axis_rx_tkeep_next = 4'b1111;
m_axis_rx_tlast_next = 1'b1; m_axis_rx_tlast_next = 1'b1;
if (term_lane_reg == 0 && crc_valid_save[3]) begin if (crc_valid_save[3]) begin
// CRC valid // CRC valid
if (frame_oversize_next) begin if (frame_oversize_next) begin
// too long // too long
@@ -524,14 +525,16 @@ always_ff @(posedge clk) begin
stat_rx_err_preamble_reg <= stat_rx_err_preamble_next; stat_rx_err_preamble_reg <= stat_rx_err_preamble_next;
if (!GBX_IF_EN || xgmii_rx_valid) begin if (!GBX_IF_EN || xgmii_rx_valid) begin
term_lane_reg <= 0;
term_present_reg <= 1'b0; term_present_reg <= 1'b0;
term_first_cycle_reg <= 1'b0;
term_lane_reg <= 0;
framing_error_reg <= xgmii_rxc != 0; framing_error_reg <= xgmii_rxc != 0;
for (integer i = CTRL_W-1; i >= 0; i = i - 1) begin for (integer i = CTRL_W-1; i >= 0; i = i - 1) begin
if (xgmii_rxc[i] && (xgmii_rxd[i*8 +: 8] == XGMII_TERM)) begin if (xgmii_rxc[i] && (xgmii_rxd[i*8 +: 8] == XGMII_TERM)) begin
term_lane_reg <= 2'(i);
term_present_reg <= 1'b1; term_present_reg <= 1'b1;
term_first_cycle_reg <= i == 0;
term_lane_reg <= 2'(i);
framing_error_reg <= (xgmii_rxc & ({CTRL_W{1'b1}} >> (CTRL_W-i))) != 0; framing_error_reg <= (xgmii_rxc & ({CTRL_W{1'b1}} >> (CTRL_W-i))) != 0;
end end
end end

17
src/eth/rtl/taxi_axis_xgmii_rx_64.sv
View File

@@ -114,8 +114,9 @@ logic [31:0] swap_rxd = 32'd0;
logic [3:0] swap_rxc = 4'd0; logic [3:0] swap_rxc = 4'd0;
logic [3:0] swap_rxc_term = 4'd0; logic [3:0] swap_rxc_term = 4'd0;
logic [2:0] term_lane_reg = 0, term_lane_d0_reg = 0;
logic term_present_reg = 1'b0; logic term_present_reg = 1'b0;
logic term_first_cycle_reg = 1'b0;
logic [2:0] term_lane_reg = 0, term_lane_d0_reg = 0;
logic framing_error_reg = 1'b0, framing_error_d0_reg = 1'b0; logic framing_error_reg = 1'b0, framing_error_d0_reg = 1'b0;
logic [DATA_W-1:0] xgmii_rxd_d0 = '0; logic [DATA_W-1:0] xgmii_rxd_d0 = '0;
@@ -393,7 +394,7 @@ always_comb begin
state_next = STATE_IDLE; state_next = STATE_IDLE;
end else if (term_present_reg) begin end else if (term_present_reg) begin
reset_crc = 1'b1; reset_crc = 1'b1;
if (term_lane_reg <= 4) begin if (term_first_cycle_reg) begin
// end this cycle // end this cycle
m_axis_rx_tkeep_next = {KEEP_W{1'b1}} >> 3'(CTRL_W-4-term_lane_reg); m_axis_rx_tkeep_next = {KEEP_W{1'b1}} >> 3'(CTRL_W-4-term_lane_reg);
m_axis_rx_tlast_next = 1'b1; m_axis_rx_tlast_next = 1'b1;
@@ -552,14 +553,16 @@ always_ff @(posedge clk) begin
xgmii_rxd_d0 <= {xgmii_rxd_masked[31:0], swap_rxd}; xgmii_rxd_d0 <= {xgmii_rxd_masked[31:0], swap_rxd};
xgmii_rxc_d0 <= {xgmii_rxc[3:0], swap_rxc}; xgmii_rxc_d0 <= {xgmii_rxc[3:0], swap_rxc};
term_lane_reg <= 0;
term_present_reg <= 1'b0; term_present_reg <= 1'b0;
term_first_cycle_reg <= 1'b0;
term_lane_reg <= 0;
framing_error_reg <= {xgmii_rxc[3:0], swap_rxc} != 0; framing_error_reg <= {xgmii_rxc[3:0], swap_rxc} != 0;
for (integer i = CTRL_W-1; i >= 0; i = i - 1) begin for (integer i = CTRL_W-1; i >= 0; i = i - 1) begin
if ({xgmii_term[3:0], swap_rxc_term}[i]) begin if ({xgmii_term[3:0], swap_rxc_term}[i]) begin
term_lane_reg <= 3'(i);
term_present_reg <= 1'b1; term_present_reg <= 1'b1;
term_first_cycle_reg <= i <= 4;
term_lane_reg <= 3'(i);
framing_error_reg <= ({xgmii_rxc[3:0], swap_rxc} & ({CTRL_W{1'b1}} >> (CTRL_W-i))) != 0; framing_error_reg <= ({xgmii_rxc[3:0], swap_rxc} & ({CTRL_W{1'b1}} >> (CTRL_W-i))) != 0;
end end
end end
@@ -567,14 +570,16 @@ always_ff @(posedge clk) begin
xgmii_rxd_d0 <= xgmii_rxd_masked; xgmii_rxd_d0 <= xgmii_rxd_masked;
xgmii_rxc_d0 <= xgmii_rxc; xgmii_rxc_d0 <= xgmii_rxc;
term_lane_reg <= 0;
term_present_reg <= 1'b0; term_present_reg <= 1'b0;
term_first_cycle_reg <= 1'b0;
term_lane_reg <= 0;
framing_error_reg <= xgmii_rxc != 0; framing_error_reg <= xgmii_rxc != 0;
for (integer i = CTRL_W-1; i >= 0; i = i - 1) begin for (integer i = CTRL_W-1; i >= 0; i = i - 1) begin
if (xgmii_rxc[i] && (xgmii_rxd[i*8 +: 8] == XGMII_TERM)) begin if (xgmii_rxc[i] && (xgmii_rxd[i*8 +: 8] == XGMII_TERM)) begin
term_lane_reg <= 3'(i);
term_present_reg <= 1'b1; term_present_reg <= 1'b1;
term_first_cycle_reg <= i <= 4;
term_lane_reg <= 3'(i);
framing_error_reg <= (xgmii_rxc & ({CTRL_W{1'b1}} >> (CTRL_W-i))) != 0; framing_error_reg <= (xgmii_rxc & ({CTRL_W{1'b1}} >> (CTRL_W-i))) != 0;
end end
end end