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example: Add signal sync timing constraints to example designs

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-02-25 16:04:32 -08:00
parent 8785c1517b
commit 84fb93b5c3
43 changed files with 43 additions and 0 deletions
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example/Alveo/fpga/fpga_X3522_10g/Makefile
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@@ -26,6 +26,7 @@ XDC_FILES = ../fpga_x3522.xdc
XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl
XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl
XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl
# IP
IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_161.tcl