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example/fb2CG: Add example design for fb2CG@KU15P
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
@@ -98,6 +98,7 @@ Example designs are provided for several different FPGA boards, showcasing many
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* Cisco Nexus K3P-Q/ExaNIC X100 (Xilinx Kintex UltraScale+ XCKU3P)
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* Digilent Arty A7 (Xilinx Artix 7 XC7A35T)
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* HiTech Global HTG-940 (Xilinx Virtex UltraScale+ XCVU9P/XCVU13P)
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* Silicom fb2CG@KU15P (Xilinx Kintex UltraScale+ XCKU15P)
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* Xilinx Alveo U45N/SN1000 (Xilinx Virtex UltraScale+ XCU26)
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* Xilinx Alveo U50 (Xilinx Virtex UltraScale+ XCU50)
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* Xilinx Alveo U55C (Xilinx Virtex UltraScale+ XCU55C)
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32
example/fb2CG/fpga/README.md
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32
example/fb2CG/fpga/README.md
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@@ -0,0 +1,32 @@
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# Taxi Example Design for fb2CG@KU15P
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## Introduction
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This example design targets the Silicom fb2CG@KU15P FPGA board.
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The design places looped-back MACs on the QSFP28 ports.
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* QSFP28
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* Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers
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## Board details
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* FPGA: xcku15p-ffve1760-2-e
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* 25GBASE-R PHY: Soft PCS with GTY transceivers
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## Licensing
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* Toolchain
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* Vivado Enterprise (requires license)
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* IP
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* No licensed vendor IP or 3rd party IP
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## How to build
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Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
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## How to test
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Run `make program` to program the board with Vivado.
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To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems.
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153
example/fb2CG/fpga/common/vivado.mk
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153
example/fb2CG/fpga/common/vivado.mk
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@@ -0,0 +1,153 @@
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# SPDX-License-Identifier: MIT
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###################################################################
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#
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# Xilinx Vivado FPGA Makefile
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#
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# Copyright (c) 2016-2025 Alex Forencich
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#
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###################################################################
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#
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# Parameters:
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# FPGA_TOP - Top module name
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# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
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# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
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# SYN_FILES - list of source files
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# INC_FILES - list of include files
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# XDC_FILES - list of timing constraint files
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# XCI_FILES - list of IP XCI files
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# IP_TCL_FILES - list of IP TCL files (sourced during project creation)
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# CONFIG_TCL_FILES - list of config TCL files (sourced before each build)
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#
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# Note: both SYN_FILES and INC_FILES support file list files. File list
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# files are files with a .f extension that contain a list of additional
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# files to include, one path relative to the .f file location per line.
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# The .f files are processed recursively, and then the complete file list
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# is de-duplicated, with later files in the list taking precedence.
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#
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# Example:
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#
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# FPGA_TOP = fpga
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# FPGA_FAMILY = VirtexUltrascale
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# FPGA_DEVICE = xcvu095-ffva2104-2-e
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# SYN_FILES = rtl/fpga.v
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# XDC_FILES = fpga.xdc
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# XCI_FILES = ip/pcspma.xci
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# include ../common/vivado.mk
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#
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###################################################################
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# phony targets
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.PHONY: fpga vivado tmpclean clean distclean
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# prevent make from deleting intermediate files and reports
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.PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm
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.SECONDARY:
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CONFIG ?= config.mk
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-include $(CONFIG)
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FPGA_TOP ?= fpga
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PROJECT ?= $(FPGA_TOP)
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XDC_FILES ?= $(PROJECT).xdc
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# handle file list files
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process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
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process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
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uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
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SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES)))
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INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES)))
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###################################################################
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# Main Targets
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#
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# all: build everything (fpga)
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# fpga: build FPGA config
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# vivado: open project in Vivado
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# tmpclean: remove intermediate files
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# clean: remove output files and project files
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# distclean: remove archived output files
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###################################################################
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all: fpga
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fpga: $(PROJECT).bit
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vivado: $(PROJECT).xpr
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vivado $(PROJECT).xpr
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tmpclean::
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-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
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-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
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clean:: tmpclean
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-rm -rf *.bit *.bin *.ltx *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
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-rm -rf *_utilization.rpt *_utilization_hierarchical.rpt
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distclean:: clean
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-rm -rf rev
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###################################################################
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# Target implementations
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###################################################################
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# Vivado project file
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# create fresh project if Makefile or IP files have changed
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create_project.tcl: Makefile $(XCI_FILES) $(IP_TCL_FILES)
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rm -rf defines.v
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touch defines.v
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for x in $(DEFS); do echo '`define' $$x >> defines.v; done
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echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@
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echo "add_files -fileset sources_1 defines.v $(SYN_FILES)" >> $@
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echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@
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echo "add_files -fileset constrs_1 $(XDC_FILES)" >> $@
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for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done
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for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done
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for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
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# source config TCL scripts if any source file has changed
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update_config.tcl: $(CONFIG_TCL_FILES) $(SYN_FILES) $(INC_FILES) $(XDC_FILES)
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echo "open_project -quiet $(PROJECT).xpr" > $@
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for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
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$(PROJECT).xpr: create_project.tcl update_config.tcl
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vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
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# synthesis run
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$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES) $(INC_FILES) $(XDC_FILES) | $(PROJECT).xpr
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echo "open_project $(PROJECT).xpr" > run_synth.tcl
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echo "reset_run synth_1" >> run_synth.tcl
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echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
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echo "wait_on_run synth_1" >> run_synth.tcl
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vivado -nojournal -nolog -mode batch -source run_synth.tcl
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# implementation run
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$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp
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echo "open_project $(PROJECT).xpr" > run_impl.tcl
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echo "reset_run impl_1" >> run_impl.tcl
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echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
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echo "wait_on_run impl_1" >> run_impl.tcl
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echo "open_run impl_1" >> run_impl.tcl
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echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl
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echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl
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vivado -nojournal -nolog -mode batch -source run_impl.tcl
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# output files (including potentially bit, bin, ltx, and xsa)
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$(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp
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echo "open_project $(PROJECT).xpr" > generate_bit.tcl
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echo "open_run impl_1" >> generate_bit.tcl
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echo "write_bitstream -force -bin_file $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl
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echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl
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echo "write_hw_platform -fixed -force -include_bit $(PROJECT).xsa" >> generate_bit.tcl
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vivado -nojournal -nolog -mode batch -source generate_bit.tcl
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ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit .
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ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bin .
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if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi
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mkdir -p rev
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COUNT=100; \
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while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \
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do COUNT=$$((COUNT+1)); done; \
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cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \
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cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \
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if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \
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if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi
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810
example/fb2CG/fpga/fpga.xdc
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810
example/fb2CG/fpga/fpga.xdc
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@@ -0,0 +1,810 @@
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# SPDX-License-Identifier: MIT
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#
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# Copyright (c) 2014-2025 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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#
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# XDC constraints for the fb2CG@KU15P
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# part: xcku15p-ffve1760-2-e
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# General configuration
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set_property CFGBVS GND [current_design]
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set_property CONFIG_VOLTAGE 1.8 [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
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set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN disable [current_design]
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set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
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set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
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set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
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set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design]
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set_property CONFIG_MODE SPIx4 [current_design]
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set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
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# System clocks
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# init clock 50 MHz
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set_property -dict {LOC E7 IOSTANDARD LVCMOS18} [get_ports {init_clk}]
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create_clock -period 20.000 -name init_clk [get_ports {init_clk}]
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# E7 is not a global clock capable input, so need to set CLOCK_DEDICATED_ROUTE to satisfy DRC
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#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets init_clk_ibuf_inst/O]
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set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets {init_clk_bufg}]
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# DDR4 refclk1
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#set_property -dict {LOC AT32 IOSTANDARD DIFF_SSTL12} [get_ports {clk_ddr4_refclk1_p}]
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#set_property -dict {LOC AU32 IOSTANDARD DIFF_SSTL12} [get_ports {clk_ddr4_refclk1_n}]
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#create_clock -period 3.750 -name clk_ddr4_refclk1 [get_ports {clk_ddr4_refclk1_p}]
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# DDR4 refclk2
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#set_property -dict {LOC G29 IOSTANDARD DIFF_SSTL12} [get_ports {clk_ddr4_refclk2_p}]
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#set_property -dict {LOC G28 IOSTANDARD DIFF_SSTL12} [get_ports {clk_ddr4_refclk2_n}]
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#create_clock -period 3.750 -name clk_ddr4_refclk2 [get_ports {clk_ddr4_refclk1_p}]
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# LEDs
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set_property -dict {LOC C4 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports {led_sreg_d}]
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set_property -dict {LOC B3 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports {led_sreg_ld}]
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set_property -dict {LOC G3 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports {led_sreg_clk}]
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set_property -dict {LOC C5 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_bmc[0]}]
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set_property -dict {LOC C6 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_bmc[1]}]
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set_property -dict {LOC D3 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports {led_exp[0]}]
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set_property -dict {LOC D4 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports {led_exp[1]}]
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set_false_path -to [get_ports {led_sreg_d led_sreg_ld led_sreg_clk led_bmc[*] led_exp[*]}]
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set_output_delay 0 [get_ports {led_sreg_d led_sreg_ld led_sreg_clk led_bmc[*] led_exp[*]}]
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# GPIO
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#set_property -dict {LOC B4 IOSTANDARD LVCMOS33} [get_ports {pps_in}] ;# from SMA J6 via Q1 (inverted)
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#set_property -dict {LOC A4 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 4} [get_ports {pps_out}] ;# to SMA J6 via U4 and U5, and u.FL J7 (PPS OUT) via U3
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#set_property -dict {LOC A3 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports {pps_out_en}] ; # to U5 IN (connects pps_out to SMA J6 when high)
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#set_property -dict {LOC H2 IOSTANDARD LVCMOS33} [get_ports {misc_ucoax}] ; from u.FL J5 (PPS IN)
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#set_false_path -to [get_ports {pps_out pps_out_en}]
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#set_output_delay 0 [get_ports {pps_out pps_out_en}]
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#set_false_path -from [get_ports {pps_in}]
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#set_input_delay 0 [get_ports {pps_in}]
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# BMC interface
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#set_property -dict {LOC D7 IOSTANDARD LVCMOS18} [get_ports {bmc_miso}]
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#set_property -dict {LOC J4 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports {bmc_nss}]
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#set_property -dict {LOC B6 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports {bmc_clk}]
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#set_property -dict {LOC D5 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports {bmc_mosi}]
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#set_property -dict {LOC H4 IOSTANDARD LVCMOS18} [get_ports {bmc_int}]
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#set_false_path -to [get_ports {bmc_nss bmc_clk bmc_mosi}]
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#set_output_delay 0 [get_ports {bmc_nss bmc_clk bmc_mosi}]
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#set_false_path -from [get_ports {bmc_miso bmc_int}]
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#set_input_delay 0 [get_ports {bmc_miso bmc_int}]
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# Board status
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#set_property -dict {LOC J2 IOSTANDARD LVCMOS33} [get_ports {fan_tacho[0]}]
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#set_property -dict {LOC J3 IOSTANDARD LVCMOS33} [get_ports {fan_tacho[1]}]
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set_property -dict {LOC A6 IOSTANDARD LVCMOS18} [get_ports {pg[0]}]
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set_property -dict {LOC C7 IOSTANDARD LVCMOS18} [get_ports {pg[1]}]
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#set_property -dict {LOC E2 IOSTANDARD LVCMOS33} [get_ports {pwrbrk}]
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set_false_path -from [get_ports {pg[*]}]
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set_input_delay 0 [get_ports {pg[*]}]
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# QSFP28 Interfaces
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set_property -dict {LOC Y39 } [get_ports {qsfp_0_rx_p[0]}] ;# MGTYRXP0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
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set_property -dict {LOC Y40 } [get_ports {qsfp_0_rx_n[0]}] ;# MGTYRXN0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
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set_property -dict {LOC Y34 } [get_ports {qsfp_0_tx_p[0]}] ;# MGTYTXP0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
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set_property -dict {LOC Y35 } [get_ports {qsfp_0_tx_n[0]}] ;# MGTYTXN0_130 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
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set_property -dict {LOC W41 } [get_ports {qsfp_0_rx_p[1]}] ;# MGTYRXP1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
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set_property -dict {LOC W42 } [get_ports {qsfp_0_rx_n[1]}] ;# MGTYRXN1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
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set_property -dict {LOC W36 } [get_ports {qsfp_0_tx_p[1]}] ;# MGTYTXP1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
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set_property -dict {LOC W37 } [get_ports {qsfp_0_tx_n[1]}] ;# MGTYTXN1_130 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
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set_property -dict {LOC V39 } [get_ports {qsfp_0_rx_p[2]}] ;# MGTYRXP2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
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set_property -dict {LOC V40 } [get_ports {qsfp_0_rx_n[2]}] ;# MGTYRXN2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
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set_property -dict {LOC V34 } [get_ports {qsfp_0_tx_p[2]}] ;# MGTYTXP2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
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set_property -dict {LOC V35 } [get_ports {qsfp_0_tx_n[2]}] ;# MGTYTXN2_130 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
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set_property -dict {LOC U41 } [get_ports {qsfp_0_rx_p[3]}] ;# MGTYRXP3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
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set_property -dict {LOC U42 } [get_ports {qsfp_0_rx_n[3]}] ;# MGTYRXN3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
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set_property -dict {LOC U36 } [get_ports {qsfp_0_tx_p[3]}] ;# MGTYTXP3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
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set_property -dict {LOC U37 } [get_ports {qsfp_0_tx_n[3]}] ;# MGTYTXN3_130 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
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set_property -dict {LOC W32 } [get_ports {qsfp_0_mgt_refclk_p}] ;# MGTREFCLK0P_130 from U28
|
||||
set_property -dict {LOC W33 } [get_ports {qsfp_0_mgt_refclk_n}] ;# MGTREFCLK0N_130 from U28
|
||||
set_property -dict {LOC B9 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {qsfp_0_mod_prsnt_n}]
|
||||
set_property -dict {LOC A8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports {qsfp_0_reset_n}]
|
||||
set_property -dict {LOC A9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports {qsfp_0_lp_mode}]
|
||||
set_property -dict {LOC A10 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {qsfp_0_intr_n}]
|
||||
#set_property -dict {LOC B8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports {qsfp_0_i2c_scl}]
|
||||
#set_property -dict {LOC B7 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports {qsfp_0_i2c_sda}]
|
||||
|
||||
# 161.1328125 MHz MGT reference clock
|
||||
create_clock -period 6.206 -name qsfp_0_mgt_refclk [get_ports {qsfp_0_mgt_refclk_p}]
|
||||
|
||||
set_false_path -to [get_ports {qsfp_0_reset_n qsfp_0_lp_mode}]
|
||||
set_output_delay 0 [get_ports {qsfp_0_reset_n qsfp_0_lp_mode}]
|
||||
set_false_path -from [get_ports {qsfp_0_mod_prsnt_n qsfp_0_intr_n}]
|
||||
set_input_delay 0 [get_ports {qsfp_0_mod_prsnt_n qsfp_0_intr_n}]
|
||||
|
||||
#set_false_path -to [get_ports {qsfp_0_i2c_scl qsfp_0_i2c_sda}]
|
||||
#set_output_delay 0 [get_ports {qsfp_0_i2c_scl qsfp_0_i2c_sda}]
|
||||
#set_false_path -from [get_ports {qsfp_0_i2c_scl qsfp_0_i2c_sda}]
|
||||
#set_input_delay 0 [get_ports {qsfp_0_i2c_scl qsfp_0_i2c_sda}]
|
||||
|
||||
set_property -dict {LOC M39 } [get_ports {qsfp_1_rx_p[0]}] ;# MGTYRXP0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC M40 } [get_ports {qsfp_1_rx_n[0]}] ;# MGTYRXN0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC M34 } [get_ports {qsfp_1_tx_p[0]}] ;# MGTYTXP0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC M35 } [get_ports {qsfp_1_tx_n[0]}] ;# MGTYTXN0_132 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC L41 } [get_ports {qsfp_1_rx_p[1]}] ;# MGTYRXP1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC L42 } [get_ports {qsfp_1_rx_n[1]}] ;# MGTYRXN1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC L36 } [get_ports {qsfp_1_tx_p[1]}] ;# MGTYTXP1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC L37 } [get_ports {qsfp_1_tx_n[1]}] ;# MGTYTXN1_132 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC K39 } [get_ports {qsfp_1_rx_p[2]}] ;# MGTYRXP2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC K40 } [get_ports {qsfp_1_rx_n[2]}] ;# MGTYRXN2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC K34 } [get_ports {qsfp_1_tx_p[2]}] ;# MGTYTXP2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC K35 } [get_ports {qsfp_1_tx_n[2]}] ;# MGTYTXN2_132 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC J41 } [get_ports {qsfp_1_rx_p[3]}] ;# MGTYRXP3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC J42 } [get_ports {qsfp_1_rx_n[3]}] ;# MGTYRXN3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC J36 } [get_ports {qsfp_1_tx_p[3]}] ;# MGTYTXP3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC J37 } [get_ports {qsfp_1_tx_n[3]}] ;# MGTYTXN3_132 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5
|
||||
set_property -dict {LOC P30 } [get_ports {qsfp_1_mgt_refclk_p}] ;# MGTREFCLK0P_132 from U28
|
||||
set_property -dict {LOC P31 } [get_ports {qsfp_1_mgt_refclk_n}] ;# MGTREFCLK0N_132 from U28
|
||||
set_property -dict {LOC E10 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {qsfp_1_mod_prsnt_n}]
|
||||
set_property -dict {LOC C10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports {qsfp_1_reset_n}]
|
||||
set_property -dict {LOC D9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports {qsfp_1_lp_mode}]
|
||||
set_property -dict {LOC D10 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {qsfp_1_intr_n}]
|
||||
#set_property -dict {LOC C9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports {qsfp_1_i2c_scl}]
|
||||
#set_property -dict {LOC D8 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports {qsfp_1_i2c_sda}]
|
||||
|
||||
# 161.1328125 MHz MGT reference clock
|
||||
create_clock -period 6.206 -name qsfp_1_mgt_refclk [get_ports {qsfp_1_mgt_refclk_p}]
|
||||
|
||||
set_false_path -to [get_ports {qsfp_1_reset_n qsfp_1_lp_mode}]
|
||||
set_output_delay 0 [get_ports {qsfp_1_reset_n qsfp_1_lp_mode}]
|
||||
set_false_path -from [get_ports {qsfp_1_mod_prsnt_n qsfp_1_intr_n}]
|
||||
set_input_delay 0 [get_ports {qsfp_1_mod_prsnt_n qsfp_1_intr_n}]
|
||||
|
||||
#set_false_path -to [get_ports {qsfp_1_i2c_scl qsfp_1_i2c_sda}]
|
||||
#set_output_delay 0 [get_ports {qsfp_1_i2c_scl qsfp_1_i2c_sda}]
|
||||
#set_false_path -from [get_ports {qsfp_1_i2c_scl qsfp_1_i2c_sda}]
|
||||
#set_input_delay 0 [get_ports {qsfp_1_i2c_scl qsfp_1_i2c_sda}]
|
||||
|
||||
# Expansion connector
|
||||
#set_property -dict {LOC AG41} [get_ports {exp_rx_p[0]}] ;# MGTYRXP0_128 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC AG42} [get_ports {exp_rx_n[0]}] ;# MGTYRXN0_128 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC AG36} [get_ports {exp_tx_p[0]}] ;# MGTYTXP0_128 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC AG37} [get_ports {exp_tx_n[0]}] ;# MGTYTXN0_128 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC AH39} [get_ports {exp_rx_p[1]}] ;# MGTYRXP0_128 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC AH40} [get_ports {exp_rx_n[1]}] ;# MGTYRXN0_128 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC AH34} [get_ports {exp_tx_p[1]}] ;# MGTYTXP0_128 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC AH35} [get_ports {exp_tx_n[1]}] ;# MGTYTXN0_128 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC AJ41} [get_ports {exp_rx_p[2]}] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AJ42} [get_ports {exp_rx_n[2]}] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AJ36} [get_ports {exp_tx_p[2]}] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AJ37} [get_ports {exp_tx_n[2]}] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AK39} [get_ports {exp_rx_p[3]}] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AK40} [get_ports {exp_rx_n[3]}] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AK34} [get_ports {exp_tx_p[3]}] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AK35} [get_ports {exp_tx_n[3]}] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AL41} [get_ports {exp_rx_p[4]}] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AL42} [get_ports {exp_rx_n[4]}] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AL36} [get_ports {exp_tx_p[4]}] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AL37} [get_ports {exp_tx_n[4]}] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AM39} [get_ports {exp_rx_p[5]}] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AM40} [get_ports {exp_rx_n[5]}] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AM34} [get_ports {exp_tx_p[5]}] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AM35} [get_ports {exp_tx_n[5]}] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AL32} [get_ports {exp_refclk_0_p}] ;# MGTREFCLK0P_128 from U28
|
||||
#set_property -dict {LOC AL33} [get_ports {exp_refclk_0_n}] ;# MGTREFCLK0N_128 from U28
|
||||
#set_property -dict {LOC AG32} [get_ports {exp_refclk_1_p}] ;# MGTREFCLK0P_127 from U28
|
||||
#set_property -dict {LOC AG33} [get_ports {exp_refclk_1_n}] ;# MGTREFCLK0N_127 from U28
|
||||
#set_property -dict {LOC E3 IOSTANDARD LVCMOS33} [get_ports {exp_gpio[0]}]
|
||||
#set_property -dict {LOC F3 IOSTANDARD LVCMOS33} [get_ports {exp_gpio[1]}]
|
||||
|
||||
# 161.1328125 MHz MGT reference clock
|
||||
#create_clock -period 6.206 -name exp_refclk_0 [get_ports {exp_refclk_0_p}]
|
||||
#create_clock -period 6.206 -name exp_refclk_1 [get_ports {exp_refclk_1_p}]
|
||||
|
||||
# PCIe Interface
|
||||
#set_property -dict {LOC AG2 } [get_ports {pcie_rx_p[0]}] ;# MGTHRXP3_227 GTHE4_CHANNEL_X0Y15 / GTHE4_COMMON_X0Y3
|
||||
#set_property -dict {LOC AG1 } [get_ports {pcie_rx_n[0]}] ;# MGTHRXN3_227 GTHE4_CHANNEL_X0Y15 / GTHE4_COMMON_X0Y3
|
||||
#set_property -dict {LOC AG6 } [get_ports {pcie_tx_p[0]}] ;# MGTHTXP3_227 GTHE4_CHANNEL_X0Y15 / GTHE4_COMMON_X0Y3
|
||||
#set_property -dict {LOC AG5 } [get_ports {pcie_tx_n[0]}] ;# MGTHTXN3_227 GTHE4_CHANNEL_X0Y15 / GTHE4_COMMON_X0Y3
|
||||
#set_property -dict {LOC AH4 } [get_ports {pcie_rx_p[1]}] ;# MGTHRXP2_227 GTHE4_CHANNEL_X0Y14 / GTHE4_COMMON_X0Y3
|
||||
#set_property -dict {LOC AH3 } [get_ports {pcie_rx_n[1]}] ;# MGTHRXN2_227 GTHE4_CHANNEL_X0Y14 / GTHE4_COMMON_X0Y3
|
||||
#set_property -dict {LOC AH8 } [get_ports {pcie_tx_p[1]}] ;# MGTHTXP2_227 GTHE4_CHANNEL_X0Y14 / GTHE4_COMMON_X0Y3
|
||||
#set_property -dict {LOC AH7 } [get_ports {pcie_tx_n[1]}] ;# MGTHTXN2_227 GTHE4_CHANNEL_X0Y14 / GTHE4_COMMON_X0Y3
|
||||
#set_property -dict {LOC AJ2 } [get_ports {pcie_rx_p[2]}] ;# MGTHRXP1_227 GTHE4_CHANNEL_X0Y13 / GTHE4_COMMON_X0Y3
|
||||
#set_property -dict {LOC AJ1 } [get_ports {pcie_rx_n[2]}] ;# MGTHRXN1_227 GTHE4_CHANNEL_X0Y13 / GTHE4_COMMON_X0Y3
|
||||
#set_property -dict {LOC AJ6 } [get_ports {pcie_tx_p[2]}] ;# MGTHTXP1_227 GTHE4_CHANNEL_X0Y13 / GTHE4_COMMON_X0Y3
|
||||
#set_property -dict {LOC AJ5 } [get_ports {pcie_tx_n[2]}] ;# MGTHTXN1_227 GTHE4_CHANNEL_X0Y13 / GTHE4_COMMON_X0Y3
|
||||
#set_property -dict {LOC AK4 } [get_ports {pcie_rx_p[3]}] ;# MGTHRXP0_227 GTHE4_CHANNEL_X0Y12 / GTHE4_COMMON_X0Y3
|
||||
#set_property -dict {LOC AK3 } [get_ports {pcie_rx_n[3]}] ;# MGTHRXN0_227 GTHE4_CHANNEL_X0Y12 / GTHE4_COMMON_X0Y3
|
||||
#set_property -dict {LOC AK8 } [get_ports {pcie_tx_p[3]}] ;# MGTHTXP0_227 GTHE4_CHANNEL_X0Y12 / GTHE4_COMMON_X0Y3
|
||||
#set_property -dict {LOC AK7 } [get_ports {pcie_tx_n[3]}] ;# MGTHTXN0_227 GTHE4_CHANNEL_X0Y12 / GTHE4_COMMON_X0Y3
|
||||
#set_property -dict {LOC AL2 } [get_ports {pcie_rx_p[4]}] ;# MGTHRXP3_226 GTHE4_CHANNEL_X0Y11 / GTHE4_COMMON_X0Y2
|
||||
#set_property -dict {LOC AL1 } [get_ports {pcie_rx_n[4]}] ;# MGTHRXN3_226 GTHE4_CHANNEL_X0Y11 / GTHE4_COMMON_X0Y2
|
||||
#set_property -dict {LOC AL6 } [get_ports {pcie_tx_p[4]}] ;# MGTHTXP3_226 GTHE4_CHANNEL_X0Y11 / GTHE4_COMMON_X0Y2
|
||||
#set_property -dict {LOC AL5 } [get_ports {pcie_tx_n[4]}] ;# MGTHTXN3_226 GTHE4_CHANNEL_X0Y11 / GTHE4_COMMON_X0Y2
|
||||
#set_property -dict {LOC AM4 } [get_ports {pcie_rx_p[5]}] ;# MGTHRXP2_226 GTHE4_CHANNEL_X0Y10 / GTHE4_COMMON_X0Y2
|
||||
#set_property -dict {LOC AM3 } [get_ports {pcie_rx_n[5]}] ;# MGTHRXN2_226 GTHE4_CHANNEL_X0Y10 / GTHE4_COMMON_X0Y2
|
||||
#set_property -dict {LOC AM8 } [get_ports {pcie_tx_p[5]}] ;# MGTHTXP2_226 GTHE4_CHANNEL_X0Y10 / GTHE4_COMMON_X0Y2
|
||||
#set_property -dict {LOC AM7 } [get_ports {pcie_tx_n[5]}] ;# MGTHTXN2_226 GTHE4_CHANNEL_X0Y10 / GTHE4_COMMON_X0Y2
|
||||
#set_property -dict {LOC AN2 } [get_ports {pcie_rx_p[6]}] ;# MGTHRXP1_226 GTHE4_CHANNEL_X0Y9 / GTHE4_COMMON_X0Y2
|
||||
#set_property -dict {LOC AN1 } [get_ports {pcie_rx_n[6]}] ;# MGTHRXN1_226 GTHE4_CHANNEL_X0Y9 / GTHE4_COMMON_X0Y2
|
||||
#set_property -dict {LOC AN6 } [get_ports {pcie_tx_p[6]}] ;# MGTHTXP1_226 GTHE4_CHANNEL_X0Y9 / GTHE4_COMMON_X0Y2
|
||||
#set_property -dict {LOC AN5 } [get_ports {pcie_tx_n[6]}] ;# MGTHTXN1_226 GTHE4_CHANNEL_X0Y9 / GTHE4_COMMON_X0Y2
|
||||
#set_property -dict {LOC AP4 } [get_ports {pcie_rx_p[7]}] ;# MGTHRXP0_226 GTHE4_CHANNEL_X0Y8 / GTHE4_COMMON_X0Y2
|
||||
#set_property -dict {LOC AP3 } [get_ports {pcie_rx_n[7]}] ;# MGTHRXN0_226 GTHE4_CHANNEL_X0Y8 / GTHE4_COMMON_X0Y2
|
||||
#set_property -dict {LOC AP8 } [get_ports {pcie_tx_p[7]}] ;# MGTHTXP0_226 GTHE4_CHANNEL_X0Y8 / GTHE4_COMMON_X0Y2
|
||||
#set_property -dict {LOC AP7 } [get_ports {pcie_tx_n[7]}] ;# MGTHTXN0_226 GTHE4_CHANNEL_X0Y8 / GTHE4_COMMON_X0Y2
|
||||
#set_property -dict {LOC AR2 } [get_ports {pcie_rx_p[8]}] ;# MGTHRXP3_225 GTHE4_CHANNEL_X0Y7 / GTHE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC AR1 } [get_ports {pcie_rx_n[8]}] ;# MGTHRXN3_225 GTHE4_CHANNEL_X0Y7 / GTHE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC AR6 } [get_ports {pcie_tx_p[8]}] ;# MGTHTXP3_225 GTHE4_CHANNEL_X0Y7 / GTHE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC AR5 } [get_ports {pcie_tx_n[8]}] ;# MGTHTXN3_225 GTHE4_CHANNEL_X0Y7 / GTHE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC AT4 } [get_ports {pcie_rx_p[9]}] ;# MGTHRXP2_225 GTHE4_CHANNEL_X0Y6 / GTHE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC AT3 } [get_ports {pcie_rx_n[9]}] ;# MGTHRXN2_225 GTHE4_CHANNEL_X0Y6 / GTHE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC AT8 } [get_ports {pcie_tx_p[9]}] ;# MGTHTXP2_225 GTHE4_CHANNEL_X0Y6 / GTHE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC AT7 } [get_ports {pcie_tx_n[9]}] ;# MGTHTXN2_225 GTHE4_CHANNEL_X0Y6 / GTHE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC AU2 } [get_ports {pcie_rx_p[10]}] ;# MGTHRXP1_225 GTHE4_CHANNEL_X0Y5 / GTHE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC AU1 } [get_ports {pcie_rx_n[10]}] ;# MGTHRXN1_225 GTHE4_CHANNEL_X0Y5 / GTHE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC AU6 } [get_ports {pcie_tx_p[10]}] ;# MGTHTXP1_225 GTHE4_CHANNEL_X0Y5 / GTHE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC AU5 } [get_ports {pcie_tx_n[10]}] ;# MGTHTXN1_225 GTHE4_CHANNEL_X0Y5 / GTHE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC AV4 } [get_ports {pcie_rx_p[11]}] ;# MGTHRXP0_225 GTHE4_CHANNEL_X0Y4 / GTHE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC AV3 } [get_ports {pcie_rx_n[11]}] ;# MGTHRXN0_225 GTHE4_CHANNEL_X0Y4 / GTHE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC AV8 } [get_ports {pcie_tx_p[11]}] ;# MGTHTXP0_225 GTHE4_CHANNEL_X0Y4 / GTHE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC AV7 } [get_ports {pcie_tx_n[11]}] ;# MGTHTXN0_225 GTHE4_CHANNEL_X0Y4 / GTHE4_COMMON_X0Y1
|
||||
#set_property -dict {LOC AW2 } [get_ports {pcie_rx_p[12]}] ;# MGTHRXP3_224 GTHE4_CHANNEL_X0Y3 / GTHE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AW1 } [get_ports {pcie_rx_n[12]}] ;# MGTHRXN3_224 GTHE4_CHANNEL_X0Y3 / GTHE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AW6 } [get_ports {pcie_tx_p[12]}] ;# MGTHTXP3_224 GTHE4_CHANNEL_X0Y3 / GTHE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AW5 } [get_ports {pcie_tx_n[12]}] ;# MGTHTXN3_224 GTHE4_CHANNEL_X0Y3 / GTHE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AY4 } [get_ports {pcie_rx_p[13]}] ;# MGTHRXP2_224 GTHE4_CHANNEL_X0Y2 / GTHE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AY3 } [get_ports {pcie_rx_n[13]}] ;# MGTHRXN2_224 GTHE4_CHANNEL_X0Y2 / GTHE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AY8 } [get_ports {pcie_tx_p[13]}] ;# MGTHTXP2_224 GTHE4_CHANNEL_X0Y2 / GTHE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AY7 } [get_ports {pcie_tx_n[13]}] ;# MGTHTXN2_224 GTHE4_CHANNEL_X0Y2 / GTHE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC BA2 } [get_ports {pcie_rx_p[14]}] ;# MGTHRXP1_224 GTHE4_CHANNEL_X0Y1 / GTHE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC BA1 } [get_ports {pcie_rx_n[14]}] ;# MGTHRXN1_224 GTHE4_CHANNEL_X0Y1 / GTHE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC BA6 } [get_ports {pcie_tx_p[14]}] ;# MGTHTXP1_224 GTHE4_CHANNEL_X0Y1 / GTHE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC BA5 } [get_ports {pcie_tx_n[14]}] ;# MGTHTXN1_224 GTHE4_CHANNEL_X0Y1 / GTHE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC BB4 } [get_ports {pcie_rx_p[15]}] ;# MGTHRXP0_224 GTHE4_CHANNEL_X0Y0 / GTHE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC BB3 } [get_ports {pcie_rx_n[15]}] ;# MGTHRXN0_224 GTHE4_CHANNEL_X0Y0 / GTHE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC BB8 } [get_ports {pcie_tx_p[15]}] ;# MGTHTXP0_224 GTHE4_CHANNEL_X0Y0 / GTHE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC BB7 } [get_ports {pcie_tx_n[15]}] ;# MGTHTXN0_224 GTHE4_CHANNEL_X0Y0 / GTHE4_COMMON_X0Y0
|
||||
#set_property -dict {LOC AN10} [get_ports {pcie_refclk_p}] ;# MGTREFCLK0P_226
|
||||
#set_property -dict {LOC AN9 } [get_ports {pcie_refclk_n}] ;# MGTREFCLK0N_226
|
||||
#set_property -dict {LOC G1 IOSTANDARD LVCMOS33 PULLUP true} [get_ports pcie_rst_n]
|
||||
|
||||
# 100 MHz MGT reference clock
|
||||
#create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_refclk_p]
|
||||
|
||||
#set_false_path -from [get_ports {pcie_rst_n}]
|
||||
#set_input_delay 0 [get_ports {pcie_rst_n}]
|
||||
|
||||
# DDR4 C0
|
||||
# 5x K4A8G165WB-BCTD / MT40A512M16HA-075E
|
||||
#set_property -dict {LOC AY22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}]
|
||||
#set_property -dict {LOC AY23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}]
|
||||
#set_property -dict {LOC AV23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}]
|
||||
#set_property -dict {LOC AY24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}]
|
||||
#set_property -dict {LOC AK23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}]
|
||||
#set_property -dict {LOC AV21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}]
|
||||
#set_property -dict {LOC AV22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}]
|
||||
#set_property -dict {LOC AT24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}]
|
||||
#set_property -dict {LOC AW24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}]
|
||||
#set_property -dict {LOC AY21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}]
|
||||
#set_property -dict {LOC AT22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}]
|
||||
#set_property -dict {LOC AP23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}]
|
||||
#set_property -dict {LOC BA21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}]
|
||||
#set_property -dict {LOC AU24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}]
|
||||
#set_property -dict {LOC AL22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}]
|
||||
#set_property -dict {LOC BB22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}]
|
||||
#set_property -dict {LOC BB25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}]
|
||||
#set_property -dict {LOC AW21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}]
|
||||
#set_property -dict {LOC AW23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}]
|
||||
#set_property -dict {LOC BA22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}]
|
||||
#set_property -dict {LOC BB23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}]
|
||||
#set_property -dict {LOC BA24 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t}]
|
||||
#set_property -dict {LOC BB24 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c}]
|
||||
#set_property -dict {LOC AL21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke}]
|
||||
#set_property -dict {LOC BA25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n}]
|
||||
#set_property -dict {LOC AR21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}]
|
||||
#set_property -dict {LOC AT21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt}]
|
||||
#set_property -dict {LOC AK17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}]
|
||||
#set_property -dict {LOC BB20 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_reset_n}]
|
||||
#set_property -dict {LOC AV20 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_alert_n}]
|
||||
#set_property -dict {LOC AU20 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_ten}]
|
||||
|
||||
#set_property -dict {LOC AL17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}]
|
||||
#set_property -dict {LOC AJ16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}]
|
||||
#set_property -dict {LOC AK19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}]
|
||||
#set_property -dict {LOC AK16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}]
|
||||
#set_property -dict {LOC AL19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}]
|
||||
#set_property -dict {LOC AH16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}]
|
||||
#set_property -dict {LOC AM17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}]
|
||||
#set_property -dict {LOC AH17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}]
|
||||
#set_property -dict {LOC AL24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}]
|
||||
#set_property -dict {LOC AH21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}]
|
||||
#set_property -dict {LOC AK24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}]
|
||||
#set_property -dict {LOC AJ24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}]
|
||||
#set_property -dict {LOC AK21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}]
|
||||
#set_property -dict {LOC AH22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}]
|
||||
#set_property -dict {LOC AJ21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}]
|
||||
#set_property -dict {LOC AJ23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}]
|
||||
#set_property -dict {LOC BA14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}]
|
||||
#set_property -dict {LOC BB13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}]
|
||||
#set_property -dict {LOC AY13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}]
|
||||
#set_property -dict {LOC BB14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}]
|
||||
#set_property -dict {LOC AY14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}]
|
||||
#set_property -dict {LOC BB15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}]
|
||||
#set_property -dict {LOC BA15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}]
|
||||
#set_property -dict {LOC BB12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}]
|
||||
#set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}]
|
||||
#set_property -dict {LOC AW13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}]
|
||||
#set_property -dict {LOC AU15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}]
|
||||
#set_property -dict {LOC AU13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}]
|
||||
#set_property -dict {LOC AT16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}]
|
||||
#set_property -dict {LOC AW14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}]
|
||||
#set_property -dict {LOC AU14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}]
|
||||
#set_property -dict {LOC AV13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}]
|
||||
#set_property -dict {LOC BB18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}]
|
||||
#set_property -dict {LOC AY18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}]
|
||||
#set_property -dict {LOC BA19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}]
|
||||
#set_property -dict {LOC AW19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}]
|
||||
#set_property -dict {LOC BB17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}]
|
||||
#set_property -dict {LOC AW18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}]
|
||||
#set_property -dict {LOC BB19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}]
|
||||
#set_property -dict {LOC AY19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}]
|
||||
#set_property -dict {LOC AV17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}]
|
||||
#set_property -dict {LOC AT19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}]
|
||||
#set_property -dict {LOC AU18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}]
|
||||
#set_property -dict {LOC AU19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}]
|
||||
#set_property -dict {LOC AU17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}]
|
||||
#set_property -dict {LOC AR19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}]
|
||||
#set_property -dict {LOC AV18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}]
|
||||
#set_property -dict {LOC AR18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}]
|
||||
#set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}]
|
||||
#set_property -dict {LOC AM20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}]
|
||||
#set_property -dict {LOC AN18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}]
|
||||
#set_property -dict {LOC AN20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}]
|
||||
#set_property -dict {LOC AP16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}]
|
||||
#set_property -dict {LOC AL20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}]
|
||||
#set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}]
|
||||
#set_property -dict {LOC AP20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}]
|
||||
#set_property -dict {LOC AR23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}]
|
||||
#set_property -dict {LOC AM23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}]
|
||||
#set_property -dict {LOC AR24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}]
|
||||
#set_property -dict {LOC AM24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}]
|
||||
#set_property -dict {LOC AR22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}]
|
||||
#set_property -dict {LOC AN22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}]
|
||||
#set_property -dict {LOC AP24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}]
|
||||
#set_property -dict {LOC AM22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}]
|
||||
#set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}]
|
||||
#set_property -dict {LOC AR12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}]
|
||||
#set_property -dict {LOC AP15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}]
|
||||
#set_property -dict {LOC AR13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}]
|
||||
#set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}]
|
||||
#set_property -dict {LOC AT12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}]
|
||||
#set_property -dict {LOC AP14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}]
|
||||
#set_property -dict {LOC AP13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}]
|
||||
#set_property -dict {LOC AJ19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}]
|
||||
#set_property -dict {LOC AJ18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}]
|
||||
#set_property -dict {LOC AH20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}]
|
||||
#set_property -dict {LOC AJ20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}]
|
||||
#set_property -dict {LOC AY12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}]
|
||||
#set_property -dict {LOC BA12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}]
|
||||
#set_property -dict {LOC AU12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}]
|
||||
#set_property -dict {LOC AV12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}]
|
||||
#set_property -dict {LOC AY17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}]
|
||||
#set_property -dict {LOC BA17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}]
|
||||
#set_property -dict {LOC AR17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}]
|
||||
#set_property -dict {LOC AT17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}]
|
||||
#set_property -dict {LOC AM19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}]
|
||||
#set_property -dict {LOC AM18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}]
|
||||
#set_property -dict {LOC AN21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}]
|
||||
#set_property -dict {LOC AP21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}]
|
||||
#set_property -dict {LOC AN13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}]
|
||||
#set_property -dict {LOC AN12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}]
|
||||
#set_property -dict {LOC AK18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[0]}]
|
||||
#set_property -dict {LOC AK22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[1]}]
|
||||
#set_property -dict {LOC AY16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[2]}]
|
||||
#set_property -dict {LOC AV15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[3]}]
|
||||
#set_property -dict {LOC BA20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[4]}]
|
||||
#set_property -dict {LOC AT20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[5]}]
|
||||
#set_property -dict {LOC AP19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[6]}]
|
||||
#set_property -dict {LOC AN23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[7]}]
|
||||
#set_property -dict {LOC AR14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[8]}]
|
||||
|
||||
# DDR4 C1
|
||||
# 5x K4A8G165WB-BCTD / MT40A512M16HA-075E
|
||||
#set_property -dict {LOC AT30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}]
|
||||
#set_property -dict {LOC AR29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}]
|
||||
#set_property -dict {LOC AP30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}]
|
||||
#set_property -dict {LOC AR32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}]
|
||||
#set_property -dict {LOC AU30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}]
|
||||
#set_property -dict {LOC AP28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}]
|
||||
#set_property -dict {LOC AW31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}]
|
||||
#set_property -dict {LOC AM30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}]
|
||||
#set_property -dict {LOC AR33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}]
|
||||
#set_property -dict {LOC AN28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}]
|
||||
#set_property -dict {LOC AV31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}]
|
||||
#set_property -dict {LOC AP29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}]
|
||||
#set_property -dict {LOC AR31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}]
|
||||
#set_property -dict {LOC AN30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}]
|
||||
#set_property -dict {LOC AN32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}]
|
||||
#set_property -dict {LOC AV32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}]
|
||||
#set_property -dict {LOC BA34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}]
|
||||
#set_property -dict {LOC AP34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}]
|
||||
#set_property -dict {LOC AT31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}]
|
||||
#set_property -dict {LOC AP33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}]
|
||||
#set_property -dict {LOC AV33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}]
|
||||
#set_property -dict {LOC AT34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t}]
|
||||
#set_property -dict {LOC AU34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c}]
|
||||
#set_property -dict {LOC AP31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke}]
|
||||
#set_property -dict {LOC AR34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n}]
|
||||
#set_property -dict {LOC AU33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}]
|
||||
#set_property -dict {LOC AN31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt}]
|
||||
#set_property -dict {LOC AW26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}]
|
||||
#set_property -dict {LOC AV25 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}]
|
||||
#set_property -dict {LOC BA31 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_alert_n}]
|
||||
#set_property -dict {LOC AT27 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_ten}]
|
||||
|
||||
#set_property -dict {LOC AV41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}]
|
||||
#set_property -dict {LOC BB39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}]
|
||||
#set_property -dict {LOC AY42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}]
|
||||
#set_property -dict {LOC BA40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}]
|
||||
#set_property -dict {LOC AV42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}]
|
||||
#set_property -dict {LOC BA39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}]
|
||||
#set_property -dict {LOC AW41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}]
|
||||
#set_property -dict {LOC BB40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}]
|
||||
#set_property -dict {LOC AV38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}]
|
||||
#set_property -dict {LOC BA37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}]
|
||||
#set_property -dict {LOC AW38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}]
|
||||
#set_property -dict {LOC AV37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}]
|
||||
#set_property -dict {LOC AU37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}]
|
||||
#set_property -dict {LOC AW36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}]
|
||||
#set_property -dict {LOC BB38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}]
|
||||
#set_property -dict {LOC AV36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}]
|
||||
#set_property -dict {LOC BB34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}]
|
||||
#set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}]
|
||||
#set_property -dict {LOC BB33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}]
|
||||
#set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}]
|
||||
#set_property -dict {LOC BA36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}]
|
||||
#set_property -dict {LOC AW34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}]
|
||||
#set_property -dict {LOC BB37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}]
|
||||
#set_property -dict {LOC AW33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}]
|
||||
#set_property -dict {LOC BA32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}]
|
||||
#set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}]
|
||||
#set_property -dict {LOC BB29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}]
|
||||
#set_property -dict {LOC AY29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}]
|
||||
#set_property -dict {LOC BB32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}]
|
||||
#set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}]
|
||||
#set_property -dict {LOC BB28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}]
|
||||
#set_property -dict {LOC AW29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}]
|
||||
#set_property -dict {LOC AY28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}]
|
||||
#set_property -dict {LOC AV26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}]
|
||||
#set_property -dict {LOC BA26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}]
|
||||
#set_property -dict {LOC AV27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}]
|
||||
#set_property -dict {LOC AW28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}]
|
||||
#set_property -dict {LOC AV28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}]
|
||||
#set_property -dict {LOC AY26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}]
|
||||
#set_property -dict {LOC AY27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}]
|
||||
#set_property -dict {LOC AU27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}]
|
||||
#set_property -dict {LOC AP25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}]
|
||||
#set_property -dict {LOC AR27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}]
|
||||
#set_property -dict {LOC AP26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}]
|
||||
#set_property -dict {LOC AU28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}]
|
||||
#set_property -dict {LOC AN25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}]
|
||||
#set_property -dict {LOC AR26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}]
|
||||
#set_property -dict {LOC AR28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}]
|
||||
#set_property -dict {LOC AM29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}]
|
||||
#set_property -dict {LOC AK30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}]
|
||||
#set_property -dict {LOC AL29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}]
|
||||
#set_property -dict {LOC AH30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}]
|
||||
#set_property -dict {LOC AM28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}]
|
||||
#set_property -dict {LOC AJ30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}]
|
||||
#set_property -dict {LOC AK29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}]
|
||||
#set_property -dict {LOC AJ29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}]
|
||||
#set_property -dict {LOC AL25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}]
|
||||
#set_property -dict {LOC AH26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}]
|
||||
#set_property -dict {LOC AL27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}]
|
||||
#set_property -dict {LOC AJ25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}]
|
||||
#set_property -dict {LOC AM27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}]
|
||||
#set_property -dict {LOC AH27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}]
|
||||
#set_property -dict {LOC AM25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}]
|
||||
#set_property -dict {LOC AJ26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}]
|
||||
#set_property -dict {LOC AK13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}]
|
||||
#set_property -dict {LOC AJ13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}]
|
||||
#set_property -dict {LOC AL14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}]
|
||||
#set_property -dict {LOC AH13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}]
|
||||
#set_property -dict {LOC AK14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}]
|
||||
#set_property -dict {LOC AH12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}]
|
||||
#set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}]
|
||||
#set_property -dict {LOC AK12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}]
|
||||
#set_property -dict {LOC AY41 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}]
|
||||
#set_property -dict {LOC BA41 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}]
|
||||
#set_property -dict {LOC AY37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}]
|
||||
#set_property -dict {LOC AY38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}]
|
||||
#set_property -dict {LOC BA35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}]
|
||||
#set_property -dict {LOC BB35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}]
|
||||
#set_property -dict {LOC BA30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}]
|
||||
#set_property -dict {LOC BB30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}]
|
||||
#set_property -dict {LOC BA27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}]
|
||||
#set_property -dict {LOC BB27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}]
|
||||
#set_property -dict {LOC AT29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}]
|
||||
#set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}]
|
||||
#set_property -dict {LOC AJ28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}]
|
||||
#set_property -dict {LOC AK28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}]
|
||||
#set_property -dict {LOC AN26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}]
|
||||
#set_property -dict {LOC AN27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}]
|
||||
#set_property -dict {LOC AJ15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}]
|
||||
#set_property -dict {LOC AJ14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}]
|
||||
#set_property -dict {LOC AW39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[0]}]
|
||||
#set_property -dict {LOC AU35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[1]}]
|
||||
#set_property -dict {LOC AY34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[2]}]
|
||||
#set_property -dict {LOC AY31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[3]}]
|
||||
#set_property -dict {LOC AU25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[4]}]
|
||||
#set_property -dict {LOC AT26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[5]}]
|
||||
#set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[6]}]
|
||||
#set_property -dict {LOC AK26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[7]}]
|
||||
#set_property -dict {LOC AM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[8]}]
|
||||
|
||||
# DDR4 C2
|
||||
# 5x K4A8G165WB-BCTD / MT40A512M16HA-075E
|
||||
#set_property -dict {LOC J30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}]
|
||||
#set_property -dict {LOC J29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}]
|
||||
#set_property -dict {LOC G32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}]
|
||||
#set_property -dict {LOC F31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}]
|
||||
#set_property -dict {LOC H29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}]
|
||||
#set_property -dict {LOC F28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}]
|
||||
#set_property -dict {LOC J28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}]
|
||||
#set_property -dict {LOC H32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}]
|
||||
#set_property -dict {LOC L29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}]
|
||||
#set_property -dict {LOC H31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}]
|
||||
#set_property -dict {LOC F30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}]
|
||||
#set_property -dict {LOC J32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}]
|
||||
#set_property -dict {LOC B28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}]
|
||||
#set_property -dict {LOC K32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}]
|
||||
#set_property -dict {LOC F29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}]
|
||||
#set_property -dict {LOC D29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}]
|
||||
#set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}]
|
||||
#set_property -dict {LOC G31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}]
|
||||
#set_property -dict {LOC H30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}]
|
||||
#set_property -dict {LOC E31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}]
|
||||
#set_property -dict {LOC D30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[1]}]
|
||||
#set_property -dict {LOC E32 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t}]
|
||||
#set_property -dict {LOC D32 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c}]
|
||||
#set_property -dict {LOC E30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke}]
|
||||
#set_property -dict {LOC C31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n}]
|
||||
#set_property -dict {LOC E28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}]
|
||||
#set_property -dict {LOC D28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt}]
|
||||
#set_property -dict {LOC J18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}]
|
||||
#set_property -dict {LOC L19 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}]
|
||||
#set_property -dict {LOC F19 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_alert_n}]
|
||||
#set_property -dict {LOC E15 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_ten}]
|
||||
|
||||
#set_property -dict {LOC G38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}]
|
||||
#set_property -dict {LOC D42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}]
|
||||
#set_property -dict {LOC F39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}]
|
||||
#set_property -dict {LOC G41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}]
|
||||
#set_property -dict {LOC F38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}]
|
||||
#set_property -dict {LOC G42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}]
|
||||
#set_property -dict {LOC G39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}]
|
||||
#set_property -dict {LOC E42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}]
|
||||
#set_property -dict {LOC C39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}]
|
||||
#set_property -dict {LOC B41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}]
|
||||
#set_property -dict {LOC B39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}]
|
||||
#set_property -dict {LOC C41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}]
|
||||
#set_property -dict {LOC B38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}]
|
||||
#set_property -dict {LOC C42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}]
|
||||
#set_property -dict {LOC A38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}]
|
||||
#set_property -dict {LOC C40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}]
|
||||
#set_property -dict {LOC AT36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}]
|
||||
#set_property -dict {LOC AR38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}]
|
||||
#set_property -dict {LOC AP36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}]
|
||||
#set_property -dict {LOC AR37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}]
|
||||
#set_property -dict {LOC AR36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}]
|
||||
#set_property -dict {LOC AP39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}]
|
||||
#set_property -dict {LOC AP37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}]
|
||||
#set_property -dict {LOC AP40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}]
|
||||
#set_property -dict {LOC N24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}]
|
||||
#set_property -dict {LOC M26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}]
|
||||
#set_property -dict {LOC N26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}]
|
||||
#set_property -dict {LOC L25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}]
|
||||
#set_property -dict {LOC N25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}]
|
||||
#set_property -dict {LOC L26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}]
|
||||
#set_property -dict {LOC M23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}]
|
||||
#set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}]
|
||||
#set_property -dict {LOC AP41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}]
|
||||
#set_property -dict {LOC AT41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}]
|
||||
#set_property -dict {LOC AP42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}]
|
||||
#set_property -dict {LOC AU40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}]
|
||||
#set_property -dict {LOC AR41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}]
|
||||
#set_property -dict {LOC AV40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}]
|
||||
#set_property -dict {LOC AR42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}]
|
||||
#set_property -dict {LOC AT40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}]
|
||||
#set_property -dict {LOC K28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}]
|
||||
#set_property -dict {LOC K31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}]
|
||||
#set_property -dict {LOC P28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}]
|
||||
#set_property -dict {LOC N28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}]
|
||||
#set_property -dict {LOC M27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}]
|
||||
#set_property -dict {LOC L31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}]
|
||||
#set_property -dict {LOC N27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}]
|
||||
#set_property -dict {LOC L28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}]
|
||||
#set_property -dict {LOC D34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}]
|
||||
#set_property -dict {LOC A34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}]
|
||||
#set_property -dict {LOC C34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}]
|
||||
#set_property -dict {LOC A35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}]
|
||||
#set_property -dict {LOC C36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}]
|
||||
#set_property -dict {LOC A36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}]
|
||||
#set_property -dict {LOC C37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}]
|
||||
#set_property -dict {LOC B34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}]
|
||||
#set_property -dict {LOC B29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}]
|
||||
#set_property -dict {LOC B33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}]
|
||||
#set_property -dict {LOC A29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}]
|
||||
#set_property -dict {LOC B32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}]
|
||||
#set_property -dict {LOC A28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}]
|
||||
#set_property -dict {LOC A33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}]
|
||||
#set_property -dict {LOC C29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}]
|
||||
#set_property -dict {LOC B31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}]
|
||||
#set_property -dict {LOC E37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}]
|
||||
#set_property -dict {LOC E36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}]
|
||||
#set_property -dict {LOC F36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}]
|
||||
#set_property -dict {LOC D37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}]
|
||||
#set_property -dict {LOC E38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}]
|
||||
#set_property -dict {LOC F33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}]
|
||||
#set_property -dict {LOC G36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}]
|
||||
#set_property -dict {LOC E33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}]
|
||||
#set_property -dict {LOC F41 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}]
|
||||
#set_property -dict {LOC E41 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}]
|
||||
#set_property -dict {LOC A39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}]
|
||||
#set_property -dict {LOC A40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}]
|
||||
#set_property -dict {LOC AT37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}]
|
||||
#set_property -dict {LOC AU38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}]
|
||||
#set_property -dict {LOC M24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}]
|
||||
#set_property -dict {LOC L24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}]
|
||||
#set_property -dict {LOC AT42 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}]
|
||||
#set_property -dict {LOC AU42 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}]
|
||||
#set_property -dict {LOC L30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}]
|
||||
#set_property -dict {LOC K30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}]
|
||||
#set_property -dict {LOC B36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}]
|
||||
#set_property -dict {LOC B37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}]
|
||||
#set_property -dict {LOC A30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}]
|
||||
#set_property -dict {LOC A31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}]
|
||||
#set_property -dict {LOC F35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}]
|
||||
#set_property -dict {LOC E35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}]
|
||||
#set_property -dict {LOC G40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[0]}]
|
||||
#set_property -dict {LOC D39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[1]}]
|
||||
#set_property -dict {LOC AP38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[2]}]
|
||||
#set_property -dict {LOC P23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[3]}]
|
||||
#set_property -dict {LOC AT39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[4]}]
|
||||
#set_property -dict {LOC M28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[5]}]
|
||||
#set_property -dict {LOC D35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[6]}]
|
||||
#set_property -dict {LOC C30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[7]}]
|
||||
#set_property -dict {LOC G34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[8]}]
|
||||
|
||||
# DDR4 C3
|
||||
# 5x K4A8G165WB-BCTD / MT40A512M16HA-075E
|
||||
#set_property -dict {LOC F23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[0]}]
|
||||
#set_property -dict {LOC G23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[1]}]
|
||||
#set_property -dict {LOC H24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[2]}]
|
||||
#set_property -dict {LOC F25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[3]}]
|
||||
#set_property -dict {LOC F26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[4]}]
|
||||
#set_property -dict {LOC F24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[5]}]
|
||||
#set_property -dict {LOC K26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[6]}]
|
||||
#set_property -dict {LOC G27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[7]}]
|
||||
#set_property -dict {LOC J27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[8]}]
|
||||
#set_property -dict {LOC G24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[9]}]
|
||||
#set_property -dict {LOC E25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[10]}]
|
||||
#set_property -dict {LOC H27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[11]}]
|
||||
#set_property -dict {LOC E23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[12]}]
|
||||
#set_property -dict {LOC G26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[13]}]
|
||||
#set_property -dict {LOC J23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[14]}]
|
||||
#set_property -dict {LOC D23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[15]}]
|
||||
#set_property -dict {LOC B27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[16]}]
|
||||
#set_property -dict {LOC J25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[0]}]
|
||||
#set_property -dict {LOC K25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[1]}]
|
||||
#set_property -dict {LOC J24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[0]}]
|
||||
#set_property -dict {LOC D25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[1]}]
|
||||
#set_property -dict {LOC E27 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t}]
|
||||
#set_property -dict {LOC D27 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c}]
|
||||
#set_property -dict {LOC E26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke}]
|
||||
#set_property -dict {LOC H25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n}]
|
||||
#set_property -dict {LOC D24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_act_n}]
|
||||
#set_property -dict {LOC B22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt}]
|
||||
#set_property -dict {LOC A14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_par}]
|
||||
#set_property -dict {LOC M16 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c3_reset_n}]
|
||||
#set_property -dict {LOC F20 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c3_alert_n}]
|
||||
#set_property -dict {LOC J17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c3_ten}]
|
||||
|
||||
#set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[0]}]
|
||||
#set_property -dict {LOC G17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[1]}]
|
||||
#set_property -dict {LOC F16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[2]}]
|
||||
#set_property -dict {LOC G16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[3]}]
|
||||
#set_property -dict {LOC E16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[4]}]
|
||||
#set_property -dict {LOC H17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[5]}]
|
||||
#set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[6]}]
|
||||
#set_property -dict {LOC F18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[7]}]
|
||||
#set_property -dict {LOC N12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[8]}]
|
||||
#set_property -dict {LOC P15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[9]}]
|
||||
#set_property -dict {LOC M13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[10]}]
|
||||
#set_property -dict {LOC P12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[11]}]
|
||||
#set_property -dict {LOC M12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[12]}]
|
||||
#set_property -dict {LOC N15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[13]}]
|
||||
#set_property -dict {LOC M14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[14]}]
|
||||
#set_property -dict {LOC P13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[15]}]
|
||||
#set_property -dict {LOC C17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[16]}]
|
||||
#set_property -dict {LOC C15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[17]}]
|
||||
#set_property -dict {LOC A16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[18]}]
|
||||
#set_property -dict {LOC A15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[19]}]
|
||||
#set_property -dict {LOC B17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[20]}]
|
||||
#set_property -dict {LOC D15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[21]}]
|
||||
#set_property -dict {LOC D18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[22]}]
|
||||
#set_property -dict {LOC D17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[23]}]
|
||||
#set_property -dict {LOC J14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[24]}]
|
||||
#set_property -dict {LOC L16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[25]}]
|
||||
#set_property -dict {LOC H15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[26]}]
|
||||
#set_property -dict {LOC H14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[27]}]
|
||||
#set_property -dict {LOC J15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[28]}]
|
||||
#set_property -dict {LOC K16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[29]}]
|
||||
#set_property -dict {LOC K15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[30]}]
|
||||
#set_property -dict {LOC H16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[31]}]
|
||||
#set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[32]}]
|
||||
#set_property -dict {LOC H19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[33]}]
|
||||
#set_property -dict {LOC J20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[34]}]
|
||||
#set_property -dict {LOC J19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[35]}]
|
||||
#set_property -dict {LOC K20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[36]}]
|
||||
#set_property -dict {LOC K18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[37]}]
|
||||
#set_property -dict {LOC H20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[38]}]
|
||||
#set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[39]}]
|
||||
#set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[40]}]
|
||||
#set_property -dict {LOC B19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[41]}]
|
||||
#set_property -dict {LOC A21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[42]}]
|
||||
#set_property -dict {LOC A19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[43]}]
|
||||
#set_property -dict {LOC B21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[44]}]
|
||||
#set_property -dict {LOC D19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[45]}]
|
||||
#set_property -dict {LOC C21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[46]}]
|
||||
#set_property -dict {LOC A20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[47]}]
|
||||
#set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[48]}]
|
||||
#set_property -dict {LOC N22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[49]}]
|
||||
#set_property -dict {LOC P20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[50]}]
|
||||
#set_property -dict {LOC N21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[51]}]
|
||||
#set_property -dict {LOC P19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[52]}]
|
||||
#set_property -dict {LOC N20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[53]}]
|
||||
#set_property -dict {LOC P18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[54]}]
|
||||
#set_property -dict {LOC P22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[55]}]
|
||||
#set_property -dict {LOC C25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[56]}]
|
||||
#set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[57]}]
|
||||
#set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[58]}]
|
||||
#set_property -dict {LOC A26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[59]}]
|
||||
#set_property -dict {LOC C26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[60]}]
|
||||
#set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[61]}]
|
||||
#set_property -dict {LOC A24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[62]}]
|
||||
#set_property -dict {LOC A25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[63]}]
|
||||
#set_property -dict {LOC H22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[64]}]
|
||||
#set_property -dict {LOC E21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[65]}]
|
||||
#set_property -dict {LOC G21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[66]}]
|
||||
#set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[67]}]
|
||||
#set_property -dict {LOC H21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[68]}]
|
||||
#set_property -dict {LOC E20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[69]}]
|
||||
#set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[70]}]
|
||||
#set_property -dict {LOC D22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[71]}]
|
||||
#set_property -dict {LOC G14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[0]}]
|
||||
#set_property -dict {LOC F14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[0]}]
|
||||
#set_property -dict {LOC P14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[1]}]
|
||||
#set_property -dict {LOC N14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[1]}]
|
||||
#set_property -dict {LOC C16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[2]}]
|
||||
#set_property -dict {LOC B16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[2]}]
|
||||
#set_property -dict {LOC L15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[3]}]
|
||||
#set_property -dict {LOC L14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[3]}]
|
||||
#set_property -dict {LOC K22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[4]}]
|
||||
#set_property -dict {LOC J22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[4]}]
|
||||
#set_property -dict {LOC C20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[5]}]
|
||||
#set_property -dict {LOC C19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[5]}]
|
||||
#set_property -dict {LOC M21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[6]}]
|
||||
#set_property -dict {LOC L21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[6]}]
|
||||
#set_property -dict {LOC B23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[7]}]
|
||||
#set_property -dict {LOC B24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[7]}]
|
||||
#set_property -dict {LOC G19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[8]}]
|
||||
#set_property -dict {LOC G18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[8]}]
|
||||
#set_property -dict {LOC F15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[0]}]
|
||||
#set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[1]}]
|
||||
#set_property -dict {LOC B14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[2]}]
|
||||
#set_property -dict {LOC K17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[3]}]
|
||||
#set_property -dict {LOC L20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[4]}]
|
||||
#set_property -dict {LOC B18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[5]}]
|
||||
#set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[6]}]
|
||||
#set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[7]}]
|
||||
#set_property -dict {LOC F21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[8]}]
|
||||
84
example/fb2CG/fpga/fpga/Makefile
Normal file
84
example/fb2CG/fpga/fpga/Makefile
Normal file
@@ -0,0 +1,84 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcku15p-ffve1760-2-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = kintexuplus
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = ../rtl/fpga.sv
|
||||
SYN_FILES += ../rtl/fpga_core.sv
|
||||
SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f
|
||||
SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f
|
||||
SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv
|
||||
SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv
|
||||
SYN_FILES += ../lib/taxi/rtl/io/taxi_led_sreg.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga.xdc
|
||||
XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_161.tcl
|
||||
|
||||
# Configuration
|
||||
# CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
%.mcs %.prm: %.bit
|
||||
echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(PROJECT).mcs $(PROJECT).prm
|
||||
echo "open_hw_manager" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu512-spi-x1_x2_x4}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
84
example/fb2CG/fpga/fpga_10g/Makefile
Normal file
84
example/fb2CG/fpga/fpga_10g/Makefile
Normal file
@@ -0,0 +1,84 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcku15p-ffve1760-2-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = kintexuplus
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = ../rtl/fpga.sv
|
||||
SYN_FILES += ../rtl/fpga_core.sv
|
||||
SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f
|
||||
SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f
|
||||
SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv
|
||||
SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv
|
||||
SYN_FILES += ../lib/taxi/rtl/io/taxi_led_sreg.sv
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga.xdc
|
||||
XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_161.tcl
|
||||
|
||||
# Configuration
|
||||
# CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
%.mcs %.prm: %.bit
|
||||
echo "write_cfgmem -force -format mcs -size 64 -interface SPIx4 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(PROJECT).mcs $(PROJECT).prm
|
||||
echo "open_hw_manager" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu512-spi-x1_x2_x4}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
1
example/fb2CG/fpga/lib/taxi
Symbolic link
1
example/fb2CG/fpga/lib/taxi
Symbolic link
@@ -0,0 +1 @@
|
||||
../../../../
|
||||
232
example/fb2CG/fpga/rtl/fpga.sv
Normal file
232
example/fb2CG/fpga/rtl/fpga.sv
Normal file
@@ -0,0 +1,232 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA top-level module
|
||||
*/
|
||||
module fpga #
|
||||
(
|
||||
parameter logic SIM = 1'b0,
|
||||
parameter string VENDOR = "XILINX",
|
||||
parameter string FAMILY = "kintexuplus"
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Clock: 100MHz
|
||||
*/
|
||||
input wire logic init_clk,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
output wire logic led_sreg_d,
|
||||
output wire logic led_sreg_ld,
|
||||
output wire logic led_sreg_clk,
|
||||
output wire logic [1:0] led_bmc,
|
||||
output wire logic [1:0] led_exp,
|
||||
|
||||
/*
|
||||
* Board status
|
||||
*/
|
||||
input wire logic [1:0] pg,
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire logic [3:0] qsfp_0_tx_p,
|
||||
output wire logic [3:0] qsfp_0_tx_n,
|
||||
input wire logic [3:0] qsfp_0_rx_p,
|
||||
input wire logic [3:0] qsfp_0_rx_n,
|
||||
input wire logic qsfp_0_mgt_refclk_p,
|
||||
input wire logic qsfp_0_mgt_refclk_n,
|
||||
input wire logic qsfp_0_mod_prsnt_n,
|
||||
output wire logic qsfp_0_reset_n,
|
||||
output wire logic qsfp_0_lp_mode,
|
||||
input wire logic qsfp_0_intr_n,
|
||||
|
||||
output wire logic [3:0] qsfp_1_tx_p,
|
||||
output wire logic [3:0] qsfp_1_tx_n,
|
||||
input wire logic [3:0] qsfp_1_rx_p,
|
||||
input wire logic [3:0] qsfp_1_rx_n,
|
||||
input wire logic qsfp_1_mgt_refclk_p,
|
||||
input wire logic qsfp_1_mgt_refclk_n,
|
||||
input wire logic qsfp_1_mod_prsnt_n,
|
||||
output wire logic qsfp_1_reset_n,
|
||||
output wire logic qsfp_1_lp_mode,
|
||||
input wire logic qsfp_1_intr_n
|
||||
);
|
||||
|
||||
// Clock and reset
|
||||
|
||||
wire init_clk_bufg;
|
||||
|
||||
// Internal 125 MHz clock
|
||||
wire clk_125mhz_mmcm_out;
|
||||
wire clk_125mhz_int;
|
||||
wire rst_125mhz_int;
|
||||
|
||||
wire mmcm_rst = !pg[0] || !pg[1];
|
||||
wire mmcm_locked;
|
||||
wire mmcm_clkfb;
|
||||
|
||||
BUFG
|
||||
init_clk_bufg_inst (
|
||||
.I(init_clk),
|
||||
.O(init_clk_bufg)
|
||||
);
|
||||
|
||||
// MMCM instance
|
||||
MMCME4_BASE #(
|
||||
// 50 MHz input
|
||||
.CLKIN1_PERIOD(20.000),
|
||||
.REF_JITTER1(0.010),
|
||||
// 50 MHz input / 1 = 50 MHz PFD (range 10 MHz to 500 MHz)
|
||||
.DIVCLK_DIVIDE(1),
|
||||
// 50 MHz PFD * 25 = 1250 MHz VCO (range 800 MHz to 1600 MHz)
|
||||
.CLKFBOUT_MULT_F(25),
|
||||
.CLKFBOUT_PHASE(0),
|
||||
// 1250 MHz / 10 = 125 MHz, 0 degrees
|
||||
.CLKOUT0_DIVIDE_F(10),
|
||||
.CLKOUT0_DUTY_CYCLE(0.5),
|
||||
.CLKOUT0_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT1_DIVIDE(10),
|
||||
.CLKOUT1_DUTY_CYCLE(0.5),
|
||||
.CLKOUT1_PHASE(90),
|
||||
// Not used
|
||||
.CLKOUT2_DIVIDE(20),
|
||||
.CLKOUT2_DUTY_CYCLE(0.5),
|
||||
.CLKOUT2_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT3_DIVIDE(4),
|
||||
.CLKOUT3_DUTY_CYCLE(0.5),
|
||||
.CLKOUT3_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.5),
|
||||
.CLKOUT4_PHASE(0),
|
||||
.CLKOUT4_CASCADE("FALSE"),
|
||||
// Not used
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.5),
|
||||
.CLKOUT5_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.5),
|
||||
.CLKOUT6_PHASE(0),
|
||||
|
||||
// optimized bandwidth
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
// don't wait for lock during startup
|
||||
.STARTUP_WAIT("FALSE")
|
||||
)
|
||||
clk_mmcm_inst (
|
||||
// 300 MHz input
|
||||
.CLKIN1(init_clk_bufg),
|
||||
// direct clkfb feeback
|
||||
.CLKFBIN(mmcm_clkfb),
|
||||
.CLKFBOUT(mmcm_clkfb),
|
||||
.CLKFBOUTB(),
|
||||
// 125 MHz, 0 degrees
|
||||
.CLKOUT0(clk_125mhz_mmcm_out),
|
||||
.CLKOUT0B(),
|
||||
// Not used
|
||||
.CLKOUT1(),
|
||||
.CLKOUT1B(),
|
||||
// Not used
|
||||
.CLKOUT2(),
|
||||
.CLKOUT2B(),
|
||||
// Not used
|
||||
.CLKOUT3(),
|
||||
.CLKOUT3B(),
|
||||
// Not used
|
||||
.CLKOUT4(),
|
||||
// Not used
|
||||
.CLKOUT5(),
|
||||
// Not used
|
||||
.CLKOUT6(),
|
||||
// reset input
|
||||
.RST(mmcm_rst),
|
||||
// don't power down
|
||||
.PWRDWN(1'b0),
|
||||
// locked output
|
||||
.LOCKED(mmcm_locked)
|
||||
);
|
||||
|
||||
BUFG
|
||||
clk_125mhz_bufg_inst (
|
||||
.I(clk_125mhz_mmcm_out),
|
||||
.O(clk_125mhz_int)
|
||||
);
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_125mhz_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.rst(~mmcm_locked),
|
||||
.out(rst_125mhz_int)
|
||||
);
|
||||
|
||||
fpga_core #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
* Clock: 125 MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
.clk_125mhz(clk_125mhz_int),
|
||||
.rst_125mhz(rst_125mhz_int),
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
.led_sreg_d(led_sreg_d),
|
||||
.led_sreg_ld(led_sreg_ld),
|
||||
.led_sreg_clk(led_sreg_clk),
|
||||
.led_bmc(led_bmc),
|
||||
.led_exp(led_exp),
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
.qsfp_0_tx_p(qsfp_0_tx_p),
|
||||
.qsfp_0_tx_n(qsfp_0_tx_n),
|
||||
.qsfp_0_rx_p(qsfp_0_rx_p),
|
||||
.qsfp_0_rx_n(qsfp_0_rx_n),
|
||||
.qsfp_0_mgt_refclk_p(qsfp_0_mgt_refclk_p),
|
||||
.qsfp_0_mgt_refclk_n(qsfp_0_mgt_refclk_n),
|
||||
.qsfp_0_mod_prsnt_n(qsfp_0_mod_prsnt_n),
|
||||
.qsfp_0_reset_n(qsfp_0_reset_n),
|
||||
.qsfp_0_lp_mode(qsfp_0_lp_mode),
|
||||
.qsfp_0_intr_n(qsfp_0_intr_n),
|
||||
|
||||
.qsfp_1_tx_p(qsfp_1_tx_p),
|
||||
.qsfp_1_tx_n(qsfp_1_tx_n),
|
||||
.qsfp_1_rx_p(qsfp_1_rx_p),
|
||||
.qsfp_1_rx_n(qsfp_1_rx_n),
|
||||
.qsfp_1_mgt_refclk_p(qsfp_1_mgt_refclk_p),
|
||||
.qsfp_1_mgt_refclk_n(qsfp_1_mgt_refclk_n),
|
||||
.qsfp_1_mod_prsnt_n(qsfp_1_mod_prsnt_n),
|
||||
.qsfp_1_reset_n(qsfp_1_reset_n),
|
||||
.qsfp_1_lp_mode(qsfp_1_lp_mode),
|
||||
.qsfp_1_intr_n(qsfp_1_intr_n)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
409
example/fb2CG/fpga/rtl/fpga_core.sv
Normal file
409
example/fb2CG/fpga/rtl/fpga_core.sv
Normal file
@@ -0,0 +1,409 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA core logic
|
||||
*/
|
||||
module fpga_core #
|
||||
(
|
||||
parameter logic SIM = 1'b0,
|
||||
parameter string VENDOR = "XILINX",
|
||||
parameter string FAMILY = "kintexuplus"
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Clock: 156.25MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
input wire logic clk_125mhz,
|
||||
input wire logic rst_125mhz,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
output wire logic led_sreg_d,
|
||||
output wire logic led_sreg_ld,
|
||||
output wire logic led_sreg_clk,
|
||||
output wire logic [1:0] led_bmc,
|
||||
output wire logic [1:0] led_exp,
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire logic [3:0] qsfp_0_tx_p,
|
||||
output wire logic [3:0] qsfp_0_tx_n,
|
||||
input wire logic [3:0] qsfp_0_rx_p,
|
||||
input wire logic [3:0] qsfp_0_rx_n,
|
||||
input wire logic qsfp_0_mgt_refclk_p,
|
||||
input wire logic qsfp_0_mgt_refclk_n,
|
||||
input wire logic qsfp_0_mod_prsnt_n,
|
||||
output wire logic qsfp_0_reset_n,
|
||||
output wire logic qsfp_0_lp_mode,
|
||||
input wire logic qsfp_0_intr_n,
|
||||
|
||||
output wire logic [3:0] qsfp_1_tx_p,
|
||||
output wire logic [3:0] qsfp_1_tx_n,
|
||||
input wire logic [3:0] qsfp_1_rx_p,
|
||||
input wire logic [3:0] qsfp_1_rx_n,
|
||||
input wire logic qsfp_1_mgt_refclk_p,
|
||||
input wire logic qsfp_1_mgt_refclk_n,
|
||||
input wire logic qsfp_1_mod_prsnt_n,
|
||||
output wire logic qsfp_1_reset_n,
|
||||
output wire logic qsfp_1_lp_mode,
|
||||
input wire logic qsfp_1_intr_n
|
||||
);
|
||||
|
||||
// LED
|
||||
wire [7:0] led_g;
|
||||
wire [7:0] led_r;
|
||||
|
||||
taxi_led_sreg #(
|
||||
.COUNT(8),
|
||||
.INVERT(1),
|
||||
.REVERSE(0),
|
||||
.INTERLEAVE(1),
|
||||
.PRESCALE(63)
|
||||
)
|
||||
led_sreg_driver_inst (
|
||||
.clk(clk_125mhz),
|
||||
.rst(rst_125mhz),
|
||||
|
||||
.led_a(led_r),
|
||||
.led_b(led_g),
|
||||
|
||||
.sreg_d(led_sreg_d),
|
||||
.sreg_ld(led_sreg_ld),
|
||||
.sreg_clk(led_sreg_clk)
|
||||
);
|
||||
|
||||
// QSFP28
|
||||
assign qsfp_0_reset_n = 1'b1;
|
||||
assign qsfp_0_lp_mode = 1'b0;
|
||||
assign qsfp_1_reset_n = 1'b1;
|
||||
assign qsfp_1_lp_mode = 1'b0;
|
||||
|
||||
wire [7:0] qsfp_tx_clk;
|
||||
wire [7:0] qsfp_tx_rst;
|
||||
wire [7:0] qsfp_rx_clk;
|
||||
wire [7:0] qsfp_rx_rst;
|
||||
|
||||
wire [7:0] qsfp_rx_status;
|
||||
|
||||
assign led_g = qsfp_rx_status;
|
||||
assign led_r = '0;
|
||||
assign led_bmc = '0;
|
||||
assign led_exp = '1;
|
||||
|
||||
wire [1:0] qsfp_gtpowergood;
|
||||
|
||||
taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_qsfp_tx[7:0]();
|
||||
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_qsfp_tx_cpl[7:0]();
|
||||
taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_qsfp_rx[7:0]();
|
||||
|
||||
wire [1:0] qsfp_mgt_refclk_p = {qsfp_1_mgt_refclk_p, qsfp_0_mgt_refclk_p};
|
||||
wire [1:0] qsfp_mgt_refclk_n = {qsfp_1_mgt_refclk_n, qsfp_0_mgt_refclk_n};
|
||||
|
||||
wire [1:0] qsfp_mgt_refclk;
|
||||
wire [1:0] qsfp_mgt_refclk_bufg;
|
||||
|
||||
wire [1:0] qsfp_rst;
|
||||
|
||||
for (genvar n = 0; n < 2; n = n + 1) begin : gty_clk
|
||||
|
||||
wire qsfp_mgt_refclk_int;
|
||||
|
||||
if (SIM) begin
|
||||
|
||||
assign qsfp_mgt_refclk[n] = qsfp_mgt_refclk_p[n];
|
||||
assign qsfp_mgt_refclk_int = qsfp_mgt_refclk_p[n];
|
||||
assign qsfp_mgt_refclk_bufg[n] = qsfp_mgt_refclk_int;
|
||||
|
||||
end else begin
|
||||
|
||||
IBUFDS_GTE4 ibufds_gte4_qsfp_mgt_refclk_inst (
|
||||
.I (qsfp_mgt_refclk_p[n]),
|
||||
.IB (qsfp_mgt_refclk_n[n]),
|
||||
.CEB (1'b0),
|
||||
.O (qsfp_mgt_refclk[n]),
|
||||
.ODIV2 (qsfp_mgt_refclk_int)
|
||||
);
|
||||
|
||||
BUFG_GT bufg_gt_qsfp_mgt_refclk_inst (
|
||||
.CE (&qsfp_gtpowergood),
|
||||
.CEMASK (1'b1),
|
||||
.CLR (1'b0),
|
||||
.CLRMASK (1'b1),
|
||||
.DIV (3'd0),
|
||||
.I (qsfp_mgt_refclk_int),
|
||||
.O (qsfp_mgt_refclk_bufg[n])
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
qsfp_sync_reset_inst (
|
||||
.clk(qsfp_mgt_refclk_bufg[n]),
|
||||
.rst(rst_125mhz),
|
||||
.out(qsfp_rst[n])
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
wire [7:0] qsfp_tx_p;
|
||||
wire [7:0] qsfp_tx_n;
|
||||
wire [7:0] qsfp_rx_p = {qsfp_1_rx_p, qsfp_0_rx_p};
|
||||
wire [7:0] qsfp_rx_n = {qsfp_1_rx_n, qsfp_0_rx_n};
|
||||
|
||||
assign qsfp_0_tx_p = qsfp_tx_p[3:0];
|
||||
assign qsfp_0_tx_n = qsfp_tx_n[3:0];
|
||||
assign qsfp_1_tx_p = qsfp_tx_p[7:4];
|
||||
assign qsfp_1_tx_n = qsfp_tx_n[7:4];
|
||||
|
||||
for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
|
||||
|
||||
localparam CLK = n;
|
||||
localparam CNT = 4;
|
||||
|
||||
taxi_eth_mac_25g_us #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
|
||||
.CNT(CNT),
|
||||
|
||||
// GT type
|
||||
.GT_TYPE("GTY"),
|
||||
|
||||
// PHY parameters
|
||||
.PADDING_EN(1'b1),
|
||||
.DIC_EN(1'b1),
|
||||
.MIN_FRAME_LEN(64),
|
||||
.PTP_TS_EN(1'b0),
|
||||
.PTP_TS_FMT_TOD(1'b1),
|
||||
.PTP_TS_W(96),
|
||||
.PRBS31_EN(1'b0),
|
||||
.TX_SERDES_PIPELINE(1),
|
||||
.RX_SERDES_PIPELINE(1),
|
||||
.COUNT_125US(125000/6.4)
|
||||
)
|
||||
mac_inst (
|
||||
.xcvr_ctrl_clk(clk_125mhz),
|
||||
.xcvr_ctrl_rst(qsfp_rst[CLK]),
|
||||
|
||||
/*
|
||||
* Common
|
||||
*/
|
||||
.xcvr_gtpowergood_out(qsfp_gtpowergood[n]),
|
||||
.xcvr_gtrefclk00_in(qsfp_mgt_refclk[CLK]),
|
||||
.xcvr_qpll0lock_out(),
|
||||
.xcvr_qpll0clk_out(),
|
||||
.xcvr_qpll0refclk_out(),
|
||||
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp(qsfp_tx_p[n*CNT +: CNT]),
|
||||
.xcvr_txn(qsfp_tx_n[n*CNT +: CNT]),
|
||||
.xcvr_rxp(qsfp_rx_p[n*CNT +: CNT]),
|
||||
.xcvr_rxn(qsfp_rx_n[n*CNT +: CNT]),
|
||||
|
||||
/*
|
||||
* MAC clocks
|
||||
*/
|
||||
.rx_clk(qsfp_rx_clk[n*CNT +: CNT]),
|
||||
.rx_rst_in('0),
|
||||
.rx_rst_out(qsfp_rx_rst[n*CNT +: CNT]),
|
||||
.tx_clk(qsfp_tx_clk[n*CNT +: CNT]),
|
||||
.tx_rst_in('0),
|
||||
.tx_rst_out(qsfp_tx_rst[n*CNT +: CNT]),
|
||||
.ptp_sample_clk('0),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(axis_qsfp_tx[n*CNT +: CNT]),
|
||||
.m_axis_tx_cpl(axis_qsfp_tx_cpl[n*CNT +: CNT]),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(axis_qsfp_rx[n*CNT +: CNT]),
|
||||
|
||||
/*
|
||||
* PTP clock
|
||||
*/
|
||||
.tx_ptp_ts('0),
|
||||
.tx_ptp_ts_step('0),
|
||||
.rx_ptp_ts('0),
|
||||
.rx_ptp_ts_step('0),
|
||||
|
||||
|
||||
/*
|
||||
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
|
||||
*/
|
||||
.tx_lfc_req('0),
|
||||
.tx_lfc_resend('0),
|
||||
.rx_lfc_en('0),
|
||||
.rx_lfc_req(),
|
||||
.rx_lfc_ack('0),
|
||||
|
||||
/*
|
||||
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
|
||||
*/
|
||||
.tx_pfc_req('0),
|
||||
.tx_pfc_resend('0),
|
||||
.rx_pfc_en('0),
|
||||
.rx_pfc_req(),
|
||||
.rx_pfc_ack('0),
|
||||
|
||||
/*
|
||||
* Pause interface
|
||||
*/
|
||||
.tx_lfc_pause_en('0),
|
||||
.tx_pause_req('0),
|
||||
.tx_pause_ack(),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_start_packet(),
|
||||
.tx_error_underflow(),
|
||||
.rx_start_packet(),
|
||||
.rx_error_count(),
|
||||
.rx_error_bad_frame(),
|
||||
.rx_error_bad_fcs(),
|
||||
.rx_bad_block(),
|
||||
.rx_sequence_error(),
|
||||
.rx_block_lock(),
|
||||
.rx_high_ber(),
|
||||
.rx_status(qsfp_rx_status[n*CNT +: CNT]),
|
||||
.stat_tx_mcf(),
|
||||
.stat_rx_mcf(),
|
||||
.stat_tx_lfc_pkt(),
|
||||
.stat_tx_lfc_xon(),
|
||||
.stat_tx_lfc_xoff(),
|
||||
.stat_tx_lfc_paused(),
|
||||
.stat_tx_pfc_pkt(),
|
||||
.stat_tx_pfc_xon(),
|
||||
.stat_tx_pfc_xoff(),
|
||||
.stat_tx_pfc_paused(),
|
||||
.stat_rx_lfc_pkt(),
|
||||
.stat_rx_lfc_xon(),
|
||||
.stat_rx_lfc_xoff(),
|
||||
.stat_rx_lfc_paused(),
|
||||
.stat_rx_pfc_pkt(),
|
||||
.stat_rx_pfc_xon(),
|
||||
.stat_rx_pfc_xoff(),
|
||||
.stat_rx_pfc_paused(),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_ifg('{CNT{8'd12}}),
|
||||
.cfg_tx_enable('1),
|
||||
.cfg_rx_enable('1),
|
||||
.cfg_tx_prbs31_enable('0),
|
||||
.cfg_rx_prbs31_enable('0),
|
||||
.cfg_mcf_rx_eth_dst_mcast('{CNT{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_mcf_rx_check_eth_dst_mcast('1),
|
||||
.cfg_mcf_rx_eth_dst_ucast('{CNT{48'd0}}),
|
||||
.cfg_mcf_rx_check_eth_dst_ucast('0),
|
||||
.cfg_mcf_rx_eth_src('{CNT{48'd0}}),
|
||||
.cfg_mcf_rx_check_eth_src('0),
|
||||
.cfg_mcf_rx_eth_type('{CNT{16'h8808}}),
|
||||
.cfg_mcf_rx_opcode_lfc('{CNT{16'h0001}}),
|
||||
.cfg_mcf_rx_check_opcode_lfc('1),
|
||||
.cfg_mcf_rx_opcode_pfc('{CNT{16'h0101}}),
|
||||
.cfg_mcf_rx_check_opcode_pfc('1),
|
||||
.cfg_mcf_rx_forward('0),
|
||||
.cfg_mcf_rx_enable('0),
|
||||
.cfg_tx_lfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_tx_lfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
|
||||
.cfg_tx_lfc_eth_type('{CNT{16'h8808}}),
|
||||
.cfg_tx_lfc_opcode('{CNT{16'h0001}}),
|
||||
.cfg_tx_lfc_en('0),
|
||||
.cfg_tx_lfc_quanta('{CNT{16'hffff}}),
|
||||
.cfg_tx_lfc_refresh('{CNT{16'h7fff}}),
|
||||
.cfg_tx_pfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_tx_pfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
|
||||
.cfg_tx_pfc_eth_type('{CNT{16'h8808}}),
|
||||
.cfg_tx_pfc_opcode('{CNT{16'h0101}}),
|
||||
.cfg_tx_pfc_en('0),
|
||||
.cfg_tx_pfc_quanta('{CNT{'{8{16'hffff}}}}),
|
||||
.cfg_tx_pfc_refresh('{CNT{'{8{16'h7fff}}}}),
|
||||
.cfg_rx_lfc_opcode('{CNT{16'h0001}}),
|
||||
.cfg_rx_lfc_en('0),
|
||||
.cfg_rx_pfc_opcode('{CNT{16'h0101}}),
|
||||
.cfg_rx_pfc_en('0)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
for (genvar n = 0; n < 8; n = n + 1) begin : qsfp_ch
|
||||
|
||||
taxi_axis_async_fifo #(
|
||||
.DEPTH(16384),
|
||||
.RAM_PIPELINE(2),
|
||||
.FRAME_FIFO(1),
|
||||
.USER_BAD_FRAME_VALUE(1'b1),
|
||||
.USER_BAD_FRAME_MASK(1'b1),
|
||||
.DROP_OVERSIZE_FRAME(1),
|
||||
.DROP_BAD_FRAME(1),
|
||||
.DROP_WHEN_FULL(1)
|
||||
)
|
||||
ch_fifo (
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_clk(qsfp_rx_clk[n]),
|
||||
.s_rst(qsfp_rx_rst[n]),
|
||||
.s_axis(axis_qsfp_rx[n]),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_clk(qsfp_tx_clk[n]),
|
||||
.m_rst(qsfp_tx_rst[n]),
|
||||
.m_axis(axis_qsfp_tx[n]),
|
||||
|
||||
/*
|
||||
* Pause
|
||||
*/
|
||||
.s_pause_req(1'b0),
|
||||
.s_pause_ack(),
|
||||
.m_pause_req(1'b0),
|
||||
.m_pause_ack(),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.s_status_depth(),
|
||||
.s_status_depth_commit(),
|
||||
.s_status_overflow(),
|
||||
.s_status_bad_frame(),
|
||||
.s_status_good_frame(),
|
||||
.m_status_depth(),
|
||||
.m_status_depth_commit(),
|
||||
.m_status_overflow(),
|
||||
.m_status_bad_frame(),
|
||||
.m_status_good_frame()
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
52
example/fb2CG/fpga/tb/fpga_core/Makefile
Normal file
52
example/fb2CG/fpga/tb/fpga_core/Makefile
Normal file
@@ -0,0 +1,52 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
DUT = fpga_core
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = $(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += ../../rtl/$(DUT).sv
|
||||
VERILOG_SOURCES += ../../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f
|
||||
VERILOG_SOURCES += ../../lib/taxi/rtl/axis/taxi_axis_async_fifo.f
|
||||
VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_reset.sv
|
||||
VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_signal.sv
|
||||
VERILOG_SOURCES += ../../lib/taxi/rtl/io/taxi_led_sreg.sv
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_SIM := "1'b1"
|
||||
export PARAM_VENDOR := "\"XILINX\""
|
||||
export PARAM_FAMILY := "\"kintexuplus\""
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
1
example/fb2CG/fpga/tb/fpga_core/baser.py
Symbolic link
1
example/fb2CG/fpga/tb/fpga_core/baser.py
Symbolic link
@@ -0,0 +1 @@
|
||||
../../lib/taxi/tb/eth/baser.py
|
||||
198
example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py
Normal file
198
example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py
Normal file
@@ -0,0 +1,198 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: MIT
|
||||
"""
|
||||
|
||||
Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import logging
|
||||
import os
|
||||
import sys
|
||||
|
||||
import cocotb_test.simulator
|
||||
|
||||
import cocotb
|
||||
from cocotb.log import SimLog
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge, Combine
|
||||
|
||||
from cocotbext.eth import XgmiiFrame
|
||||
|
||||
try:
|
||||
from baser import BaseRSerdesSource, BaseRSerdesSink
|
||||
except ImportError:
|
||||
# attempt import from current directory
|
||||
sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
|
||||
try:
|
||||
from baser import BaseRSerdesSource, BaseRSerdesSink
|
||||
finally:
|
||||
del sys.path[0]
|
||||
|
||||
|
||||
class TB:
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = SimLog("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start())
|
||||
cocotb.start_soon(Clock(dut.qsfp_0_mgt_refclk_p, 6.206, units="ns").start())
|
||||
cocotb.start_soon(Clock(dut.qsfp_1_mgt_refclk_p, 6.206, units="ns").start())
|
||||
|
||||
self.qsfp_sources = []
|
||||
self.qsfp_sinks = []
|
||||
|
||||
for inst in dut.gty_quad:
|
||||
for ch in inst.mac_inst.ch:
|
||||
cocotb.start_soon(Clock(ch.ch_inst.tx_clk, 2.56, units="ns").start())
|
||||
cocotb.start_soon(Clock(ch.ch_inst.rx_clk, 2.56, units="ns").start())
|
||||
|
||||
self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
|
||||
self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True))
|
||||
|
||||
dut.qsfp_0_mod_prsnt_n.setimmediatevalue(0)
|
||||
dut.qsfp_0_intr_n.setimmediatevalue(0)
|
||||
dut.qsfp_1_mod_prsnt_n.setimmediatevalue(0)
|
||||
dut.qsfp_1_intr_n.setimmediatevalue(0)
|
||||
|
||||
async def init(self):
|
||||
|
||||
self.dut.rst_125mhz.setimmediatevalue(0)
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.clk_125mhz)
|
||||
|
||||
self.dut.rst_125mhz.value = 1
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.clk_125mhz)
|
||||
|
||||
self.dut.rst_125mhz.value = 0
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.clk_125mhz)
|
||||
|
||||
|
||||
async def mac_test(tb, source, sink):
|
||||
tb.log.info("Test MAC")
|
||||
|
||||
tb.log.info("Multiple small packets")
|
||||
|
||||
count = 64
|
||||
|
||||
pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
|
||||
|
||||
for p in pkts:
|
||||
await source.send(XgmiiFrame.from_payload(p))
|
||||
|
||||
for k in range(count):
|
||||
rx_frame = await sink.recv()
|
||||
|
||||
tb.log.info("RX frame: %s", rx_frame)
|
||||
|
||||
assert rx_frame.get_payload() == pkts[k]
|
||||
assert rx_frame.check_fcs()
|
||||
|
||||
tb.log.info("Multiple large packets")
|
||||
|
||||
count = 32
|
||||
|
||||
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
|
||||
|
||||
for p in pkts:
|
||||
await source.send(XgmiiFrame.from_payload(p))
|
||||
|
||||
for k in range(count):
|
||||
rx_frame = await sink.recv()
|
||||
|
||||
tb.log.info("RX frame: %s", rx_frame)
|
||||
|
||||
assert rx_frame.get_payload() == pkts[k]
|
||||
assert rx_frame.check_fcs()
|
||||
|
||||
tb.log.info("MAC test done")
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def run_test(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.init()
|
||||
|
||||
tests = []
|
||||
|
||||
for k in range(len(tb.qsfp_sources)):
|
||||
tb.log.info("Start QSFP %d MAC loopback test", k)
|
||||
|
||||
tests.append(cocotb.start_soon(mac_test(tb, tb.qsfp_sources[k], tb.qsfp_sinks[k])))
|
||||
|
||||
await Combine(*tests)
|
||||
|
||||
await RisingEdge(dut.clk_125mhz)
|
||||
await RisingEdge(dut.clk_125mhz)
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
def test_fpga_core(request):
|
||||
dut = "fpga_core"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = dut
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
os.path.join(lib_dir, "taxi", "rtl", "eth", "us", "taxi_eth_mac_25g_us.f"),
|
||||
os.path.join(lib_dir, "taxi", "rtl", "axis", "taxi_axis_async_fifo.f"),
|
||||
os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_reset.sv"),
|
||||
os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_signal.sv"),
|
||||
os.path.join(lib_dir, "taxi", "rtl", "io", "taxi_debounce_switch.sv"),
|
||||
os.path.join(lib_dir, "taxi", "rtl", "io", "taxi_led_sreg.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['SIM'] = "1'b1"
|
||||
parameters['VENDOR'] = "\"XILINX\""
|
||||
parameters['FAMILY'] = "\"kintexuplus\""
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
Reference in New Issue
Block a user