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axis: Add AXI stream broadcaster module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
179
rtl/axis/taxi_axis_broadcast.sv
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179
rtl/axis/taxi_axis_broadcast.sv
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@@ -0,0 +1,179 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2019-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4-Stream broadcaster
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*/
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module taxi_axis_broadcast #
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(
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// Number of AXI stream outputs
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parameter M_COUNT = 4
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* AXI4-Stream input (sink)
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*/
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taxi_axis_if.snk s_axis,
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/*
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* AXI4-Stream outputs (sources)
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*/
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taxi_axis_if.src m_axis[M_COUNT-1:0]
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);
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// extract parameters
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localparam DATA_W = s_axis.DATA_W;
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localparam logic KEEP_EN = s_axis.KEEP_EN && m_axis.KEEP_EN;
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localparam KEEP_W = s_axis.KEEP_W;
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localparam logic STRB_EN = s_axis.STRB_EN && m_axis.STRB_EN;
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localparam logic LAST_EN = s_axis.LAST_EN && m_axis.LAST_EN;
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localparam logic ID_EN = s_axis.ID_EN && m_axis.ID_EN;
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localparam ID_W = s_axis.ID_W;
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localparam logic DEST_EN = s_axis.DEST_EN && m_axis.DEST_EN;
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localparam DEST_W = s_axis.DEST_W;
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localparam logic USER_EN = s_axis.USER_EN && m_axis.USER_EN;
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localparam USER_W = s_axis.USER_W;
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// check configuration
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if (m_axis.DATA_W != DATA_W)
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$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
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if (KEEP_EN && m_axis.KEEP_W != KEEP_W)
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$fatal(0, "Error: Interface KEEP_W parameter mismatch (instance %m)");
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// datapath registers
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logic s_axis_tready_reg = 1'b0, s_axis_tready_next;
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logic [DATA_W-1:0] m_axis_tdata_reg = '0;
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logic [KEEP_W-1:0] m_axis_tkeep_reg = '0;
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logic [KEEP_W-1:0] m_axis_tstrb_reg = '0;
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logic [M_COUNT-1:0] m_axis_tvalid_reg = '0, m_axis_tvalid_next;
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logic m_axis_tlast_reg = 1'b0;
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logic [ID_W-1:0] m_axis_tid_reg = '0;
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logic [DEST_W-1:0] m_axis_tdest_reg = '0;
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logic [USER_W-1:0] m_axis_tuser_reg = '0;
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logic [DATA_W-1:0] temp_m_axis_tdata_reg = '0;
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logic [KEEP_W-1:0] temp_m_axis_tkeep_reg = '0;
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logic [KEEP_W-1:0] temp_m_axis_tstrb_reg = '0;
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logic temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
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logic temp_m_axis_tlast_reg = 1'b0;
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logic [ID_W-1:0] temp_m_axis_tid_reg = '0;
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logic [DEST_W-1:0] temp_m_axis_tdest_reg = '0;
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logic [USER_W-1:0] temp_m_axis_tuser_reg = '0;
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// // datapath control
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logic store_axis_input_to_output;
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logic store_axis_input_to_temp;
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logic store_axis_temp_to_output;
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assign s_axis.tready = s_axis_tready_reg;
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wire [M_COUNT-1:0] m_axis_tready;
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wire [M_COUNT-1:0] m_axis_tvalid;
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for (genvar n = 0; n < M_COUNT; n = n + 1) begin
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assign m_axis[n].tdata = m_axis_tdata_reg;
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assign m_axis[n].tkeep = KEEP_EN ? m_axis_tkeep_reg : '1;
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assign m_axis[n].tstrb = STRB_EN ? m_axis_tstrb_reg : m_axis[n].tkeep;
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assign m_axis[n].tvalid = m_axis_tvalid_reg[n];
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assign m_axis[n].tlast = LAST_EN ? m_axis_tlast_reg : 1'b1;
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assign m_axis[n].tid = ID_EN ? m_axis_tid_reg : '0;
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assign m_axis[n].tdest = DEST_EN ? m_axis_tdest_reg : '0;
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assign m_axis[n].tuser = USER_EN ? m_axis_tuser_reg : '0;
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assign m_axis_tready[n] = m_axis[n].tready;
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assign m_axis_tvalid[n] = m_axis[n].tvalid;
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end
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// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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wire s_axis_tready_early = ((m_axis_tready & m_axis_tvalid) == m_axis_tvalid) || (!temp_m_axis_tvalid_reg && (m_axis_tvalid == 0 || !s_axis.tvalid));
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always @* begin
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// transfer sink ready state to source
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m_axis_tvalid_next = m_axis_tvalid_reg & ~m_axis_tready;
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temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
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store_axis_input_to_output = 1'b0;
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store_axis_input_to_temp = 1'b0;
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store_axis_temp_to_output = 1'b0;
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if (s_axis_tready_reg) begin
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// input is ready
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if (((m_axis_tready & m_axis_tvalid) == m_axis_tvalid) || m_axis_tvalid == 0) begin
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// output is ready or currently not valid, transfer data to output
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m_axis_tvalid_next = {M_COUNT{s_axis.tvalid}};
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store_axis_input_to_output = 1'b1;
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end else begin
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// output is not ready, store input in temp
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temp_m_axis_tvalid_next = s_axis.tvalid;
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store_axis_input_to_temp = 1'b1;
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end
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end else if ((m_axis_tready & m_axis_tvalid) == m_axis_tvalid) begin
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// input is not ready, but output is ready
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m_axis_tvalid_next = {M_COUNT{temp_m_axis_tvalid_reg}};
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temp_m_axis_tvalid_next = 1'b0;
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store_axis_temp_to_output = 1'b1;
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end
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end
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always @(posedge clk) begin
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s_axis_tready_reg <= s_axis_tready_early;
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m_axis_tvalid_reg <= m_axis_tvalid_next;
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temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
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// datapath
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if (store_axis_input_to_output) begin
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m_axis_tdata_reg <= s_axis.tdata;
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m_axis_tkeep_reg <= s_axis.tkeep;
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m_axis_tstrb_reg <= s_axis.tstrb;
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m_axis_tlast_reg <= s_axis.tlast;
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m_axis_tid_reg <= s_axis.tid;
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m_axis_tdest_reg <= s_axis.tdest;
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m_axis_tuser_reg <= s_axis.tuser;
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end else if (store_axis_temp_to_output) begin
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m_axis_tdata_reg <= temp_m_axis_tdata_reg;
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m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
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m_axis_tstrb_reg <= temp_m_axis_tstrb_reg;
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m_axis_tlast_reg <= temp_m_axis_tlast_reg;
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m_axis_tid_reg <= temp_m_axis_tid_reg;
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m_axis_tdest_reg <= temp_m_axis_tdest_reg;
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m_axis_tuser_reg <= temp_m_axis_tuser_reg;
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end
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if (store_axis_input_to_temp) begin
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temp_m_axis_tdata_reg <= s_axis.tdata;
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temp_m_axis_tkeep_reg <= s_axis.tkeep;
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temp_m_axis_tstrb_reg <= s_axis.tstrb;
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temp_m_axis_tlast_reg <= s_axis.tlast;
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temp_m_axis_tid_reg <= s_axis.tid;
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temp_m_axis_tdest_reg <= s_axis.tdest;
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temp_m_axis_tuser_reg <= s_axis.tuser;
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end
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if (rst) begin
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s_axis_tready_reg <= 1'b0;
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m_axis_tvalid_reg <= '0;
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temp_m_axis_tvalid_reg <= '0;
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end
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end
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endmodule
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`resetall
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58
tb/axis/taxi_axis_broadcast/Makefile
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58
tb/axis/taxi_axis_broadcast/Makefile
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@@ -0,0 +1,58 @@
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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#
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# Copyright (c) 2021-2025 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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TOPLEVEL_LANG = verilog
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SIM ?= verilator
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WAVES ?= 0
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COCOTB_HDL_TIMEUNIT = 1ns
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COCOTB_HDL_TIMEPRECISION = 1ps
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DUT = taxi_axis_broadcast
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COCOTB_TEST_MODULES = test_$(DUT)
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COCOTB_TOPLEVEL = test_$(DUT)
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MODULE = $(COCOTB_TEST_MODULES)
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TOPLEVEL = $(COCOTB_TOPLEVEL)
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VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
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VERILOG_SOURCES += ../../../rtl/axis/$(DUT).sv
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VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv
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# handle file list files
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process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
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process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
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uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
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VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
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# module parameters
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export PARAM_M_COUNT := 4
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export PARAM_DATA_W := 8
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export PARAM_KEEP_EN := $(shell expr $(PARAM_DATA_W) \> 8 )
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export PARAM_KEEP_W := $(shell expr \( $(PARAM_DATA_W) + 7 \) / 8 )
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export PARAM_STRB_EN := 0
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export PARAM_LAST_EN := 1
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export PARAM_ID_EN := 1
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export PARAM_ID_W := 8
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export PARAM_DEST_EN := 1
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export PARAM_DEST_W := 8
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export PARAM_USER_EN := 1
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export PARAM_USER_W := 1
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
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else ifeq ($(SIM), verilator)
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
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ifeq ($(WAVES), 1)
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COMPILE_ARGS += --trace-fst
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VERILATOR_TRACE = 1
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endif
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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188
tb/axis/taxi_axis_broadcast/test_taxi_axis_broadcast.py
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188
tb/axis/taxi_axis_broadcast/test_taxi_axis_broadcast.py
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@@ -0,0 +1,188 @@
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#!/usr/bin/env python
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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"""
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Copyright (c) 2021-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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"""
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import itertools
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import logging
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import os
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import cocotb_test.simulator
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import pytest
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge
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from cocotb.regression import TestFactory
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from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
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class TB(object):
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def __init__(self, dut):
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self.dut = dut
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self.log = logging.getLogger("cocotb.tb")
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self.log.setLevel(logging.DEBUG)
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cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
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self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.clk, dut.rst)
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self.sink = [AxiStreamSink(AxiStreamBus.from_entity(bus), dut.clk, dut.rst) for bus in dut.m_axis]
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def set_idle_generator(self, generator=None):
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if generator:
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self.source.set_pause_generator(generator())
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def set_backpressure_generator(self, generator=None):
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if generator:
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for sink in self.sink:
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sink.set_pause_generator(generator())
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async def reset(self):
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self.dut.rst.setimmediatevalue(0)
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 1
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 0
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
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tb = TB(dut)
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id_count = 2**len(tb.source.bus.tid)
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cur_id = 1
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await tb.reset()
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tb.set_idle_generator(idle_inserter)
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tb.set_backpressure_generator(backpressure_inserter)
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test_frames = []
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for test_data in [payload_data(x) for x in payload_lengths()]:
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test_frame = AxiStreamFrame(test_data)
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test_frame.tid = cur_id
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test_frame.tdest = cur_id
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test_frames.append(test_frame)
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await tb.source.send(test_frame)
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cur_id = (cur_id + 1) % id_count
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for test_frame in test_frames:
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for sink in tb.sink:
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rx_frame = await sink.recv()
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assert rx_frame.tdata == test_frame.tdata
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assert rx_frame.tid == test_frame.tid
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assert rx_frame.tdest == test_frame.tdest
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assert not rx_frame.tuser
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for sink in tb.sink:
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assert sink.empty()
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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def cycle_pause():
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return itertools.cycle([1, 1, 1, 0])
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def size_list():
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data_width = len(cocotb.top.s_axis.tdata)
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byte_width = data_width // 8
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return list(range(1, byte_width*4+1))+[512]+[1]*64
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def incrementing_payload(length):
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return bytearray(itertools.islice(itertools.cycle(range(256)), length))
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if cocotb.SIM_NAME:
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factory = TestFactory(run_test)
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factory.add_option("payload_lengths", [size_list])
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factory.add_option("payload_data", [incrementing_payload])
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factory.add_option("idle_inserter", [None, cycle_pause])
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factory.add_option("backpressure_inserter", [None, cycle_pause])
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factory.generate_tests()
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# cocotb-test
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tests_dir = os.path.dirname(__file__)
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rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
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def process_f_files(files):
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lst = {}
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for f in files:
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if f[-2:].lower() == '.f':
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with open(f, 'r') as fp:
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l = fp.read().split()
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for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
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lst[os.path.basename(f)] = f
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else:
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lst[os.path.basename(f)] = f
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return list(lst.values())
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@pytest.mark.parametrize("data_w", [8, 16, 32])
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@pytest.mark.parametrize("m_count", range(1, 4))
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def test_taxi_axis_broadcast(request, m_count, data_w):
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dut = "taxi_axis_broadcast"
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module = os.path.splitext(os.path.basename(__file__))[0]
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toplevel = module
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verilog_sources = [
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os.path.join(tests_dir, f"{toplevel}.sv"),
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os.path.join(rtl_dir, "axis", f"{dut}.sv"),
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os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"),
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]
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verilog_sources = process_f_files(verilog_sources)
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parameters = {}
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parameters['M_COUNT'] = m_count
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parameters['DATA_W'] = data_w
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parameters['KEEP_EN'] = int(parameters['DATA_W'] > 8)
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parameters['KEEP_W'] = (parameters['DATA_W'] + 7) // 8
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parameters['STRB_EN'] = 0
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parameters['LAST_EN'] = 1
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parameters['ID_EN'] = 1
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parameters['ID_W'] = 8
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parameters['DEST_EN'] = 1
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parameters['DEST_W'] = 8
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parameters['USER_EN'] = 1
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parameters['USER_W'] = 1
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extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
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|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
74
tb/axis/taxi_axis_broadcast/test_taxi_axis_broadcast.sv
Normal file
74
tb/axis/taxi_axis_broadcast/test_taxi_axis_broadcast.sv
Normal file
@@ -0,0 +1,74 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream broadcaster testbench
|
||||
*/
|
||||
module test_taxi_axis_broadcast #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter M_COUNT = 4,
|
||||
parameter DATA_W = 8,
|
||||
parameter logic KEEP_EN = (DATA_W>8),
|
||||
parameter KEEP_W = ((DATA_W+7)/8),
|
||||
parameter logic STRB_EN = 1'b0,
|
||||
parameter logic LAST_EN = 1'b1,
|
||||
parameter logic ID_EN = 1'b0,
|
||||
parameter ID_W = 8,
|
||||
parameter logic DEST_EN = 1'b0,
|
||||
parameter DEST_W = 8,
|
||||
parameter logic USER_EN = 1'b1,
|
||||
parameter USER_W = 1
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.KEEP_EN(KEEP_EN),
|
||||
.KEEP_W(KEEP_W),
|
||||
.STRB_EN(STRB_EN),
|
||||
.LAST_EN(LAST_EN),
|
||||
.ID_EN(ID_EN),
|
||||
.ID_W(ID_W),
|
||||
.DEST_EN(DEST_EN),
|
||||
.DEST_W(DEST_W),
|
||||
.USER_EN(USER_EN),
|
||||
.USER_W(USER_W)
|
||||
) s_axis(), m_axis[M_COUNT]();
|
||||
|
||||
taxi_axis_broadcast #(
|
||||
.M_COUNT(M_COUNT)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_axis(s_axis),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(m_axis)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user