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example/fb2CG: Add example design for fb2CG@KU15P
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
409
example/fb2CG/fpga/rtl/fpga_core.sv
Normal file
409
example/fb2CG/fpga/rtl/fpga_core.sv
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@@ -0,0 +1,409 @@
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// SPDX-License-Identifier: MIT
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/*
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Copyright (c) 2014-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA core logic
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*/
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module fpga_core #
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(
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parameter logic SIM = 1'b0,
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parameter string VENDOR = "XILINX",
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parameter string FAMILY = "kintexuplus"
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)
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(
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/*
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* Clock: 156.25MHz
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* Synchronous reset
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*/
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input wire logic clk_125mhz,
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input wire logic rst_125mhz,
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/*
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* GPIO
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*/
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output wire logic led_sreg_d,
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output wire logic led_sreg_ld,
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output wire logic led_sreg_clk,
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output wire logic [1:0] led_bmc,
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output wire logic [1:0] led_exp,
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/*
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* Ethernet: QSFP28
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*/
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output wire logic [3:0] qsfp_0_tx_p,
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output wire logic [3:0] qsfp_0_tx_n,
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input wire logic [3:0] qsfp_0_rx_p,
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input wire logic [3:0] qsfp_0_rx_n,
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input wire logic qsfp_0_mgt_refclk_p,
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input wire logic qsfp_0_mgt_refclk_n,
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input wire logic qsfp_0_mod_prsnt_n,
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output wire logic qsfp_0_reset_n,
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output wire logic qsfp_0_lp_mode,
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input wire logic qsfp_0_intr_n,
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output wire logic [3:0] qsfp_1_tx_p,
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output wire logic [3:0] qsfp_1_tx_n,
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input wire logic [3:0] qsfp_1_rx_p,
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input wire logic [3:0] qsfp_1_rx_n,
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input wire logic qsfp_1_mgt_refclk_p,
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input wire logic qsfp_1_mgt_refclk_n,
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input wire logic qsfp_1_mod_prsnt_n,
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output wire logic qsfp_1_reset_n,
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output wire logic qsfp_1_lp_mode,
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input wire logic qsfp_1_intr_n
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);
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// LED
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wire [7:0] led_g;
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wire [7:0] led_r;
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taxi_led_sreg #(
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.COUNT(8),
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.INVERT(1),
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.REVERSE(0),
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.INTERLEAVE(1),
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.PRESCALE(63)
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)
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led_sreg_driver_inst (
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.clk(clk_125mhz),
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.rst(rst_125mhz),
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.led_a(led_r),
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.led_b(led_g),
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.sreg_d(led_sreg_d),
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.sreg_ld(led_sreg_ld),
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.sreg_clk(led_sreg_clk)
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);
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// QSFP28
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assign qsfp_0_reset_n = 1'b1;
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assign qsfp_0_lp_mode = 1'b0;
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assign qsfp_1_reset_n = 1'b1;
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assign qsfp_1_lp_mode = 1'b0;
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wire [7:0] qsfp_tx_clk;
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wire [7:0] qsfp_tx_rst;
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wire [7:0] qsfp_rx_clk;
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wire [7:0] qsfp_rx_rst;
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wire [7:0] qsfp_rx_status;
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assign led_g = qsfp_rx_status;
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assign led_r = '0;
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assign led_bmc = '0;
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assign led_exp = '1;
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wire [1:0] qsfp_gtpowergood;
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taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_qsfp_tx[7:0]();
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taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_qsfp_tx_cpl[7:0]();
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taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_qsfp_rx[7:0]();
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wire [1:0] qsfp_mgt_refclk_p = {qsfp_1_mgt_refclk_p, qsfp_0_mgt_refclk_p};
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wire [1:0] qsfp_mgt_refclk_n = {qsfp_1_mgt_refclk_n, qsfp_0_mgt_refclk_n};
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wire [1:0] qsfp_mgt_refclk;
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wire [1:0] qsfp_mgt_refclk_bufg;
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wire [1:0] qsfp_rst;
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for (genvar n = 0; n < 2; n = n + 1) begin : gty_clk
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wire qsfp_mgt_refclk_int;
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if (SIM) begin
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assign qsfp_mgt_refclk[n] = qsfp_mgt_refclk_p[n];
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assign qsfp_mgt_refclk_int = qsfp_mgt_refclk_p[n];
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assign qsfp_mgt_refclk_bufg[n] = qsfp_mgt_refclk_int;
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end else begin
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IBUFDS_GTE4 ibufds_gte4_qsfp_mgt_refclk_inst (
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.I (qsfp_mgt_refclk_p[n]),
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.IB (qsfp_mgt_refclk_n[n]),
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.CEB (1'b0),
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.O (qsfp_mgt_refclk[n]),
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.ODIV2 (qsfp_mgt_refclk_int)
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);
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BUFG_GT bufg_gt_qsfp_mgt_refclk_inst (
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.CE (&qsfp_gtpowergood),
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.CEMASK (1'b1),
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.CLR (1'b0),
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.CLRMASK (1'b1),
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.DIV (3'd0),
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.I (qsfp_mgt_refclk_int),
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.O (qsfp_mgt_refclk_bufg[n])
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);
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end
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taxi_sync_reset #(
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.N(4)
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)
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qsfp_sync_reset_inst (
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.clk(qsfp_mgt_refclk_bufg[n]),
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.rst(rst_125mhz),
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.out(qsfp_rst[n])
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);
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end
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wire [7:0] qsfp_tx_p;
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wire [7:0] qsfp_tx_n;
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wire [7:0] qsfp_rx_p = {qsfp_1_rx_p, qsfp_0_rx_p};
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wire [7:0] qsfp_rx_n = {qsfp_1_rx_n, qsfp_0_rx_n};
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assign qsfp_0_tx_p = qsfp_tx_p[3:0];
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assign qsfp_0_tx_n = qsfp_tx_n[3:0];
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assign qsfp_1_tx_p = qsfp_tx_p[7:4];
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assign qsfp_1_tx_n = qsfp_tx_n[7:4];
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for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
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localparam CLK = n;
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localparam CNT = 4;
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taxi_eth_mac_25g_us #(
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.SIM(SIM),
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.VENDOR(VENDOR),
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.FAMILY(FAMILY),
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.CNT(CNT),
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// GT type
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.GT_TYPE("GTY"),
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// PHY parameters
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.PADDING_EN(1'b1),
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.DIC_EN(1'b1),
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.MIN_FRAME_LEN(64),
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.PTP_TS_EN(1'b0),
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.PTP_TS_FMT_TOD(1'b1),
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.PTP_TS_W(96),
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.PRBS31_EN(1'b0),
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.TX_SERDES_PIPELINE(1),
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.RX_SERDES_PIPELINE(1),
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.COUNT_125US(125000/6.4)
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)
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mac_inst (
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.xcvr_ctrl_clk(clk_125mhz),
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.xcvr_ctrl_rst(qsfp_rst[CLK]),
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/*
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* Common
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*/
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.xcvr_gtpowergood_out(qsfp_gtpowergood[n]),
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.xcvr_gtrefclk00_in(qsfp_mgt_refclk[CLK]),
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.xcvr_qpll0lock_out(),
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.xcvr_qpll0clk_out(),
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.xcvr_qpll0refclk_out(),
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/*
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* Serial data
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*/
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.xcvr_txp(qsfp_tx_p[n*CNT +: CNT]),
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.xcvr_txn(qsfp_tx_n[n*CNT +: CNT]),
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.xcvr_rxp(qsfp_rx_p[n*CNT +: CNT]),
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.xcvr_rxn(qsfp_rx_n[n*CNT +: CNT]),
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/*
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* MAC clocks
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*/
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.rx_clk(qsfp_rx_clk[n*CNT +: CNT]),
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.rx_rst_in('0),
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.rx_rst_out(qsfp_rx_rst[n*CNT +: CNT]),
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.tx_clk(qsfp_tx_clk[n*CNT +: CNT]),
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.tx_rst_in('0),
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.tx_rst_out(qsfp_tx_rst[n*CNT +: CNT]),
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.ptp_sample_clk('0),
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/*
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* Transmit interface (AXI stream)
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*/
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.s_axis_tx(axis_qsfp_tx[n*CNT +: CNT]),
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.m_axis_tx_cpl(axis_qsfp_tx_cpl[n*CNT +: CNT]),
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/*
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* Receive interface (AXI stream)
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*/
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.m_axis_rx(axis_qsfp_rx[n*CNT +: CNT]),
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/*
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* PTP clock
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*/
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.tx_ptp_ts('0),
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.tx_ptp_ts_step('0),
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.rx_ptp_ts('0),
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.rx_ptp_ts_step('0),
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/*
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* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
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*/
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.tx_lfc_req('0),
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.tx_lfc_resend('0),
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.rx_lfc_en('0),
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.rx_lfc_req(),
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.rx_lfc_ack('0),
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/*
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* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
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*/
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.tx_pfc_req('0),
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.tx_pfc_resend('0),
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.rx_pfc_en('0),
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.rx_pfc_req(),
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.rx_pfc_ack('0),
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/*
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* Pause interface
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*/
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.tx_lfc_pause_en('0),
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.tx_pause_req('0),
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.tx_pause_ack(),
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/*
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* Status
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*/
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.tx_start_packet(),
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.tx_error_underflow(),
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.rx_start_packet(),
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.rx_error_count(),
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.rx_error_bad_frame(),
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.rx_error_bad_fcs(),
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.rx_bad_block(),
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.rx_sequence_error(),
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.rx_block_lock(),
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.rx_high_ber(),
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.rx_status(qsfp_rx_status[n*CNT +: CNT]),
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.stat_tx_mcf(),
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.stat_rx_mcf(),
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.stat_tx_lfc_pkt(),
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.stat_tx_lfc_xon(),
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.stat_tx_lfc_xoff(),
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.stat_tx_lfc_paused(),
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.stat_tx_pfc_pkt(),
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.stat_tx_pfc_xon(),
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.stat_tx_pfc_xoff(),
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.stat_tx_pfc_paused(),
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.stat_rx_lfc_pkt(),
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.stat_rx_lfc_xon(),
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.stat_rx_lfc_xoff(),
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.stat_rx_lfc_paused(),
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.stat_rx_pfc_pkt(),
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.stat_rx_pfc_xon(),
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.stat_rx_pfc_xoff(),
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.stat_rx_pfc_paused(),
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/*
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* Configuration
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*/
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.cfg_ifg('{CNT{8'd12}}),
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.cfg_tx_enable('1),
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.cfg_rx_enable('1),
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.cfg_tx_prbs31_enable('0),
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.cfg_rx_prbs31_enable('0),
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.cfg_mcf_rx_eth_dst_mcast('{CNT{48'h01_80_C2_00_00_01}}),
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.cfg_mcf_rx_check_eth_dst_mcast('1),
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.cfg_mcf_rx_eth_dst_ucast('{CNT{48'd0}}),
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.cfg_mcf_rx_check_eth_dst_ucast('0),
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.cfg_mcf_rx_eth_src('{CNT{48'd0}}),
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.cfg_mcf_rx_check_eth_src('0),
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.cfg_mcf_rx_eth_type('{CNT{16'h8808}}),
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.cfg_mcf_rx_opcode_lfc('{CNT{16'h0001}}),
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.cfg_mcf_rx_check_opcode_lfc('1),
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.cfg_mcf_rx_opcode_pfc('{CNT{16'h0101}}),
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.cfg_mcf_rx_check_opcode_pfc('1),
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.cfg_mcf_rx_forward('0),
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.cfg_mcf_rx_enable('0),
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.cfg_tx_lfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
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.cfg_tx_lfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
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.cfg_tx_lfc_eth_type('{CNT{16'h8808}}),
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.cfg_tx_lfc_opcode('{CNT{16'h0001}}),
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.cfg_tx_lfc_en('0),
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.cfg_tx_lfc_quanta('{CNT{16'hffff}}),
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.cfg_tx_lfc_refresh('{CNT{16'h7fff}}),
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.cfg_tx_pfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
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.cfg_tx_pfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
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.cfg_tx_pfc_eth_type('{CNT{16'h8808}}),
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.cfg_tx_pfc_opcode('{CNT{16'h0101}}),
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.cfg_tx_pfc_en('0),
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.cfg_tx_pfc_quanta('{CNT{'{8{16'hffff}}}}),
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.cfg_tx_pfc_refresh('{CNT{'{8{16'h7fff}}}}),
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.cfg_rx_lfc_opcode('{CNT{16'h0001}}),
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.cfg_rx_lfc_en('0),
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.cfg_rx_pfc_opcode('{CNT{16'h0101}}),
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.cfg_rx_pfc_en('0)
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);
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end
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for (genvar n = 0; n < 8; n = n + 1) begin : qsfp_ch
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taxi_axis_async_fifo #(
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.DEPTH(16384),
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.RAM_PIPELINE(2),
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.FRAME_FIFO(1),
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.USER_BAD_FRAME_VALUE(1'b1),
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.USER_BAD_FRAME_MASK(1'b1),
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.DROP_OVERSIZE_FRAME(1),
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.DROP_BAD_FRAME(1),
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.DROP_WHEN_FULL(1)
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)
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ch_fifo (
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/*
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* AXI4-Stream input (sink)
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*/
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.s_clk(qsfp_rx_clk[n]),
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.s_rst(qsfp_rx_rst[n]),
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.s_axis(axis_qsfp_rx[n]),
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/*
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* AXI4-Stream output (source)
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*/
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.m_clk(qsfp_tx_clk[n]),
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.m_rst(qsfp_tx_rst[n]),
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.m_axis(axis_qsfp_tx[n]),
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/*
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* Pause
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*/
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.s_pause_req(1'b0),
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.s_pause_ack(),
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.m_pause_req(1'b0),
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.m_pause_ack(),
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/*
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* Status
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*/
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.s_status_depth(),
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.s_status_depth_commit(),
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.s_status_overflow(),
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.s_status_bad_frame(),
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.s_status_good_frame(),
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.m_status_depth(),
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.m_status_depth_commit(),
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.m_status_overflow(),
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.m_status_bad_frame(),
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.m_status_good_frame()
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);
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end
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endmodule
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`resetall
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