bslathi19/taxi
1
0
Fork 0
mirror of https://github.com/fpganinja/taxi.git synced 2025-12-07 16:28:40 -08:00
Code Issues Packages Projects Releases Wiki Activity

eth: Normalize CRC register naming in 10G RX modules

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-10-04 15:54:49 -07:00
parent d0d6747f88
commit 879b65cc70
4 changed files with 48 additions and 48 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
src/eth/rtl/taxi_axis_baser_rx_32.sv
View File

@@ -207,17 +207,17 @@ logic stat_rx_err_preamble_reg = 1'b0, stat_rx_err_preamble_next;
logic [PTP_TS_W-1:0] ptp_ts_out_reg = '0, ptp_ts_out_next; logic [PTP_TS_W-1:0] ptp_ts_out_reg = '0, ptp_ts_out_next;
logic [31:0] crc_state = '1; logic [31:0] crc_state_reg = '1;
wire [31:0] crc_next; wire [31:0] crc_state_next;
wire [3:0] crc_valid; wire [3:0] crc_valid;
logic [3:0] crc_valid_save; logic [3:0] crc_valid_save;
assign crc_valid[3] = crc_next == ~32'h2144df1c; assign crc_valid[3] = crc_state_next == ~32'h2144df1c;
assign crc_valid[2] = crc_next == ~32'hc622f71d; assign crc_valid[2] = crc_state_next == ~32'hc622f71d;
assign crc_valid[1] = crc_next == ~32'hb1c2a1a3; assign crc_valid[1] = crc_state_next == ~32'hb1c2a1a3;
assign crc_valid[0] = crc_next == ~32'h9d6cdf7e; assign crc_valid[0] = crc_state_next == ~32'h9d6cdf7e;
assign m_axis_rx.tdata = m_axis_rx_tdata_reg; assign m_axis_rx.tdata = m_axis_rx_tdata_reg;
assign m_axis_rx.tkeep = m_axis_rx_tkeep_reg; assign m_axis_rx.tkeep = m_axis_rx_tkeep_reg;
@@ -263,9 +263,9 @@ taxi_lfsr #(
) )
eth_crc ( eth_crc (
.data_in(input_data_d0), .data_in(input_data_d0),
.state_in(crc_state), .state_in(crc_state_reg),
.data_out(), .data_out(),
.state_out(crc_next) .state_out(crc_state_next)
); );
always_comb begin always_comb begin
@@ -774,9 +774,9 @@ always_ff @(posedge clk) begin
end end
if (reset_crc) begin if (reset_crc) begin
crc_state <= '1; crc_state_reg <= '1;
end else begin end else begin
crc_state <= crc_next; crc_state_reg <= crc_state_next;
end end
crc_valid_save <= crc_valid; crc_valid_save <= crc_valid;

28
src/eth/rtl/taxi_axis_baser_rx_64.sv
View File

@@ -215,21 +215,21 @@ logic [PTP_TS_W-1:0] ptp_ts_out_reg = '0, ptp_ts_out_next;
logic [PTP_TS_W-1:0] ptp_ts_adj_reg = '0; logic [PTP_TS_W-1:0] ptp_ts_adj_reg = '0;
logic ptp_ts_borrow_reg = '0; logic ptp_ts_borrow_reg = '0;
logic [31:0] crc_state = '1; logic [31:0] crc_state_reg = '1;
wire [31:0] crc_next; wire [31:0] crc_state_next;
wire [7:0] crc_valid; wire [7:0] crc_valid;
logic [7:0] crc_valid_save; logic [7:0] crc_valid_save;
assign crc_valid[7] = crc_next == ~32'h2144df1c; assign crc_valid[7] = crc_state_next == ~32'h2144df1c;
assign crc_valid[6] = crc_next == ~32'hc622f71d; assign crc_valid[6] = crc_state_next == ~32'hc622f71d;
assign crc_valid[5] = crc_next == ~32'hb1c2a1a3; assign crc_valid[5] = crc_state_next == ~32'hb1c2a1a3;
assign crc_valid[4] = crc_next == ~32'h9d6cdf7e; assign crc_valid[4] = crc_state_next == ~32'h9d6cdf7e;
assign crc_valid[3] = crc_next == ~32'h6522df69; assign crc_valid[3] = crc_state_next == ~32'h6522df69;
assign crc_valid[2] = crc_next == ~32'he60914ae; assign crc_valid[2] = crc_state_next == ~32'he60914ae;
assign crc_valid[1] = crc_next == ~32'he38a6876; assign crc_valid[1] = crc_state_next == ~32'he38a6876;
assign crc_valid[0] = crc_next == ~32'h6b87b1ec; assign crc_valid[0] = crc_state_next == ~32'h6b87b1ec;
logic [4+16-1:0] last_ts_reg = '0; logic [4+16-1:0] last_ts_reg = '0;
logic [4+16-1:0] ts_inc_reg = '0; logic [4+16-1:0] ts_inc_reg = '0;
@@ -276,9 +276,9 @@ taxi_lfsr #(
) )
eth_crc ( eth_crc (
.data_in(input_data_d0), .data_in(input_data_d0),
.state_in(crc_state), .state_in(crc_state_reg),
.data_out(), .data_out(),
.state_out(crc_next) .state_out(crc_state_next)
); );
// Mask input data // Mask input data
@@ -837,9 +837,9 @@ always_ff @(posedge clk) begin
input_data_d1 <= input_data_d0; input_data_d1 <= input_data_d0;
if (reset_crc) begin if (reset_crc) begin
crc_state <= '1; crc_state_reg <= '1;
end else begin end else begin
crc_state <= crc_next; crc_state_reg <= crc_state_next;
end end
crc_valid_save <= crc_valid; crc_valid_save <= crc_valid;

20
src/eth/rtl/taxi_axis_xgmii_rx_32.sv
View File

@@ -160,17 +160,17 @@ logic stat_rx_err_preamble_reg = 1'b0, stat_rx_err_preamble_next;
logic [PTP_TS_W-1:0] ptp_ts_out_reg = '0, ptp_ts_out_next; logic [PTP_TS_W-1:0] ptp_ts_out_reg = '0, ptp_ts_out_next;
logic [31:0] crc_state = '1; logic [31:0] crc_state_reg = '1;
wire [31:0] crc_next; wire [31:0] crc_state_next;
wire [3:0] crc_valid; wire [3:0] crc_valid;
logic [3:0] crc_valid_save; logic [3:0] crc_valid_save;
assign crc_valid[3] = crc_next == ~32'h2144df1c; assign crc_valid[3] = crc_state_next == ~32'h2144df1c;
assign crc_valid[2] = crc_next == ~32'hc622f71d; assign crc_valid[2] = crc_state_next == ~32'hc622f71d;
assign crc_valid[1] = crc_next == ~32'hb1c2a1a3; assign crc_valid[1] = crc_state_next == ~32'hb1c2a1a3;
assign crc_valid[0] = crc_next == ~32'h9d6cdf7e; assign crc_valid[0] = crc_state_next == ~32'h9d6cdf7e;
assign m_axis_rx.tdata = m_axis_rx_tdata_reg; assign m_axis_rx.tdata = m_axis_rx_tdata_reg;
assign m_axis_rx.tkeep = m_axis_rx_tkeep_reg; assign m_axis_rx.tkeep = m_axis_rx_tkeep_reg;
@@ -216,9 +216,9 @@ taxi_lfsr #(
) )
eth_crc ( eth_crc (
.data_in(xgmii_rxd_d0), .data_in(xgmii_rxd_d0),
.state_in(crc_state), .state_in(crc_state_reg),
.data_out(), .data_out(),
.state_out(crc_next) .state_out(crc_state_next)
); );
always_comb begin always_comb begin
@@ -539,9 +539,9 @@ always_ff @(posedge clk) begin
term_lane_d0_reg <= term_lane_reg; term_lane_d0_reg <= term_lane_reg;
if (reset_crc) begin if (reset_crc) begin
crc_state <= '1; crc_state_reg <= '1;
end else begin end else begin
crc_state <= crc_next; crc_state_reg <= crc_state_next;
end end
crc_valid_save <= crc_valid; crc_valid_save <= crc_valid;

28
src/eth/rtl/taxi_axis_xgmii_rx_64.sv
View File

@@ -167,21 +167,21 @@ logic [PTP_TS_W-1:0] ptp_ts_out_reg = '0, ptp_ts_out_next;
logic [PTP_TS_W-1:0] ptp_ts_adj_reg = '0; logic [PTP_TS_W-1:0] ptp_ts_adj_reg = '0;
logic ptp_ts_borrow_reg = '0; logic ptp_ts_borrow_reg = '0;
logic [31:0] crc_state = '1; logic [31:0] crc_state_reg = '1;
wire [31:0] crc_next; wire [31:0] crc_state_next;
wire [7:0] crc_valid; wire [7:0] crc_valid;
logic [7:0] crc_valid_save; logic [7:0] crc_valid_save;
assign crc_valid[7] = crc_next == ~32'h2144df1c; assign crc_valid[7] = crc_state_next == ~32'h2144df1c;
assign crc_valid[6] = crc_next == ~32'hc622f71d; assign crc_valid[6] = crc_state_next == ~32'hc622f71d;
assign crc_valid[5] = crc_next == ~32'hb1c2a1a3; assign crc_valid[5] = crc_state_next == ~32'hb1c2a1a3;
assign crc_valid[4] = crc_next == ~32'h9d6cdf7e; assign crc_valid[4] = crc_state_next == ~32'h9d6cdf7e;
assign crc_valid[3] = crc_next == ~32'h6522df69; assign crc_valid[3] = crc_state_next == ~32'h6522df69;
assign crc_valid[2] = crc_next == ~32'he60914ae; assign crc_valid[2] = crc_state_next == ~32'he60914ae;
assign crc_valid[1] = crc_next == ~32'he38a6876; assign crc_valid[1] = crc_state_next == ~32'he38a6876;
assign crc_valid[0] = crc_next == ~32'h6b87b1ec; assign crc_valid[0] = crc_state_next == ~32'h6b87b1ec;
logic [4+16-1:0] last_ts_reg = '0; logic [4+16-1:0] last_ts_reg = '0;
logic [4+16-1:0] ts_inc_reg = '0; logic [4+16-1:0] ts_inc_reg = '0;
@@ -228,9 +228,9 @@ taxi_lfsr #(
) )
eth_crc ( eth_crc (
.data_in(xgmii_rxd_d0), .data_in(xgmii_rxd_d0),
.state_in(crc_state), .state_in(crc_state_reg),
.data_out(), .data_out(),
.state_out(crc_next) .state_out(crc_state_next)
); );
// Mask input data // Mask input data
@@ -618,9 +618,9 @@ always_ff @(posedge clk) begin
framing_error_d0_reg <= framing_error_reg; framing_error_d0_reg <= framing_error_reg;
if (reset_crc) begin if (reset_crc) begin
crc_state <= '1; crc_state_reg <= '1;
end else begin end else begin
crc_state <= crc_next; crc_state_reg <= crc_state_next;
end end
crc_valid_save <= crc_valid; crc_valid_save <= crc_valid;