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axi: Add AXI lite to APB adapter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
@@ -38,6 +38,7 @@ To facilitate the dual-license model, contributions to the project can only be a
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* AXI lite
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* SV interface for AXI lite
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* AXI lite to AXI adapter
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* AXI lite to APB adapter
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* Register slice
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* Width converter
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* Single-port RAM
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737
src/axi/rtl/taxi_axil_apb_adapter.sv
Normal file
737
src/axi/rtl/taxi_axil_apb_adapter.sv
Normal file
@@ -0,0 +1,737 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4 lite to APB adapter
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*/
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module taxi_axil_apb_adapter
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* AXI4-Lite slave interface
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*/
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taxi_axil_if.wr_slv s_axil_wr,
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taxi_axil_if.rd_slv s_axil_rd,
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/*
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* APB master interface
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*/
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taxi_apb_if.mst m_apb
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);
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// extract parameters
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localparam AXIL_DATA_W = s_axil_rd.DATA_W;
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localparam AXIL_ADDR_W = s_axil_rd.ADDR_W;
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localparam AXIL_STRB_W = s_axil_rd.STRB_W;
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localparam logic AWUSER_EN = s_axil_wr.AWUSER_EN && m_apb.PAUSER_EN;
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localparam AWUSER_W = s_axil_wr.AWUSER_W;
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localparam logic WUSER_EN = s_axil_wr.WUSER_EN && m_apb.PWUSER_EN;
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localparam WUSER_W = s_axil_wr.WUSER_W;
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localparam logic BUSER_EN = s_axil_wr.BUSER_EN && m_apb.PBUSER_EN;
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localparam BUSER_W = s_axil_wr.BUSER_W;
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localparam logic ARUSER_EN = s_axil_rd.ARUSER_EN && m_apb.PAUSER_EN;
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localparam ARUSER_W = s_axil_rd.ARUSER_W;
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localparam logic RUSER_EN = s_axil_rd.RUSER_EN && m_apb.PRUSER_EN;
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localparam RUSER_W = s_axil_rd.RUSER_W;
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localparam APB_DATA_W = m_apb.DATA_W;
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localparam APB_ADDR_W = m_apb.ADDR_W;
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localparam APB_STRB_W = m_apb.STRB_W;
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localparam logic PAUSER_EN = (s_axil_wr.AWUSER_EN || s_axil_wr.ARUSER_EN) && m_apb.PAUSER_EN;
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localparam PAUSER_W = m_apb.PAUSER_W;
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localparam logic PWUSER_EN = s_axil_wr.WUSER_EN && m_apb.PWUSER_EN;
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localparam PWUSER_W = m_apb.PWUSER_W;
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localparam logic PRUSER_EN = s_axil_rd.RUSER_EN && m_apb.PRUSER_EN;
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localparam PRUSER_W = m_apb.PRUSER_W;
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localparam logic PBUSER_EN = s_axil_wr.BUSER_EN && m_apb.PBUSER_EN;
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localparam PBUSER_W = m_apb.PBUSER_W;
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localparam AXIL_ADDR_BIT_OFFSET = $clog2(AXIL_STRB_W);
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localparam APB_ADDR_BIT_OFFSET = $clog2(APB_STRB_W);
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localparam AXIL_BYTE_LANES = AXIL_STRB_W;
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localparam APB_BYTE_LANES = APB_STRB_W;
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localparam AXIL_BYTE_W = AXIL_DATA_W/AXIL_BYTE_LANES;
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localparam APB_BYTE_W = APB_DATA_W/APB_BYTE_LANES;
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localparam AXIL_ADDR_MASK = {AXIL_ADDR_W{1'b1}} << AXIL_ADDR_BIT_OFFSET;
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localparam APB_ADDR_MASK = {APB_ADDR_W{1'b1}} << APB_ADDR_BIT_OFFSET;
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// check configuration
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if (AXIL_BYTE_W * AXIL_STRB_W != AXIL_DATA_W)
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$fatal(0, "Error: AXI slave interface data width not evenly divisible (instance %m)");
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if (APB_BYTE_W * APB_STRB_W != APB_DATA_W)
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$fatal(0, "Error: AXI master interface data width not evenly divisible (instance %m)");
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if (AXIL_BYTE_W != APB_BYTE_W)
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$fatal(0, "Error: byte size mismatch (instance %m)");
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if (2**$clog2(AXIL_BYTE_LANES) != AXIL_BYTE_LANES)
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$fatal(0, "Error: AXI slave interface byte lane count must be even power of two (instance %m)");
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if (2**$clog2(APB_BYTE_LANES) != APB_BYTE_LANES)
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$fatal(0, "Error: APB master interface byte lane count must be even power of two (instance %m)");
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if (s_axil_wr.DATA_W != s_axil_rd.DATA_W)
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$fatal(0, "Error: AXI interface configuration mismatch (instance %m)");
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localparam [1:0]
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AXI_RESP_OKAY = 2'b00,
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AXI_RESP_EXOKAY = 2'b01,
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AXI_RESP_SLVERR = 2'b10,
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AXI_RESP_DECERR = 2'b11;
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if (APB_BYTE_LANES == AXIL_BYTE_LANES) begin : translate
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// same width; translate
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localparam [0:0]
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STATE_IDLE = 1'd0,
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STATE_DATA = 1'd1;
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logic [0:0] state_reg = STATE_IDLE, state_next;
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logic last_read_reg = 1'b0, last_read_next;
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logic s_axil_awready_reg = 1'b0, s_axil_awready_next;
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logic s_axil_wready_reg = 1'b0, s_axil_wready_next;
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logic [BUSER_W-1:0] s_axil_buser_reg = '0, s_axil_buser_next;
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logic s_axil_bvalid_reg = 1'b0, s_axil_bvalid_next;
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logic s_axil_arready_reg = 1'b0, s_axil_arready_next;
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logic [AXIL_DATA_W-1:0] s_axil_rdata_reg = '0, s_axil_rdata_next;
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logic [RUSER_W-1:0] s_axil_ruser_reg = '0, s_axil_ruser_next;
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logic s_axil_rvalid_reg = 1'b0, s_axil_rvalid_next;
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logic [1:0] s_axil_resp_reg = '0, s_axil_resp_next;
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logic [APB_ADDR_W-1:0] m_apb_paddr_reg = '0, m_apb_paddr_next;
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logic [2:0] m_apb_pprot_reg = '0, m_apb_pprot_next;
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logic m_apb_psel_reg = 1'b0, m_apb_psel_next;
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logic m_apb_penable_reg = 1'b0, m_apb_penable_next;
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logic m_apb_pwrite_reg = 1'b0, m_apb_pwrite_next;
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logic [APB_DATA_W-1:0] m_apb_pwdata_reg = '0, m_apb_pwdata_next;
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logic [APB_STRB_W-1:0] m_apb_pstrb_reg = '0, m_apb_pstrb_next;
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logic [PAUSER_W-1:0] m_apb_pauser_reg = '0, m_apb_pauser_next;
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logic [PWUSER_W-1:0] m_apb_pwuser_reg = '0, m_apb_pwuser_next;
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assign s_axil_wr.awready = s_axil_awready_reg;
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assign s_axil_wr.wready = s_axil_wready_reg;
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assign s_axil_wr.bresp = s_axil_resp_reg;
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assign s_axil_wr.buser = BUSER_EN ? s_axil_buser_reg : '0;
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assign s_axil_wr.bvalid = s_axil_bvalid_reg;
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assign s_axil_rd.arready = s_axil_arready_reg;
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assign s_axil_rd.rdata = s_axil_rdata_reg;
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assign s_axil_rd.rresp = s_axil_resp_reg;
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assign s_axil_rd.ruser = RUSER_EN ? s_axil_ruser_reg : '0;
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assign s_axil_rd.rvalid = s_axil_rvalid_reg;
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assign m_apb.paddr = m_apb_paddr_reg;
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assign m_apb.pprot = m_apb_pprot_reg;
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assign m_apb.psel = m_apb_psel_reg;
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assign m_apb.penable = m_apb_penable_reg;
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assign m_apb.pwrite = m_apb_pwrite_reg;
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assign m_apb.pwdata = m_apb_pwdata_reg;
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assign m_apb.pstrb = m_apb_pstrb_reg;
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assign m_apb.pauser = PAUSER_EN ? m_apb_pauser_reg : '0;
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assign m_apb.pwuser = PWUSER_EN ? m_apb_pwuser_reg : '0;
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logic read_eligible;
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logic write_eligible;
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always_comb begin
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state_next = STATE_IDLE;
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last_read_next = last_read_reg;
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s_axil_awready_next = 1'b0;
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s_axil_wready_next = 1'b0;
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s_axil_buser_next = s_axil_buser_reg;
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s_axil_bvalid_next = s_axil_bvalid_reg && !s_axil_wr.bready;
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s_axil_arready_next = 1'b0;
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s_axil_rdata_next = s_axil_rdata_reg;
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s_axil_ruser_next = s_axil_ruser_reg;
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s_axil_rvalid_next = s_axil_rvalid_reg && !s_axil_rd.rready;
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s_axil_resp_next = s_axil_resp_reg;
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m_apb_paddr_next = m_apb_paddr_reg;
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m_apb_pprot_next = m_apb_pprot_reg;
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m_apb_psel_next = m_apb_psel_reg;
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m_apb_penable_next = m_apb_penable_reg;
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m_apb_pwrite_next = m_apb_pwrite_reg;
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m_apb_pwdata_next = m_apb_pwdata_reg;
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m_apb_pstrb_next = m_apb_pstrb_reg;
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m_apb_pauser_next = m_apb_pauser_reg;
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m_apb_pwuser_next = m_apb_pwuser_reg;
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write_eligible = s_axil_wr.awvalid && s_axil_wr.wvalid && (!s_axil_wr.bvalid || s_axil_wr.bready) && (!s_axil_wr.awready && !s_axil_wr.wready);
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read_eligible = s_axil_rd.arvalid && (!s_axil_rd.rvalid || s_axil_rd.rready) && (!s_axil_rd.arready);
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case (state_reg)
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STATE_IDLE: begin
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m_apb_pwdata_next = s_axil_wr.wdata;
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m_apb_pstrb_next = s_axil_wr.wstrb;
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m_apb_pwuser_next = s_axil_wr.wuser;
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if (write_eligible && (!read_eligible || last_read_reg)) begin
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// start write
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last_read_next = 1'b0;
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s_axil_awready_next = 1'b1;
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s_axil_wready_next = 1'b1;
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m_apb_paddr_next = APB_ADDR_W'(s_axil_wr.awaddr);
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m_apb_pprot_next = s_axil_wr.awprot;
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m_apb_pauser_next = s_axil_wr.awuser;
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m_apb_pwrite_next = 1'b1;
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m_apb_psel_next = 1'b1;
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state_next = STATE_DATA;
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end else if (read_eligible) begin
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// start read
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last_read_next = 1'b1;
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s_axil_arready_next = 1'b1;
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m_apb_paddr_next = APB_ADDR_W'(s_axil_rd.araddr);
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m_apb_pprot_next = s_axil_rd.arprot;
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m_apb_pauser_next = s_axil_rd.aruser;
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m_apb_pwrite_next = 1'b0;
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m_apb_psel_next = 1'b1;
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state_next = STATE_DATA;
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end else begin
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state_next = STATE_IDLE;
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end
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end
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STATE_DATA: begin
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s_axil_buser_next = m_apb.pbuser;
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s_axil_rdata_next = m_apb.prdata;
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s_axil_ruser_next = m_apb.pruser;
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s_axil_resp_next = m_apb.pslverr ? AXI_RESP_SLVERR : AXI_RESP_OKAY;
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m_apb_psel_next = 1'b1;
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m_apb_penable_next = 1'b1;
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if (m_apb.psel && m_apb.penable && m_apb.pready) begin
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if (m_apb_pwrite_reg) begin
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s_axil_bvalid_next = 1'b1;
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end else begin
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s_axil_rvalid_next = 1'b1;
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end
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m_apb_psel_next = 1'b0;
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m_apb_penable_next = 1'b0;
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state_next = STATE_IDLE;
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end else begin
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state_next = STATE_DATA;
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end
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end
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default: begin
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state_next = STATE_IDLE;
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end
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endcase
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end
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always @(posedge clk) begin
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state_reg <= state_next;
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last_read_reg <= last_read_next;
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s_axil_awready_reg <= s_axil_awready_next;
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s_axil_wready_reg <= s_axil_wready_next;
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s_axil_buser_reg <= s_axil_buser_next;
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s_axil_bvalid_reg <= s_axil_bvalid_next;
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s_axil_arready_reg <= s_axil_arready_next;
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s_axil_rdata_reg <= s_axil_rdata_next;
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s_axil_ruser_reg <= s_axil_ruser_next;
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s_axil_rvalid_reg <= s_axil_rvalid_next;
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s_axil_resp_reg <= s_axil_resp_next;
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m_apb_paddr_reg <= m_apb_paddr_next;
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m_apb_pprot_reg <= m_apb_pprot_next;
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m_apb_psel_reg <= m_apb_psel_next;
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m_apb_penable_reg <= m_apb_penable_next;
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m_apb_pwrite_reg <= m_apb_pwrite_next;
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m_apb_pwdata_reg <= m_apb_pwdata_next;
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m_apb_pstrb_reg <= m_apb_pstrb_next;
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m_apb_pauser_reg <= m_apb_pauser_next;
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m_apb_pwuser_reg <= m_apb_pwuser_next;
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if (rst) begin
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state_reg <= STATE_IDLE;
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last_read_reg <= 1'b0;
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s_axil_awready_reg <= 1'b0;
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s_axil_wready_reg <= 1'b0;
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s_axil_bvalid_reg <= 1'b0;
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s_axil_arready_reg <= 1'b0;
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s_axil_rvalid_reg <= 1'b0;
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m_apb_psel_reg <= 1'b0;
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m_apb_penable_reg <= 1'b0;
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end
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end
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end else if (APB_BYTE_LANES > AXIL_BYTE_LANES) begin : upsize
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// output is wider; upsize
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localparam [0:0]
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STATE_IDLE = 1'd0,
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STATE_DATA = 1'd1;
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logic [0:0] state_reg = STATE_IDLE, state_next;
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logic last_read_reg = 1'b0, last_read_next;
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logic s_axil_awready_reg = 1'b0, s_axil_awready_next;
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logic s_axil_wready_reg = 1'b0, s_axil_wready_next;
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logic [BUSER_W-1:0] s_axil_buser_reg = '0, s_axil_buser_next;
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logic s_axil_bvalid_reg = 1'b0, s_axil_bvalid_next;
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logic s_axil_arready_reg = 1'b0, s_axil_arready_next;
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logic [AXIL_DATA_W-1:0] s_axil_rdata_reg = '0, s_axil_rdata_next;
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logic [RUSER_W-1:0] s_axil_ruser_reg = '0, s_axil_ruser_next;
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logic s_axil_rvalid_reg = 1'b0, s_axil_rvalid_next;
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logic [1:0] s_axil_resp_reg = '0, s_axil_resp_next;
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logic [APB_ADDR_W-1:0] m_apb_paddr_reg = '0, m_apb_paddr_next;
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logic [2:0] m_apb_pprot_reg = '0, m_apb_pprot_next;
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logic m_apb_psel_reg = 1'b0, m_apb_psel_next;
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logic m_apb_penable_reg = 1'b0, m_apb_penable_next;
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logic m_apb_pwrite_reg = 1'b0, m_apb_pwrite_next;
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logic [APB_DATA_W-1:0] m_apb_pwdata_reg = '0, m_apb_pwdata_next;
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logic [APB_STRB_W-1:0] m_apb_pstrb_reg = '0, m_apb_pstrb_next;
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logic [PAUSER_W-1:0] m_apb_pauser_reg = '0, m_apb_pauser_next;
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logic [PWUSER_W-1:0] m_apb_pwuser_reg = '0, m_apb_pwuser_next;
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assign s_axil_wr.awready = s_axil_awready_reg;
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assign s_axil_wr.wready = s_axil_wready_reg;
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assign s_axil_wr.bresp = s_axil_resp_reg;
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assign s_axil_wr.buser = BUSER_EN ? s_axil_buser_reg : '0;
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assign s_axil_wr.bvalid = s_axil_bvalid_reg;
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assign s_axil_rd.arready = s_axil_arready_reg;
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assign s_axil_rd.rdata = s_axil_rdata_reg;
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assign s_axil_rd.rresp = s_axil_resp_reg;
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assign s_axil_rd.ruser = RUSER_EN ? s_axil_ruser_reg : '0;
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assign s_axil_rd.rvalid = s_axil_rvalid_reg;
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assign m_apb.paddr = m_apb_paddr_reg;
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assign m_apb.pprot = m_apb_pprot_reg;
|
||||
assign m_apb.psel = m_apb_psel_reg;
|
||||
assign m_apb.penable = m_apb_penable_reg;
|
||||
assign m_apb.pwrite = m_apb_pwrite_reg;
|
||||
assign m_apb.pwdata = m_apb_pwdata_reg;
|
||||
assign m_apb.pstrb = m_apb_pstrb_reg;
|
||||
assign m_apb.pauser = PAUSER_EN ? m_apb_pauser_reg : '0;
|
||||
assign m_apb.pwuser = PWUSER_EN ? m_apb_pwuser_reg : '0;
|
||||
|
||||
logic read_eligible;
|
||||
logic write_eligible;
|
||||
|
||||
always_comb begin
|
||||
state_next = STATE_IDLE;
|
||||
|
||||
last_read_next = last_read_reg;
|
||||
|
||||
s_axil_awready_next = 1'b0;
|
||||
s_axil_wready_next = 1'b0;
|
||||
s_axil_buser_next = s_axil_buser_reg;
|
||||
s_axil_bvalid_next = s_axil_bvalid_reg && !s_axil_wr.bready;
|
||||
|
||||
s_axil_arready_next = 1'b0;
|
||||
s_axil_rdata_next = s_axil_rdata_reg;
|
||||
s_axil_ruser_next = s_axil_ruser_reg;
|
||||
s_axil_rvalid_next = s_axil_rvalid_reg && !s_axil_rd.rready;
|
||||
|
||||
s_axil_resp_next = s_axil_resp_reg;
|
||||
|
||||
m_apb_paddr_next = m_apb_paddr_reg;
|
||||
m_apb_pprot_next = m_apb_pprot_reg;
|
||||
m_apb_psel_next = m_apb_psel_reg;
|
||||
m_apb_penable_next = m_apb_penable_reg;
|
||||
m_apb_pwrite_next = m_apb_pwrite_reg;
|
||||
m_apb_pwdata_next = m_apb_pwdata_reg;
|
||||
m_apb_pstrb_next = m_apb_pstrb_reg;
|
||||
m_apb_pauser_next = m_apb_pauser_reg;
|
||||
m_apb_pwuser_next = m_apb_pwuser_reg;
|
||||
|
||||
write_eligible = s_axil_wr.awvalid && s_axil_wr.wvalid && (!s_axil_wr.bvalid || s_axil_wr.bready) && (!s_axil_wr.awready && !s_axil_wr.wready);
|
||||
read_eligible = s_axil_rd.arvalid && (!s_axil_rd.rvalid || s_axil_rd.rready) && (!s_axil_rd.arready);
|
||||
|
||||
case (state_reg)
|
||||
STATE_IDLE: begin
|
||||
m_apb_pwdata_next = {(APB_BYTE_LANES/AXIL_BYTE_LANES){s_axil_wr.wdata}};
|
||||
m_apb_pstrb_next = '0;
|
||||
m_apb_pstrb_next[s_axil_wr.awaddr[APB_ADDR_BIT_OFFSET - 1:AXIL_ADDR_BIT_OFFSET] * AXIL_STRB_W +: AXIL_STRB_W] = s_axil_wr.wstrb;
|
||||
m_apb_pwuser_next = s_axil_wr.wuser;
|
||||
|
||||
if (write_eligible && (!read_eligible || last_read_reg)) begin
|
||||
// start write
|
||||
last_read_next = 1'b0;
|
||||
|
||||
s_axil_awready_next = 1'b1;
|
||||
s_axil_wready_next = 1'b1;
|
||||
|
||||
m_apb_paddr_next = APB_ADDR_W'(s_axil_wr.awaddr);
|
||||
m_apb_pprot_next = s_axil_wr.awprot;
|
||||
m_apb_pauser_next = s_axil_wr.awuser;
|
||||
m_apb_pwrite_next = 1'b1;
|
||||
m_apb_psel_next = 1'b1;
|
||||
|
||||
state_next = STATE_DATA;
|
||||
end else if (read_eligible) begin
|
||||
// start read
|
||||
last_read_next = 1'b1;
|
||||
|
||||
s_axil_arready_next = 1'b1;
|
||||
|
||||
m_apb_paddr_next = APB_ADDR_W'(s_axil_rd.araddr);
|
||||
m_apb_pprot_next = s_axil_rd.arprot;
|
||||
m_apb_pauser_next = s_axil_rd.aruser;
|
||||
m_apb_pwrite_next = 1'b0;
|
||||
m_apb_psel_next = 1'b1;
|
||||
|
||||
state_next = STATE_DATA;
|
||||
end else begin
|
||||
state_next = STATE_IDLE;
|
||||
end
|
||||
end
|
||||
STATE_DATA: begin
|
||||
s_axil_buser_next = m_apb.pbuser;
|
||||
s_axil_rdata_next = m_apb.prdata[m_apb_paddr_reg[APB_ADDR_BIT_OFFSET - 1:AXIL_ADDR_BIT_OFFSET] * AXIL_DATA_W +: AXIL_DATA_W];
|
||||
s_axil_ruser_next = m_apb.pruser;
|
||||
s_axil_resp_next = m_apb.pslverr ? AXI_RESP_SLVERR : AXI_RESP_OKAY;
|
||||
|
||||
m_apb_psel_next = 1'b1;
|
||||
m_apb_penable_next = 1'b1;
|
||||
|
||||
if (m_apb.psel && m_apb.penable && m_apb.pready) begin
|
||||
if (m_apb_pwrite_reg) begin
|
||||
s_axil_bvalid_next = 1'b1;
|
||||
end else begin
|
||||
s_axil_rvalid_next = 1'b1;
|
||||
end
|
||||
|
||||
m_apb_psel_next = 1'b0;
|
||||
m_apb_penable_next = 1'b0;
|
||||
|
||||
state_next = STATE_IDLE;
|
||||
end else begin
|
||||
state_next = STATE_DATA;
|
||||
end
|
||||
end
|
||||
default: begin
|
||||
state_next = STATE_IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
state_reg <= state_next;
|
||||
|
||||
last_read_reg <= last_read_next;
|
||||
|
||||
s_axil_awready_reg <= s_axil_awready_next;
|
||||
s_axil_wready_reg <= s_axil_wready_next;
|
||||
s_axil_buser_reg <= s_axil_buser_next;
|
||||
s_axil_bvalid_reg <= s_axil_bvalid_next;
|
||||
|
||||
s_axil_arready_reg <= s_axil_arready_next;
|
||||
s_axil_rdata_reg <= s_axil_rdata_next;
|
||||
s_axil_ruser_reg <= s_axil_ruser_next;
|
||||
s_axil_rvalid_reg <= s_axil_rvalid_next;
|
||||
|
||||
s_axil_resp_reg <= s_axil_resp_next;
|
||||
|
||||
m_apb_paddr_reg <= m_apb_paddr_next;
|
||||
m_apb_pprot_reg <= m_apb_pprot_next;
|
||||
m_apb_psel_reg <= m_apb_psel_next;
|
||||
m_apb_penable_reg <= m_apb_penable_next;
|
||||
m_apb_pwrite_reg <= m_apb_pwrite_next;
|
||||
m_apb_pwdata_reg <= m_apb_pwdata_next;
|
||||
m_apb_pstrb_reg <= m_apb_pstrb_next;
|
||||
m_apb_pauser_reg <= m_apb_pauser_next;
|
||||
m_apb_pwuser_reg <= m_apb_pwuser_next;
|
||||
|
||||
if (rst) begin
|
||||
state_reg <= STATE_IDLE;
|
||||
|
||||
last_read_reg <= 1'b0;
|
||||
|
||||
s_axil_awready_reg <= 1'b0;
|
||||
s_axil_wready_reg <= 1'b0;
|
||||
s_axil_bvalid_reg <= 1'b0;
|
||||
s_axil_arready_reg <= 1'b0;
|
||||
s_axil_rvalid_reg <= 1'b0;
|
||||
|
||||
m_apb_psel_reg <= 1'b0;
|
||||
m_apb_penable_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin : downsize
|
||||
// output is narrower; downsize
|
||||
|
||||
// output bus is wider
|
||||
localparam DATA_W = AXIL_DATA_W;
|
||||
localparam STRB_W = AXIL_STRB_W;
|
||||
// required number of segments in wider bus
|
||||
localparam SEG_COUNT = AXIL_BYTE_LANES / APB_BYTE_LANES;
|
||||
localparam SEG_COUNT_W = $clog2(SEG_COUNT);
|
||||
// data width and keep width per segment
|
||||
localparam SEG_DATA_W = DATA_W / SEG_COUNT;
|
||||
localparam SEG_STRB_W = STRB_W / SEG_COUNT;
|
||||
|
||||
localparam [0:0]
|
||||
STATE_IDLE = 1'd0,
|
||||
STATE_DATA = 1'd1;
|
||||
|
||||
logic [0:0] state_reg = STATE_IDLE, state_next;
|
||||
|
||||
logic last_read_reg = 1'b0, last_read_next;
|
||||
|
||||
logic [DATA_W-1:0] data_reg = '0, data_next;
|
||||
logic [STRB_W-1:0] strb_reg = '0, strb_next;
|
||||
|
||||
logic [SEG_COUNT_W-1:0] current_seg_reg = '0, current_seg_next;
|
||||
|
||||
logic s_axil_awready_reg = 1'b0, s_axil_awready_next;
|
||||
logic s_axil_wready_reg = 1'b0, s_axil_wready_next;
|
||||
logic [BUSER_W-1:0] s_axil_buser_reg = '0, s_axil_buser_next;
|
||||
logic s_axil_bvalid_reg = 1'b0, s_axil_bvalid_next;
|
||||
|
||||
logic s_axil_arready_reg = 1'b0, s_axil_arready_next;
|
||||
logic [AXIL_DATA_W-1:0] s_axil_rdata_reg = '0, s_axil_rdata_next;
|
||||
logic [RUSER_W-1:0] s_axil_ruser_reg = '0, s_axil_ruser_next;
|
||||
logic s_axil_rvalid_reg = 1'b0, s_axil_rvalid_next;
|
||||
|
||||
logic [1:0] s_axil_resp_reg = '0, s_axil_resp_next;
|
||||
|
||||
logic [APB_ADDR_W-1:0] m_apb_paddr_reg = '0, m_apb_paddr_next;
|
||||
logic [2:0] m_apb_pprot_reg = '0, m_apb_pprot_next;
|
||||
logic m_apb_psel_reg = 1'b0, m_apb_psel_next;
|
||||
logic m_apb_penable_reg = 1'b0, m_apb_penable_next;
|
||||
logic m_apb_pwrite_reg = 1'b0, m_apb_pwrite_next;
|
||||
logic [APB_DATA_W-1:0] m_apb_pwdata_reg = '0, m_apb_pwdata_next;
|
||||
logic [APB_STRB_W-1:0] m_apb_pstrb_reg = '0, m_apb_pstrb_next;
|
||||
logic [PAUSER_W-1:0] m_apb_pauser_reg = '0, m_apb_pauser_next;
|
||||
logic [PWUSER_W-1:0] m_apb_pwuser_reg = '0, m_apb_pwuser_next;
|
||||
|
||||
assign s_axil_wr.awready = s_axil_awready_reg;
|
||||
assign s_axil_wr.wready = s_axil_wready_reg;
|
||||
assign s_axil_wr.bresp = s_axil_resp_reg;
|
||||
assign s_axil_wr.buser = BUSER_EN ? s_axil_buser_reg : '0;
|
||||
assign s_axil_wr.bvalid = s_axil_bvalid_reg;
|
||||
|
||||
assign s_axil_rd.arready = s_axil_arready_reg;
|
||||
assign s_axil_rd.rdata = s_axil_rdata_reg;
|
||||
assign s_axil_rd.rresp = s_axil_resp_reg;
|
||||
assign s_axil_rd.ruser = RUSER_EN ? s_axil_ruser_reg : '0;
|
||||
assign s_axil_rd.rvalid = s_axil_rvalid_reg;
|
||||
|
||||
assign m_apb.paddr = m_apb_paddr_reg;
|
||||
assign m_apb.pprot = m_apb_pprot_reg;
|
||||
assign m_apb.psel = m_apb_psel_reg;
|
||||
assign m_apb.penable = m_apb_penable_reg;
|
||||
assign m_apb.pwrite = m_apb_pwrite_reg;
|
||||
assign m_apb.pwdata = m_apb_pwdata_reg;
|
||||
assign m_apb.pstrb = m_apb_pstrb_reg;
|
||||
assign m_apb.pauser = PAUSER_EN ? m_apb_pauser_reg : '0;
|
||||
assign m_apb.pwuser = PWUSER_EN ? m_apb_pwuser_reg : '0;
|
||||
|
||||
logic read_eligible;
|
||||
logic write_eligible;
|
||||
|
||||
always_comb begin
|
||||
state_next = STATE_IDLE;
|
||||
|
||||
last_read_next = last_read_reg;
|
||||
|
||||
data_next = data_reg;
|
||||
strb_next = strb_reg;
|
||||
|
||||
current_seg_next = current_seg_reg;
|
||||
|
||||
s_axil_awready_next = 1'b0;
|
||||
s_axil_wready_next = 1'b0;
|
||||
s_axil_buser_next = s_axil_buser_reg;
|
||||
s_axil_bvalid_next = s_axil_bvalid_reg && !s_axil_wr.bready;
|
||||
|
||||
s_axil_arready_next = 1'b0;
|
||||
s_axil_rdata_next = s_axil_rdata_reg;
|
||||
s_axil_ruser_next = s_axil_ruser_reg;
|
||||
s_axil_rvalid_next = s_axil_rvalid_reg && !s_axil_rd.rready;
|
||||
|
||||
s_axil_resp_next = s_axil_resp_reg;
|
||||
|
||||
m_apb_paddr_next = m_apb_paddr_reg;
|
||||
m_apb_pprot_next = m_apb_pprot_reg;
|
||||
m_apb_psel_next = m_apb_psel_reg;
|
||||
m_apb_penable_next = m_apb_penable_reg;
|
||||
m_apb_pwrite_next = m_apb_pwrite_reg;
|
||||
m_apb_pwdata_next = m_apb_pwdata_reg;
|
||||
m_apb_pstrb_next = m_apb_pstrb_reg;
|
||||
m_apb_pauser_next = m_apb_pauser_reg;
|
||||
m_apb_pwuser_next = m_apb_pwuser_reg;
|
||||
|
||||
write_eligible = s_axil_wr.awvalid && s_axil_wr.wvalid && (!s_axil_wr.bvalid || s_axil_wr.bready) && (!s_axil_wr.awready && !s_axil_wr.wready);
|
||||
read_eligible = s_axil_rd.arvalid && (!s_axil_rd.rvalid || s_axil_rd.rready) && (!s_axil_rd.arready);
|
||||
|
||||
case (state_reg)
|
||||
STATE_IDLE: begin
|
||||
data_next = s_axil_wr.wdata;
|
||||
strb_next = s_axil_wr.wstrb;
|
||||
|
||||
s_axil_resp_next = AXI_RESP_OKAY;
|
||||
|
||||
m_apb_pwuser_next = s_axil_wr.wuser;
|
||||
|
||||
if (write_eligible && (!read_eligible || last_read_reg)) begin
|
||||
// start write
|
||||
last_read_next = 1'b0;
|
||||
|
||||
current_seg_next = s_axil_wr.awaddr[APB_ADDR_BIT_OFFSET +: SEG_COUNT_W];
|
||||
|
||||
s_axil_awready_next = 1'b1;
|
||||
s_axil_wready_next = 1'b1;
|
||||
|
||||
m_apb_paddr_next = APB_ADDR_W'(s_axil_wr.awaddr);
|
||||
m_apb_pprot_next = s_axil_wr.awprot;
|
||||
m_apb_pauser_next = s_axil_wr.awuser;
|
||||
m_apb_pwrite_next = 1'b1;
|
||||
m_apb_psel_next = 1'b1;
|
||||
|
||||
state_next = STATE_DATA;
|
||||
end else if (read_eligible) begin
|
||||
// start read
|
||||
last_read_next = 1'b1;
|
||||
|
||||
current_seg_next = s_axil_rd.araddr[APB_ADDR_BIT_OFFSET +: SEG_COUNT_W];
|
||||
|
||||
s_axil_arready_next = 1'b1;
|
||||
|
||||
m_apb_paddr_next = APB_ADDR_W'(s_axil_rd.araddr);
|
||||
m_apb_pprot_next = s_axil_rd.arprot;
|
||||
m_apb_pauser_next = s_axil_rd.aruser;
|
||||
m_apb_pwrite_next = 1'b0;
|
||||
m_apb_psel_next = 1'b1;
|
||||
|
||||
state_next = STATE_DATA;
|
||||
end else begin
|
||||
state_next = STATE_IDLE;
|
||||
end
|
||||
end
|
||||
STATE_DATA: begin
|
||||
m_apb_pwdata_next = data_next[current_seg_reg*SEG_DATA_W +: SEG_DATA_W];
|
||||
m_apb_pstrb_next = strb_next[current_seg_reg*SEG_STRB_W +: SEG_STRB_W];
|
||||
s_axil_buser_next = m_apb.pbuser;
|
||||
s_axil_rdata_next[current_seg_reg*SEG_DATA_W +: SEG_DATA_W] = m_apb.prdata;
|
||||
s_axil_ruser_next = m_apb.pruser;
|
||||
|
||||
m_apb_psel_next = 1'b1;
|
||||
m_apb_penable_next = 1'b1;
|
||||
|
||||
if (m_apb.psel && m_apb.penable && m_apb.pready) begin
|
||||
if (m_apb.pslverr) begin
|
||||
s_axil_resp_next = AXI_RESP_SLVERR;
|
||||
end
|
||||
|
||||
m_apb_paddr_next = (m_apb_paddr_reg & APB_ADDR_MASK) + SEG_STRB_W;
|
||||
m_apb_penable_next = 1'b0;
|
||||
|
||||
current_seg_next = current_seg_reg + 1;
|
||||
|
||||
if (¤t_seg_reg) begin
|
||||
if (m_apb_pwrite_reg) begin
|
||||
s_axil_bvalid_next = 1'b1;
|
||||
end else begin
|
||||
s_axil_rvalid_next = 1'b1;
|
||||
end
|
||||
|
||||
m_apb_psel_next = 1'b0;
|
||||
|
||||
state_next = STATE_IDLE;
|
||||
end else begin
|
||||
state_next = STATE_DATA;
|
||||
end
|
||||
end else begin
|
||||
state_next = STATE_DATA;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
state_reg <= state_next;
|
||||
|
||||
last_read_reg <= last_read_next;
|
||||
|
||||
data_reg <= data_next;
|
||||
strb_reg <= strb_next;
|
||||
|
||||
current_seg_reg <= current_seg_next;
|
||||
|
||||
s_axil_awready_reg <= s_axil_awready_next;
|
||||
s_axil_wready_reg <= s_axil_wready_next;
|
||||
s_axil_buser_reg <= s_axil_buser_next;
|
||||
s_axil_bvalid_reg <= s_axil_bvalid_next;
|
||||
|
||||
s_axil_arready_reg <= s_axil_arready_next;
|
||||
s_axil_rdata_reg <= s_axil_rdata_next;
|
||||
s_axil_ruser_reg <= s_axil_ruser_next;
|
||||
s_axil_rvalid_reg <= s_axil_rvalid_next;
|
||||
|
||||
s_axil_resp_reg <= s_axil_resp_next;
|
||||
|
||||
m_apb_paddr_reg <= m_apb_paddr_next;
|
||||
m_apb_pprot_reg <= m_apb_pprot_next;
|
||||
m_apb_psel_reg <= m_apb_psel_next;
|
||||
m_apb_penable_reg <= m_apb_penable_next;
|
||||
m_apb_pwrite_reg <= m_apb_pwrite_next;
|
||||
m_apb_pwdata_reg <= m_apb_pwdata_next;
|
||||
m_apb_pstrb_reg <= m_apb_pstrb_next;
|
||||
m_apb_pauser_reg <= m_apb_pauser_next;
|
||||
m_apb_pwuser_reg <= m_apb_pwuser_next;
|
||||
|
||||
if (rst) begin
|
||||
state_reg <= STATE_IDLE;
|
||||
|
||||
last_read_reg <= 1'b0;
|
||||
|
||||
s_axil_awready_reg <= 1'b0;
|
||||
s_axil_wready_reg <= 1'b0;
|
||||
s_axil_bvalid_reg <= 1'b0;
|
||||
s_axil_arready_reg <= 1'b0;
|
||||
s_axil_rvalid_reg <= 1'b0;
|
||||
|
||||
m_apb_psel_reg <= 1'b0;
|
||||
m_apb_penable_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
66
src/axi/tb/taxi_axil_apb_adapter/Makefile
Normal file
66
src/axi/tb/taxi_axil_apb_adapter/Makefile
Normal file
@@ -0,0 +1,66 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axil_apb_adapter
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/taxi_axil_if.sv
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/apb/rtl/taxi_apb_if.sv
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_ADDR_W := 32
|
||||
export PARAM_AXIL_DATA_W := 32
|
||||
export PARAM_AXIL_STRB_W := $(shell expr $(PARAM_AXIL_DATA_W) / 8 )
|
||||
export PARAM_APB_DATA_W := 32
|
||||
export PARAM_APB_STRB_W := $(shell expr $(PARAM_APB_DATA_W) / 8 )
|
||||
export PARAM_AWUSER_EN := 0
|
||||
export PARAM_AWUSER_W := 1
|
||||
export PARAM_WUSER_EN := 0
|
||||
export PARAM_WUSER_W := 1
|
||||
export PARAM_BUSER_EN := 0
|
||||
export PARAM_BUSER_W := 1
|
||||
export PARAM_ARUSER_EN := 0
|
||||
export PARAM_ARUSER_W := 1
|
||||
export PARAM_RUSER_EN := 0
|
||||
export PARAM_RUSER_W := 1
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
244
src/axi/tb/taxi_axil_apb_adapter/test_taxi_axil_apb_adapter.py
Normal file
244
src/axi/tb/taxi_axil_apb_adapter/test_taxi_axil_apb_adapter.py
Normal file
@@ -0,0 +1,244 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import random
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge, Timer
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiLiteBus, AxiLiteMaster, ApbBus, ApbRam
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
|
||||
|
||||
self.axil_master = AxiLiteMaster(AxiLiteBus.from_entity(dut.s_axil), dut.clk, dut.rst)
|
||||
self.apb_ram = ApbRam(ApbBus.from_entity(dut.m_apb), dut.clk, dut.rst, size=2**16)
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
self.axil_master.write_if.aw_channel.set_pause_generator(generator())
|
||||
self.axil_master.write_if.w_channel.set_pause_generator(generator())
|
||||
self.axil_master.read_if.ar_channel.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
self.axil_master.write_if.b_channel.set_pause_generator(generator())
|
||||
self.axil_master.read_if.r_channel.set_pause_generator(generator())
|
||||
self.apb_ram.set_pause_generator(generator())
|
||||
|
||||
async def cycle_reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.axil_master.write_if.byte_lanes
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
for length in range(1, byte_lanes*2):
|
||||
for offset in range(byte_lanes):
|
||||
tb.log.info("length %d, offset %d", length, offset)
|
||||
addr = offset+0x1000
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
tb.apb_ram.write(addr-128, b'\xaa'*(length+256))
|
||||
|
||||
await tb.axil_master.write(addr, test_data)
|
||||
|
||||
tb.log.debug("%s", tb.apb_ram.hexdump_str((addr & ~0xf)-16, (((addr & 0xf)+length-1) & ~0xf)+48))
|
||||
|
||||
assert tb.apb_ram.read(addr, length) == test_data
|
||||
assert tb.apb_ram.read(addr-1, 1) == b'\xaa'
|
||||
assert tb.apb_ram.read(addr+length, 1) == b'\xaa'
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.axil_master.write_if.byte_lanes
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
for length in range(1, byte_lanes*2):
|
||||
for offset in range(byte_lanes):
|
||||
tb.log.info("length %d, offset %d", length, offset)
|
||||
addr = offset+0x1000
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
tb.apb_ram.write(addr, test_data)
|
||||
|
||||
data = await tb.axil_master.read(addr, length)
|
||||
|
||||
assert data.data == test_data
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
async def worker(master, offset, aperture, count=16):
|
||||
for k in range(count):
|
||||
length = random.randint(1, min(32, aperture))
|
||||
addr = offset+random.randint(0, aperture-length)
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await Timer(random.randint(1, 100), 'ns')
|
||||
|
||||
await master.write(addr, test_data)
|
||||
|
||||
await Timer(random.randint(1, 100), 'ns')
|
||||
|
||||
data = await master.read(addr, length)
|
||||
assert data.data == test_data
|
||||
|
||||
workers = []
|
||||
|
||||
for k in range(16):
|
||||
workers.append(cocotb.start_soon(worker(tb.axil_master, k*0x1000, 0x1000, count=16)))
|
||||
|
||||
while workers:
|
||||
await workers.pop(0).join()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
if getattr(cocotb, 'top', None) is not None:
|
||||
|
||||
for test in [run_test_write, run_test_read]:
|
||||
|
||||
factory = TestFactory(test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
factory = TestFactory(run_stress_test)
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("apb_data_w", [8, 16, 32])
|
||||
@pytest.mark.parametrize("axil_data_w", [8, 16, 32])
|
||||
def test_taxi_axil_apb_adapter(request, axil_data_w, apb_data_w):
|
||||
dut = "taxi_axil_apb_adapter"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
os.path.join(rtl_dir, "taxi_axil_if.sv"),
|
||||
os.path.join(taxi_src_dir, "apb", "rtl", "taxi_apb_if.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['ADDR_W'] = 32
|
||||
parameters['AXIL_DATA_W'] = axil_data_w
|
||||
parameters['AXIL_STRB_W'] = parameters['AXIL_DATA_W'] // 8
|
||||
parameters['APB_DATA_W'] = apb_data_w
|
||||
parameters['APB_STRB_W'] = parameters['APB_DATA_W'] // 8
|
||||
parameters['AWUSER_EN'] = 0
|
||||
parameters['AWUSER_W'] = 1
|
||||
parameters['WUSER_EN'] = 0
|
||||
parameters['WUSER_W'] = 1
|
||||
parameters['BUSER_EN'] = 0
|
||||
parameters['BUSER_W'] = 1
|
||||
parameters['ARUSER_EN'] = 0
|
||||
parameters['ARUSER_W'] = 1
|
||||
parameters['RUSER_EN'] = 0
|
||||
parameters['RUSER_W'] = 1
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
@@ -0,0 +1,92 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Lite APB adapter testbench
|
||||
*/
|
||||
module test_taxi_axil_apb_adapter #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter ADDR_W = 32,
|
||||
parameter AXIL_DATA_W = 32,
|
||||
parameter AXIL_STRB_W = (AXIL_DATA_W/8),
|
||||
parameter APB_DATA_W = 32,
|
||||
parameter APB_STRB_W = (APB_DATA_W/8),
|
||||
parameter logic AWUSER_EN = 1'b0,
|
||||
parameter AWUSER_W = 1,
|
||||
parameter logic WUSER_EN = 1'b0,
|
||||
parameter WUSER_W = 1,
|
||||
parameter logic BUSER_EN = 1'b0,
|
||||
parameter BUSER_W = 1,
|
||||
parameter logic ARUSER_EN = 1'b0,
|
||||
parameter ARUSER_W = 1,
|
||||
parameter logic RUSER_EN = 1'b0,
|
||||
parameter RUSER_W = 1
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axil_if #(
|
||||
.DATA_W(AXIL_DATA_W),
|
||||
.ADDR_W(ADDR_W),
|
||||
.STRB_W(AXIL_STRB_W),
|
||||
.AWUSER_EN(AWUSER_EN),
|
||||
.AWUSER_W(AWUSER_W),
|
||||
.WUSER_EN(WUSER_EN),
|
||||
.WUSER_W(WUSER_W),
|
||||
.BUSER_EN(BUSER_EN),
|
||||
.BUSER_W(BUSER_W),
|
||||
.ARUSER_EN(ARUSER_EN),
|
||||
.ARUSER_W(ARUSER_W),
|
||||
.RUSER_EN(RUSER_EN),
|
||||
.RUSER_W(RUSER_W)
|
||||
) s_axil();
|
||||
|
||||
taxi_apb_if #(
|
||||
.DATA_W(APB_DATA_W),
|
||||
.ADDR_W(ADDR_W),
|
||||
.STRB_W(APB_STRB_W),
|
||||
.PAUSER_EN(AWUSER_EN),
|
||||
.PAUSER_W(AWUSER_W),
|
||||
.PWUSER_EN(WUSER_EN),
|
||||
.PWUSER_W(WUSER_W),
|
||||
.PRUSER_EN(RUSER_EN),
|
||||
.PRUSER_W(RUSER_W),
|
||||
.PBUSER_EN(BUSER_EN),
|
||||
.PBUSER_W(BUSER_W)
|
||||
) m_apb();
|
||||
|
||||
taxi_axil_apb_adapter
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-lite slave interface
|
||||
*/
|
||||
.s_axil_wr(s_axil),
|
||||
.s_axil_rd(s_axil),
|
||||
|
||||
/*
|
||||
* APB master interface
|
||||
*/
|
||||
.m_apb(m_apb)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user