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https://github.com/fpganinja/taxi.git
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apb: Add APB dual-port RAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
@@ -27,6 +27,7 @@ To facilitate the dual-license model, contributions to the project can only be a
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* APB
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* SV interface for APB
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* Single-port RAM
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* Dual-port RAM
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* AXI
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* SV interface for AXI
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* AXI to AXI lite adapter
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186
src/apb/rtl/taxi_apb_dp_ram.sv
Normal file
186
src/apb/rtl/taxi_apb_dp_ram.sv
Normal file
@@ -0,0 +1,186 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* APM RAM
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*/
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module taxi_apb_dp_ram #
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(
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// Width of address bus in bits
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parameter ADDR_W = 16,
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// Extra pipeline register on output
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parameter logic PIPELINE_OUTPUT = 1'b0
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)
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(
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/*
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* Port A
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*/
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input wire logic a_clk,
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input wire logic a_rst,
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taxi_apb_if.slv s_apb_a,
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/*
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* Port B
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*/
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input wire logic b_clk,
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input wire logic b_rst,
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taxi_apb_if.slv s_apb_b
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);
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// extract parameters
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localparam DATA_W = s_apb_a.DATA_W;
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localparam STRB_W = s_apb_a.STRB_W;
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localparam VALID_ADDR_W = ADDR_W - $clog2(STRB_W);
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localparam BYTE_LANES = STRB_W;
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localparam BYTE_W = DATA_W/BYTE_LANES;
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// check configuration
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if (BYTE_W * STRB_W != DATA_W)
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$fatal(0, "Error: APB data width not evenly divisible (instance %m)");
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if (2**$clog2(BYTE_LANES) != BYTE_LANES)
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$fatal(0, "Error: APB byte lane count must be even power of two (instance %m)");
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if (s_apb_a.DATA_W != s_apb_b.DATA_W)
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$fatal(0, "Error: APB interface configuration mismatch (instance %m)");
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if (s_apb_a.ADDR_W < ADDR_W || s_apb_a.ADDR_W < ADDR_W)
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$fatal(0, "Error: APB address width is insufficient (instance %m)");
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logic mem_wr_en_a;
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logic mem_rd_en_a;
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logic mem_wr_en_b;
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logic mem_rd_en_b;
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logic s_apb_a_pready_reg = 1'b0, s_apb_a_pready_next;
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logic s_apb_a_pready_pipe_reg = 1'b0;
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logic [DATA_W-1:0] s_apb_a_prdata_reg = '0, s_apb_a_prdata_next;
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logic [DATA_W-1:0] s_apb_a_prdata_pipe_reg = '0;
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logic s_apb_b_pready_reg = 1'b0, s_apb_b_pready_next;
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logic s_apb_b_pready_pipe_reg = 1'b0;
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logic [DATA_W-1:0] s_apb_b_prdata_reg = '0, s_apb_b_prdata_next;
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logic [DATA_W-1:0] s_apb_b_prdata_pipe_reg = '0;
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// verilator lint_off MULTIDRIVEN
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// (* RAM_STYLE="BLOCK" *)
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logic [DATA_W-1:0] mem[2**VALID_ADDR_W];
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// verilator lint_on MULTIDRIVEN
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wire [VALID_ADDR_W-1:0] s_apb_a_paddr_valid = VALID_ADDR_W'(s_apb_a.paddr >> (ADDR_W - VALID_ADDR_W));
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wire [VALID_ADDR_W-1:0] s_apb_b_paddr_valid = VALID_ADDR_W'(s_apb_b.paddr >> (ADDR_W - VALID_ADDR_W));
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assign s_apb_a.prdata = PIPELINE_OUTPUT ? s_apb_a_prdata_pipe_reg : s_apb_a_prdata_reg;
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assign s_apb_a.pready = PIPELINE_OUTPUT ? s_apb_a_pready_pipe_reg : s_apb_a_pready_reg;
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assign s_apb_a.pslverr = 1'b0;
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assign s_apb_a.pruser = '0;
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assign s_apb_a.pbuser = '0;
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assign s_apb_b.prdata = PIPELINE_OUTPUT ? s_apb_b_prdata_pipe_reg : s_apb_b_prdata_reg;
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assign s_apb_b.pready = PIPELINE_OUTPUT ? s_apb_b_pready_pipe_reg : s_apb_b_pready_reg;
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assign s_apb_b.pslverr = 1'b0;
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assign s_apb_b.pruser = '0;
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assign s_apb_b.pbuser = '0;
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initial begin
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// two nested loops for smaller number of iterations per loop
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// workaround for synthesizer complaints about large loop counts
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for (integer i = 0; i < 2**VALID_ADDR_W; i = i + 2**(VALID_ADDR_W/2)) begin
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for (integer j = i; j < i + 2**(VALID_ADDR_W/2); j = j + 1) begin
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mem[j] = '0;
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end
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end
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end
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always_comb begin
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mem_wr_en_a = 1'b0;
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mem_rd_en_a = 1'b0;
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s_apb_a_pready_next = 1'b0;
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if (s_apb_a.psel && s_apb_a.penable && (!s_apb_a_pready_reg && (PIPELINE_OUTPUT || !s_apb_a_pready_pipe_reg))) begin
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s_apb_a_pready_next = 1'b1;
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if (s_apb_a.pwrite) begin
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mem_wr_en_a = 1'b1;
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end else begin
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mem_rd_en_a = 1'b1;
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end
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end
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end
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always_ff @(posedge a_clk) begin
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s_apb_a_pready_reg <= s_apb_a_pready_next;
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for (integer i = 0; i < BYTE_LANES; i = i + 1) begin
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if (mem_wr_en_a && s_apb_a.pstrb[i]) begin
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mem[s_apb_a_paddr_valid][BYTE_W*i +: BYTE_W] <= s_apb_a.pwdata[BYTE_W*i +: BYTE_W];
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end
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end
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if (mem_rd_en_a) begin
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s_apb_a_prdata_reg <= mem[s_apb_a_paddr_valid];
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end
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s_apb_a_prdata_pipe_reg <= s_apb_a_prdata_reg;
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s_apb_a_pready_pipe_reg <= s_apb_a_pready_reg;
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if (a_rst) begin
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s_apb_a_pready_reg <= 1'b0;
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end
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end
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always_comb begin
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mem_wr_en_b = 1'b0;
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mem_rd_en_b = 1'b0;
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s_apb_b_pready_next = 1'b0;
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if (s_apb_b.psel && s_apb_b.penable && (!s_apb_b_pready_reg && (PIPELINE_OUTPUT || !s_apb_b_pready_pipe_reg))) begin
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s_apb_b_pready_next = 1'b1;
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if (s_apb_b.pwrite) begin
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mem_wr_en_b = 1'b1;
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end else begin
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mem_rd_en_b = 1'b1;
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end
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end
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end
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always_ff @(posedge b_clk) begin
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s_apb_b_pready_reg <= s_apb_b_pready_next;
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for (integer i = 0; i < BYTE_LANES; i = i + 1) begin
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if (mem_wr_en_b && s_apb_b.pstrb[i]) begin
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mem[s_apb_b_paddr_valid][BYTE_W*i +: BYTE_W] <= s_apb_b.pwdata[BYTE_W*i +: BYTE_W];
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end
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end
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if (mem_rd_en_b) begin
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s_apb_b_prdata_reg <= mem[s_apb_b_paddr_valid];
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end
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s_apb_b_prdata_pipe_reg <= s_apb_b_prdata_reg;
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s_apb_b_pready_pipe_reg <= s_apb_b_pready_reg;
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if (b_rst) begin
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s_apb_b_pready_reg <= 1'b0;
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end
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end
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endmodule
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`resetall
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54
src/apb/tb/taxi_apb_dp_ram/Makefile
Normal file
54
src/apb/tb/taxi_apb_dp_ram/Makefile
Normal file
@@ -0,0 +1,54 @@
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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#
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# Copyright (c) 2020-2025 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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TOPLEVEL_LANG = verilog
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SIM ?= verilator
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WAVES ?= 0
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COCOTB_HDL_TIMEUNIT = 1ns
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COCOTB_HDL_TIMEPRECISION = 1ps
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RTL_DIR = ../../rtl
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LIB_DIR = ../../lib
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TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
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DUT = taxi_apb_dp_ram
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COCOTB_TEST_MODULES = test_$(DUT)
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COCOTB_TOPLEVEL = test_$(DUT)
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MODULE = $(COCOTB_TEST_MODULES)
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TOPLEVEL = $(COCOTB_TOPLEVEL)
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VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
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VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
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VERILOG_SOURCES += $(RTL_DIR)/taxi_apb_if.sv
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# handle file list files
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process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
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process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
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uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
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VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
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# module parameters
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export PARAM_DATA_W := 32
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export PARAM_ADDR_W := 16
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export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 )
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export PARAM_PIPELINE_OUTPUT := 0
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
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else ifeq ($(SIM), verilator)
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
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ifeq ($(WAVES), 1)
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COMPILE_ARGS += --trace-fst
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VERILATOR_TRACE = 1
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endif
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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261
src/apb/tb/taxi_apb_dp_ram/test_taxi_apb_dp_ram.py
Normal file
261
src/apb/tb/taxi_apb_dp_ram/test_taxi_apb_dp_ram.py
Normal file
@@ -0,0 +1,261 @@
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#!/usr/bin/env python
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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"""
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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"""
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import itertools
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import logging
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import os
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import random
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import cocotb_test.simulator
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import pytest
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge, Timer
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from cocotb.regression import TestFactory
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from cocotbext.axi import ApbBus, ApbMaster
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class TB(object):
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def __init__(self, dut):
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self.dut = dut
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self.log = logging.getLogger("cocotb.tb")
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self.log.setLevel(logging.DEBUG)
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cocotb.start_soon(Clock(dut.a_clk, 8, units="ns").start())
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cocotb.start_soon(Clock(dut.b_clk, 10, units="ns").start())
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self.apb_master = []
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self.apb_master.append(ApbMaster(ApbBus.from_entity(dut.s_apb_a), dut.a_clk, dut.a_rst))
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self.apb_master.append(ApbMaster(ApbBus.from_entity(dut.s_apb_b), dut.b_clk, dut.b_rst))
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def set_idle_generator(self, generator=None):
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if generator:
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for apb_master in self.apb_master:
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apb_master.set_pause_generator(generator())
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async def cycle_reset(self):
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self.dut.a_rst.setimmediatevalue(0)
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self.dut.b_rst.setimmediatevalue(0)
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await RisingEdge(self.dut.a_clk)
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await RisingEdge(self.dut.a_clk)
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self.dut.a_rst.value = 1
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self.dut.b_rst.value = 1
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await RisingEdge(self.dut.a_clk)
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await RisingEdge(self.dut.a_clk)
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self.dut.a_rst.value = 0
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await RisingEdge(self.dut.b_clk)
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self.dut.b_rst.value = 0
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await RisingEdge(self.dut.a_clk)
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await RisingEdge(self.dut.a_clk)
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async def run_test_write(dut, port=0, data_in=None, idle_inserter=None):
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tb = TB(dut)
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apb_master = tb.apb_master[port]
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byte_lanes = apb_master.byte_lanes
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await tb.cycle_reset()
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tb.set_idle_generator(idle_inserter)
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for length in range(1, byte_lanes*2):
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for offset in range(byte_lanes):
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tb.log.info("length %d, offset %d", length, offset)
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addr = offset+0x1000
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test_data = bytearray([x % 256 for x in range(length)])
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await apb_master.write(addr-4, b'\xaa'*(length+8))
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await apb_master.write(addr, test_data)
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data = await apb_master.read(addr-1, length+2)
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assert data.data == b'\xaa'+test_data+b'\xaa'
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await RisingEdge(dut.a_clk)
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await RisingEdge(dut.a_clk)
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async def run_test_read(dut, port=0, data_in=None, idle_inserter=None):
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tb = TB(dut)
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apb_master = tb.apb_master[port]
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byte_lanes = apb_master.byte_lanes
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await tb.cycle_reset()
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tb.set_idle_generator(idle_inserter)
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for length in range(1, byte_lanes*2):
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for offset in range(byte_lanes):
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tb.log.info("length %d, offset %d", length, offset)
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addr = offset+0x1000
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test_data = bytearray([x % 256 for x in range(length)])
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await apb_master.write(addr, test_data)
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data = await apb_master.read(addr, length)
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assert data.data == test_data
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await RisingEdge(dut.a_clk)
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await RisingEdge(dut.a_clk)
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async def run_test_arb(dut, data_in=None, idle_inserter=None):
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tb = TB(dut)
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await tb.cycle_reset()
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tb.set_idle_generator(idle_inserter)
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async def worker(master, offset):
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wr_op = master.init_write(offset, b'\x11\x22\x33\x44')
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rd_op = master.init_read(offset, 4)
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await wr_op.wait()
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await rd_op.wait()
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workers = []
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for k in range(10):
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workers.append(cocotb.start_soon(worker(tb.apb_master[0], k*256)))
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workers.append(cocotb.start_soon(worker(tb.apb_master[1], k*256)))
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while workers:
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await workers.pop(0).join()
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await RisingEdge(dut.a_clk)
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await RisingEdge(dut.a_clk)
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async def run_stress_test(dut, idle_inserter=None):
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tb = TB(dut)
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await tb.cycle_reset()
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tb.set_idle_generator(idle_inserter)
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async def worker(master, offset, aperture, count=16):
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for k in range(count):
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length = random.randint(1, min(32, aperture))
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addr = offset+random.randint(0, aperture-length)
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test_data = bytearray([x % 256 for x in range(length)])
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await Timer(random.randint(1, 100), 'ns')
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await master.write(addr, test_data)
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await Timer(random.randint(1, 100), 'ns')
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data = await master.read(addr, length)
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assert data.data == test_data
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workers = []
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for k in range(16):
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workers.append(cocotb.start_soon(worker(tb.apb_master[k%len(tb.apb_master)], k*0x1000, 0x1000, count=16)))
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while workers:
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await workers.pop(0).join()
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|
||||
await RisingEdge(dut.a_clk)
|
||||
await RisingEdge(dut.a_clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
if getattr(cocotb, 'top', None) is not None:
|
||||
|
||||
for test in [run_test_write, run_test_read]:
|
||||
|
||||
factory = TestFactory(test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("port", [0, 1])
|
||||
factory.generate_tests()
|
||||
|
||||
factory = TestFactory(run_test_arb)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
factory = TestFactory(run_stress_test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("data_w", [8, 16, 32])
|
||||
def test_taxi_apb_dp_ram(request, data_w):
|
||||
dut = "taxi_apb_dp_ram"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
os.path.join(rtl_dir, "taxi_apb_if.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['DATA_W'] = data_w
|
||||
parameters['ADDR_W'] = 16
|
||||
parameters['STRB_W'] = parameters['DATA_W'] // 8
|
||||
parameters['PIPELINE_OUTPUT'] = 0
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
62
src/apb/tb/taxi_apb_dp_ram/test_taxi_apb_dp_ram.sv
Normal file
62
src/apb/tb/taxi_apb_dp_ram/test_taxi_apb_dp_ram.sv
Normal file
@@ -0,0 +1,62 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* APB dual-port RAM testbench
|
||||
*/
|
||||
module test_taxi_apb_dp_ram #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter DATA_W = 32,
|
||||
parameter ADDR_W = 16,
|
||||
parameter STRB_W = (DATA_W/8),
|
||||
parameter PIPELINE_OUTPUT = 0
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic a_clk;
|
||||
logic a_rst;
|
||||
logic b_clk;
|
||||
logic b_rst;
|
||||
|
||||
taxi_apb_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.ADDR_W(ADDR_W+16),
|
||||
.STRB_W(STRB_W)
|
||||
) s_apb_a(), s_apb_b();
|
||||
|
||||
taxi_apb_dp_ram #(
|
||||
.ADDR_W(ADDR_W),
|
||||
.PIPELINE_OUTPUT(PIPELINE_OUTPUT)
|
||||
)
|
||||
uut (
|
||||
/*
|
||||
* Port A
|
||||
*/
|
||||
.a_clk(a_clk),
|
||||
.a_rst(a_rst),
|
||||
.s_apb_a(s_apb_a),
|
||||
|
||||
/*
|
||||
* Port B
|
||||
*/
|
||||
.b_clk(b_clk),
|
||||
.b_rst(b_rst),
|
||||
.s_apb_b(s_apb_b)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user