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pcie: Add MSI-X module with AXI lite interface
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
@@ -183,6 +183,7 @@ The Taxi transport library contains many smaller components that can be composed
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* PCIe AXI lite master
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* PCIe AXI lite master for Xilinx UltraScale
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* MSI shim for Xilinx UltraScale
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* MSI-X with AXI lite control interface
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* Primitives
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* Arbiter
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* Priority encoder
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514
src/pcie/rtl/taxi_pcie_msix_axil.sv
Normal file
514
src/pcie/rtl/taxi_pcie_msix_axil.sv
Normal file
@@ -0,0 +1,514 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2022-2026 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* PCIe MSI-X module with AXI lite interface
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*/
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module taxi_pcie_msix_axil #
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(
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// TLP interface configuration
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parameter logic TLP_FORCE_64_BIT_ADDR = 1'b0
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* AXI lite interface for MSI-X tables
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*/
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taxi_axil_if.wr_slv s_axil_wr,
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taxi_axil_if.rd_slv s_axil_rd,
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/*
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* Interrupt request input
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*/
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taxi_axis_if.snk s_axis_irq,
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/*
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* Memory write TLP output
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*/
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taxi_pcie_tlp_if.src tx_wr_req_tlp,
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/*
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* Configuration
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*/
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input wire logic [7:0] bus_num,
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input wire logic [7:0] func_num,
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input wire logic msix_enable,
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input wire logic msix_mask
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);
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// extract parameters
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localparam TLP_SEGS = tx_wr_req_tlp.SEGS;
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localparam TLP_SEG_DATA_W = tx_wr_req_tlp.SEG_DATA_W;
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localparam TLP_SEG_EMPTY_W = tx_wr_req_tlp.SEG_EMPTY_W;
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localparam TLP_DATA_W = TLP_SEGS*TLP_SEG_DATA_W;
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localparam TLP_HDR_W = tx_wr_req_tlp.HDR_W;
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localparam FUNC_NUM_W = tx_wr_req_tlp.FUNC_NUM_W;
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localparam AXIL_DATA_W = s_axil_wr.DATA_W;
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localparam AXIL_ADDR_W = s_axil_wr.ADDR_W;
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localparam AXIL_STRB_W = s_axil_wr.STRB_W;
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localparam IRQ_INDEX_W = s_axis_irq.DATA_W;
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localparam TLP_DATA_W_B = TLP_DATA_W/8;
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localparam TLP_DATA_W_DW = TLP_DATA_W/32;
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localparam TBL_ADDR_W = IRQ_INDEX_W+1;
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localparam PBA_ADDR_W = IRQ_INDEX_W > 6 ? IRQ_INDEX_W-6 : 0;
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localparam PBA_ADDR_W_INT = PBA_ADDR_W > 0 ? PBA_ADDR_W : 1;
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localparam INDEX_SHIFT = $clog2(64/8);
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localparam WORD_SELECT_SHIFT = $clog2(AXIL_DATA_W/8);
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localparam WORD_SELECT_W = 64 > AXIL_DATA_W ? $clog2((64+7)/8) - $clog2(AXIL_DATA_W/8) : 0;
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// bus width assertions
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if (AXIL_STRB_W * 8 != AXIL_DATA_W)
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$fatal(0, "Error: AXI lite interface requires byte (8-bit) granularity (instance %m)");
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if (AXIL_DATA_W > 64)
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$fatal(0, "Error: AXI lite data width must be 64 or less (instance %m)");
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if (AXIL_ADDR_W < IRQ_INDEX_W+5)
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$fatal(0, "Error: AXI lite address width too narrow (instance %m)");
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if (IRQ_INDEX_W > 11)
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$fatal(0, "Error: IRQ index width must be 11 or less (instance %m)");
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localparam [2:0]
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TLP_FMT_3DW = 3'b000,
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TLP_FMT_4DW = 3'b001,
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TLP_FMT_3DW_DATA = 3'b010,
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TLP_FMT_4DW_DATA = 3'b011,
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TLP_FMT_PREFIX = 3'b100;
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localparam [1:0]
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STATE_IDLE = 2'd0,
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STATE_READ_TBL_1 = 2'd1,
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STATE_READ_TBL_2 = 2'd2,
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STATE_SEND_TLP = 2'd3;
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logic [1:0] state_reg = STATE_IDLE, state_next;
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logic [IRQ_INDEX_W-1:0] irq_index_reg = '0, irq_index_next;
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logic [63:0] vec_addr_reg = '0, vec_addr_next;
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logic [31:0] vec_data_reg = '0, vec_data_next;
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logic vec_mask_reg = 1'b0, vec_mask_next;
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logic last_read_reg = 1'b0, last_read_next;
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logic [127:0] tlp_hdr;
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logic read_eligible;
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logic write_eligible;
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logic tbl_axil_mem_rd_en;
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logic tbl_axil_mem_wr_en;
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logic [7:0] tbl_axil_mem_wr_be;
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logic [63:0] tbl_axil_mem_wr_data;
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logic pba_axil_mem_rd_en;
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logic tbl_mem_rd_en;
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logic [TBL_ADDR_W-1:0] tbl_mem_addr;
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logic pba_mem_rd_en;
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logic pba_mem_wr_en;
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logic [PBA_ADDR_W-1:0] pba_mem_addr;
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logic [63:0] pba_mem_wr_data;
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logic s_axil_awready_reg = 1'b0, s_axil_awready_next;
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logic s_axil_wready_reg = 1'b0, s_axil_wready_next;
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logic s_axil_bvalid_reg = 1'b0, s_axil_bvalid_next;
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logic s_axil_arready_reg = 1'b0, s_axil_arready_next;
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logic [AXIL_DATA_W-1:0] s_axil_rdata_reg = '0, s_axil_rdata_next;
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logic s_axil_rvalid_reg = 1'b0, s_axil_rvalid_next;
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logic irq_ready_reg = 1'b0, irq_ready_next;
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logic [31:0] tx_wr_req_tlp_data_reg = '0, tx_wr_req_tlp_data_next;
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logic [TLP_HDR_W-1:0] tx_wr_req_tlp_hdr_reg = '0, tx_wr_req_tlp_hdr_next;
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logic tx_wr_req_tlp_valid_reg = 0, tx_wr_req_tlp_valid_next;
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logic msix_enable_reg = 1'b0;
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logic msix_mask_reg = 1'b0;
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// MSI-X table
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(* ramstyle = "no_rw_check, mlab" *)
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logic [63:0] tbl_mem[2**TBL_ADDR_W];
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// MSI-X PBA
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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logic [63:0] pba_mem[2**PBA_ADDR_W];
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logic tbl_rd_data_valid_reg = 1'b0, tbl_rd_data_valid_next;
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logic pba_rd_data_valid_reg = 1'b0, pba_rd_data_valid_next;
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logic [WORD_SELECT_W-1:0] rd_data_shift_reg = '0, rd_data_shift_next;
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logic [63:0] tbl_mem_rd_data_reg = '0;
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logic [63:0] pba_mem_rd_data_reg = '0;
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logic [63:0] tbl_axil_mem_rd_data_reg = '0;
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logic [63:0] pba_axil_mem_rd_data_reg = '0;
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wire [TBL_ADDR_W-1:0] s_axil_awaddr_index = s_axil_wr.awaddr[INDEX_SHIFT +: TBL_ADDR_W];
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wire [WORD_SELECT_W-1:0] s_axil_awaddr_word = AXIL_DATA_W < 64 ? s_axil_wr.awaddr[WORD_SELECT_SHIFT +: WORD_SELECT_W] : 0;
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wire [TBL_ADDR_W-1:0] s_axil_araddr_index = s_axil_rd.araddr[INDEX_SHIFT +: TBL_ADDR_W];
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wire [WORD_SELECT_W-1:0] s_axil_araddr_word = AXIL_DATA_W < 64 ? s_axil_rd.araddr[WORD_SELECT_SHIFT +: WORD_SELECT_W] : 0;
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assign s_axil_wr.awready = s_axil_awready_reg;
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assign s_axil_wr.wready = s_axil_wready_reg;
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assign s_axil_wr.bresp = 2'b00;
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assign s_axil_wr.buser = '0;
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assign s_axil_wr.bvalid = s_axil_bvalid_reg;
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assign s_axil_rd.arready = s_axil_arready_reg;
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assign s_axil_rd.rdata = s_axil_rdata_reg;
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assign s_axil_rd.rresp = 2'b00;
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assign s_axil_rd.ruser = '0;
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assign s_axil_rd.rvalid = s_axil_rvalid_reg;
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assign s_axis_irq.tready = irq_ready_reg;
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assign tx_wr_req_tlp.data = TLP_DATA_W'(tx_wr_req_tlp_data_reg);
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assign tx_wr_req_tlp.empty = '1;
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assign tx_wr_req_tlp.hdr = tx_wr_req_tlp_hdr_reg;
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assign tx_wr_req_tlp.seq = '0;
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assign tx_wr_req_tlp.bar_id = '0;
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assign tx_wr_req_tlp.func_num = '0;
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assign tx_wr_req_tlp.error = '0;
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assign tx_wr_req_tlp.valid = tx_wr_req_tlp_valid_reg;
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assign tx_wr_req_tlp.sop = 1'b1;
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assign tx_wr_req_tlp.eop = 1'b1;
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initial begin
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for (integer i = 0; i < 2**TBL_ADDR_W; i = i + 1) begin
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tbl_mem[i] = '0;
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end
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for (integer i = 0; i < 2**PBA_ADDR_W; i = i + 1) begin
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pba_mem[i] = '0;
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end
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end
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always_comb begin
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state_next = STATE_IDLE;
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tbl_mem_rd_en = 1'b0;
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tbl_mem_addr = {irq_index_reg, 1'b0};
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pba_mem_rd_en = 1'b0;
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pba_mem_wr_en = 1'b0;
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pba_mem_addr = PBA_ADDR_W_INT'(irq_index_reg >> 6);
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pba_mem_wr_data = '0;
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irq_index_next = irq_index_reg;
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vec_addr_next = vec_addr_reg;
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vec_data_next = vec_data_reg;
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vec_mask_next = vec_mask_reg;
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irq_ready_next = 1'b0;
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tx_wr_req_tlp_data_next = tx_wr_req_tlp_data_reg;
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tx_wr_req_tlp_hdr_next = tx_wr_req_tlp_hdr_reg;
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tx_wr_req_tlp_valid_next = tx_wr_req_tlp_valid_reg && !tx_wr_req_tlp.ready;
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// TLP header
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// DW 0
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if (((vec_addr_reg[63:2] >> 30) != 0) || TLP_FORCE_64_BIT_ADDR) begin
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tlp_hdr[127:125] = TLP_FMT_4DW_DATA; // fmt - 4DW with data
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end else begin
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tlp_hdr[127:125] = TLP_FMT_3DW_DATA; // fmt - 3DW with data
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end
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tlp_hdr[124:120] = 5'b00000; // type - write
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tlp_hdr[119] = 1'b0; // T9
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tlp_hdr[118:116] = 3'b000; // TC
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tlp_hdr[115] = 1'b0; // T8
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tlp_hdr[114] = 1'b0; // attr
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tlp_hdr[113] = 1'b0; // LN
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tlp_hdr[112] = 1'b0; // TH
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tlp_hdr[111] = 1'b0; // TD
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tlp_hdr[110] = 1'b0; // EP
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tlp_hdr[109:108] = 2'b00; // attr
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tlp_hdr[107:106] = 2'b00; // AT
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tlp_hdr[105:96] = 10'd1; // length
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// DW 1
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tlp_hdr[95:88] = bus_num; // requester ID (bus number)
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tlp_hdr[87:80] = func_num; // requester ID (device/function number)
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tlp_hdr[79:72] = 8'd0; // tag
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tlp_hdr[71:68] = 4'b0000; // last BE
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tlp_hdr[67:64] = 4'b1111; // first BE
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if ((vec_addr_reg[63:32] != 0) || TLP_FORCE_64_BIT_ADDR) begin
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// DW 2+3
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tlp_hdr[63:2] = vec_addr_reg[63:2]; // address
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tlp_hdr[1:0] = 2'b00; // PH
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end else begin
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// DW 2
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tlp_hdr[63:34] = vec_addr_reg[31:2]; // address
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tlp_hdr[33:32] = 2'b00; // PH
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// DW 3
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tlp_hdr[31:0] = 32'd0;
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end
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case (state_reg)
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STATE_IDLE: begin
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irq_ready_next = 1'b1;
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if (s_axis_irq.tvalid && s_axis_irq.tready) begin
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// new request
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irq_ready_next = 1'b0;
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irq_index_next = s_axis_irq.tdata;
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tbl_mem_rd_en = 1'b1;
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tbl_mem_addr = {irq_index_next, 1'b0};
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pba_mem_rd_en = 1'b1;
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pba_mem_addr = PBA_ADDR_W_INT'(irq_index_next >> 6);
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state_next = STATE_READ_TBL_1;
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end else if (!s_axis_irq.tvalid && msix_enable_reg && !msix_mask_reg) begin
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// no new request waiting, scan PBA for masked requests
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if (pba_mem_rd_data_reg[6'(irq_index_reg)] != 0) begin
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// PBA bit for current index is set, try issuing it
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irq_ready_next = 1'b0;
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tbl_mem_rd_en = 1'b1;
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tbl_mem_addr = {irq_index_next, 1'b0};
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pba_mem_rd_en = 1'b1;
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pba_mem_addr = PBA_ADDR_W_INT'(irq_index_next >> 6);
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state_next = STATE_READ_TBL_1;
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end else begin
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// PBA bit for current index is not set
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if (pba_mem_rd_data_reg != 0) begin
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// at least one bit set in current group, move to next index
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irq_index_next = irq_index_reg + 1;
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end else begin
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// no bits set in current group, move to next group
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irq_index_next = (irq_index_reg & ({IRQ_INDEX_W{1'b1}} << 6)) + 'd64;
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end
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pba_mem_rd_en = 1'b1;
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pba_mem_addr = PBA_ADDR_W_INT'(irq_index_next >> 6);
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state_next = STATE_IDLE;
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end
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end else begin
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state_next = STATE_IDLE;
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end
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end
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STATE_READ_TBL_1: begin
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// handle first table read
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tbl_mem_rd_en = 1'b1;
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tbl_mem_addr = {irq_index_reg, 1'b1};
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vec_addr_next = {tbl_mem_rd_data_reg[63:2], 2'b00};
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state_next = STATE_READ_TBL_2;
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end
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STATE_READ_TBL_2: begin
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// handle second table read
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vec_data_next = tbl_mem_rd_data_reg[31:0];
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vec_mask_next = tbl_mem_rd_data_reg[32];
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if (msix_enable_reg && !msix_mask_reg && !vec_mask_next) begin
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// send TLP
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state_next = STATE_SEND_TLP;
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end else begin
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// set PBA bit
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pba_mem_wr_en = 1'b1;
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pba_mem_wr_data = pba_mem_rd_data_reg | (1 << 6'(irq_index_reg));
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irq_ready_next = 1'b1;
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state_next = STATE_IDLE;
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end
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end
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STATE_SEND_TLP: begin
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if (!tx_wr_req_tlp.valid || tx_wr_req_tlp.ready) begin
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// send TLP
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tx_wr_req_tlp_data_next = vec_data_reg;
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tx_wr_req_tlp_hdr_next = tlp_hdr;
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tx_wr_req_tlp_valid_next = 1'b1;
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// clear PBA bit
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pba_mem_wr_en = 1'b1;
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pba_mem_wr_data = pba_mem_rd_data_reg & ~(1 << 6'(irq_index_reg));
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// increment index so we don't check the same PBA bit immediately
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irq_index_next = irq_index_reg + 1;
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irq_ready_next = 1'b1;
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state_next = STATE_IDLE;
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end else begin
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state_next = STATE_SEND_TLP;
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end
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end
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endcase
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end
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always_ff @(posedge clk) begin
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state_reg <= state_next;
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irq_index_reg <= irq_index_next;
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vec_addr_reg <= vec_addr_next;
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vec_data_reg <= vec_data_next;
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vec_mask_reg <= vec_mask_next;
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irq_ready_reg <= irq_ready_next;
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tx_wr_req_tlp_data_reg <= tx_wr_req_tlp_data_next;
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tx_wr_req_tlp_hdr_reg <= tx_wr_req_tlp_hdr_next;
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tx_wr_req_tlp_valid_reg <= tx_wr_req_tlp_valid_next;
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msix_enable_reg <= msix_enable;
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msix_mask_reg <= msix_mask;
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if (tbl_mem_rd_en) begin
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tbl_mem_rd_data_reg <= tbl_mem[tbl_mem_addr];
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end
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if (pba_mem_wr_en) begin
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pba_mem[pba_mem_addr] <= pba_mem_wr_data;
|
||||
end else if (pba_mem_rd_en) begin
|
||||
pba_mem_rd_data_reg <= pba_mem[pba_mem_addr];
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
state_reg <= STATE_IDLE;
|
||||
|
||||
irq_ready_reg <= 1'b0;
|
||||
|
||||
tx_wr_req_tlp_valid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// AXI lite interface
|
||||
always_comb begin
|
||||
tbl_axil_mem_rd_en = 1'b0;
|
||||
tbl_axil_mem_wr_en = 1'b0;
|
||||
tbl_axil_mem_wr_be = 8'(s_axil_wr.wstrb << (s_axil_awaddr_word * AXIL_STRB_W));
|
||||
tbl_axil_mem_wr_data = {2**WORD_SELECT_W{s_axil_wr.wdata}};
|
||||
pba_axil_mem_rd_en = 1'b0;
|
||||
|
||||
tbl_rd_data_valid_next = tbl_rd_data_valid_reg;
|
||||
pba_rd_data_valid_next = pba_rd_data_valid_reg;
|
||||
rd_data_shift_next = rd_data_shift_reg;
|
||||
|
||||
last_read_next = last_read_reg;
|
||||
|
||||
s_axil_awready_next = 1'b0;
|
||||
s_axil_wready_next = 1'b0;
|
||||
s_axil_bvalid_next = s_axil_bvalid_reg && !s_axil_wr.bready;
|
||||
|
||||
s_axil_arready_next = 1'b0;
|
||||
s_axil_rdata_next = s_axil_rdata_reg;
|
||||
s_axil_rvalid_next = s_axil_rvalid_reg && !s_axil_rd.rready;
|
||||
|
||||
write_eligible = s_axil_wr.awvalid && s_axil_wr.wvalid && (!s_axil_wr.bvalid || s_axil_wr.bready) && (!s_axil_wr.awready && !s_axil_wr.wready);
|
||||
read_eligible = s_axil_rd.arvalid && (!s_axil_rd.rvalid || s_axil_rd.rready || !(tbl_rd_data_valid_reg || pba_rd_data_valid_reg)) && (!s_axil_rd.arready);
|
||||
|
||||
if ((tbl_rd_data_valid_reg || pba_rd_data_valid_reg) && (!s_axil_rd.rvalid || s_axil_rd.rready)) begin
|
||||
s_axil_rvalid_next = 1'b1;
|
||||
tbl_rd_data_valid_next = 1'b0;
|
||||
pba_rd_data_valid_next = 1'b0;
|
||||
|
||||
if (tbl_rd_data_valid_reg) begin
|
||||
if (AXIL_DATA_W < 64) begin
|
||||
s_axil_rdata_next = AXIL_DATA_W'(tbl_axil_mem_rd_data_reg >> rd_data_shift_reg*AXIL_DATA_W);
|
||||
end else begin
|
||||
s_axil_rdata_next = AXIL_DATA_W'(tbl_axil_mem_rd_data_reg);
|
||||
end
|
||||
end else begin
|
||||
if (AXIL_DATA_W < 64) begin
|
||||
s_axil_rdata_next = AXIL_DATA_W'(pba_axil_mem_rd_data_reg >> rd_data_shift_reg*AXIL_DATA_W);
|
||||
end else begin
|
||||
s_axil_rdata_next = AXIL_DATA_W'(pba_axil_mem_rd_data_reg);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
if (write_eligible && (!read_eligible || last_read_reg)) begin
|
||||
last_read_next = 1'b0;
|
||||
|
||||
s_axil_awready_next = 1'b1;
|
||||
s_axil_wready_next = 1'b1;
|
||||
s_axil_bvalid_next = 1'b1;
|
||||
|
||||
if (s_axil_wr.awaddr[IRQ_INDEX_W+5-1] == 0) begin
|
||||
tbl_axil_mem_wr_en = 1'b1;
|
||||
end
|
||||
end else if (read_eligible) begin
|
||||
last_read_next = 1'b1;
|
||||
|
||||
s_axil_arready_next = 1'b1;
|
||||
|
||||
rd_data_shift_next = s_axil_araddr_word;
|
||||
|
||||
if (s_axil_rd.araddr[IRQ_INDEX_W+5-1] == 0) begin
|
||||
tbl_axil_mem_rd_en = 1'b1;
|
||||
tbl_rd_data_valid_next = 1'b1;
|
||||
end else begin
|
||||
pba_axil_mem_rd_en = 1'b1;
|
||||
pba_rd_data_valid_next = 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
tbl_rd_data_valid_reg <= tbl_rd_data_valid_next;
|
||||
pba_rd_data_valid_reg <= pba_rd_data_valid_next;
|
||||
rd_data_shift_reg <= rd_data_shift_next;
|
||||
|
||||
last_read_reg <= last_read_next;
|
||||
|
||||
s_axil_awready_reg <= s_axil_awready_next;
|
||||
s_axil_wready_reg <= s_axil_wready_next;
|
||||
s_axil_bvalid_reg <= s_axil_bvalid_next;
|
||||
|
||||
s_axil_arready_reg <= s_axil_arready_next;
|
||||
s_axil_rdata_reg <= s_axil_rdata_next;
|
||||
s_axil_rvalid_reg <= s_axil_rvalid_next;
|
||||
|
||||
if (tbl_axil_mem_rd_en) begin
|
||||
tbl_axil_mem_rd_data_reg <= tbl_mem[s_axil_araddr_index];
|
||||
end else begin
|
||||
for (integer i = 0; i < 8; i = i + 1) begin
|
||||
if (tbl_axil_mem_wr_en && tbl_axil_mem_wr_be[i]) begin
|
||||
tbl_mem[s_axil_awaddr_index][8*i +: 8] <= tbl_axil_mem_wr_data[8*i +: 8];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
if (pba_axil_mem_rd_en) begin
|
||||
pba_axil_mem_rd_data_reg <= pba_mem[s_axil_araddr_index[PBA_ADDR_W-1:0]];
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
tbl_rd_data_valid_reg <= 1'b0;
|
||||
pba_rd_data_valid_reg <= 1'b0;
|
||||
last_read_reg <= 1'b0;
|
||||
|
||||
s_axil_awready_reg <= 1'b0;
|
||||
s_axil_wready_reg <= 1'b0;
|
||||
s_axil_bvalid_reg <= 1'b0;
|
||||
|
||||
s_axil_arready_reg <= 1'b0;
|
||||
s_axil_rvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
56
src/pcie/tb/taxi_pcie_msix_axil/Makefile
Normal file
56
src/pcie/tb/taxi_pcie_msix_axil/Makefile
Normal file
@@ -0,0 +1,56 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2021-2026 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_pcie_msix_axil
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/taxi_pcie_tlp_if.sv
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/axi/rtl/taxi_axil_if.sv
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_IRQ_INDEX_W := 11
|
||||
export PARAM_AXIL_DATA_W := 32
|
||||
export PARAM_AXIL_ADDR_W := $(shell expr $(PARAM_IRQ_INDEX_W) + 5 )
|
||||
export PARAM_TLP_FORCE_64_BIT_ADDR := 0
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
1
src/pcie/tb/taxi_pcie_msix_axil/pcie_if.py
Symbolic link
1
src/pcie/tb/taxi_pcie_msix_axil/pcie_if.py
Symbolic link
@@ -0,0 +1 @@
|
||||
../pcie_if.py
|
||||
353
src/pcie/tb/taxi_pcie_msix_axil/test_taxi_pcie_msix_axil.py
Normal file
353
src/pcie/tb/taxi_pcie_msix_axil/test_taxi_pcie_msix_axil.py
Normal file
@@ -0,0 +1,353 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2022-2026 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import re
|
||||
import sys
|
||||
from contextlib import contextmanager
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiLiteBus, AxiLiteMaster
|
||||
from cocotbext.axi import AxiStreamBus, AxiStreamSource
|
||||
|
||||
|
||||
try:
|
||||
from pcie_if import PcieIfSink, PcieIfTxBus
|
||||
except ImportError:
|
||||
# attempt import from current directory
|
||||
sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
|
||||
try:
|
||||
from pcie_if import PcieIfSink, PcieIfTxBus
|
||||
finally:
|
||||
del sys.path[0]
|
||||
|
||||
|
||||
@contextmanager
|
||||
def assert_raises(exc_type, pattern=None):
|
||||
try:
|
||||
yield
|
||||
except exc_type as e:
|
||||
if pattern:
|
||||
assert re.match(pattern, str(e)), \
|
||||
"Correct exception type caught, but message did not match pattern"
|
||||
pass
|
||||
else:
|
||||
raise AssertionError("{} was not raised".format(exc_type.__name__))
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 4, units="ns").start())
|
||||
|
||||
self.axil_master = AxiLiteMaster(AxiLiteBus.from_entity(dut.s_axil), dut.clk, dut.rst)
|
||||
|
||||
self.irq_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_irq), dut.clk, dut.rst)
|
||||
|
||||
self.tlp_sink = PcieIfSink(PcieIfTxBus.from_entity(dut.tx_wr_req_tlp), dut.clk, dut.rst)
|
||||
|
||||
dut.bus_num.setimmediatevalue(0)
|
||||
dut.func_num.setimmediatevalue(0)
|
||||
dut.msix_enable.setimmediatevalue(0)
|
||||
dut.msix_mask.setimmediatevalue(0)
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
self.axil_master.write_if.aw_channel.set_pause_generator(generator())
|
||||
self.axil_master.write_if.w_channel.set_pause_generator(generator())
|
||||
self.axil_master.read_if.ar_channel.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
self.axil_master.write_if.b_channel.set_pause_generator(generator())
|
||||
self.axil_master.read_if.r_channel.set_pause_generator(generator())
|
||||
self.tlp_sink.set_pause_generator(generator())
|
||||
|
||||
async def cycle_reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
async def run_test_table_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.axil_master.write_if.byte_lanes
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
for length in range(1, byte_lanes*4):
|
||||
for offset in range(byte_lanes):
|
||||
tb.log.info("length %d, offset %d", length, offset)
|
||||
addr = offset+0x100
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await tb.axil_master.write(addr-4, b'\xaa'*(length+8))
|
||||
|
||||
await tb.axil_master.write(addr, test_data)
|
||||
|
||||
data = await tb.axil_master.read(addr-1, length+2)
|
||||
|
||||
assert data.data == b'\xaa'+test_data+b'\xaa'
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_table_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.axil_master.write_if.byte_lanes
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
for length in range(1, byte_lanes*4):
|
||||
for offset in range(byte_lanes):
|
||||
tb.log.info("length %d, offset %d", length, offset)
|
||||
addr = offset+0x100
|
||||
test_data = bytearray([x % 256 for x in range(length)])
|
||||
|
||||
await tb.axil_master.write(addr, test_data)
|
||||
|
||||
data = await tb.axil_master.read(addr, length)
|
||||
|
||||
assert data.data == test_data
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_msix(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
tbl_offset = 0
|
||||
pba_offset = 2**(tb.axil_master.write_if.address_width-1)
|
||||
|
||||
await tb.cycle_reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
dut.msix_enable.value = 1
|
||||
|
||||
tb.log.info("Init table")
|
||||
|
||||
for k in range(2**len(dut.s_axis_irq.tdata)):
|
||||
await tb.axil_master.write_qword(tbl_offset+k*16+0, 0x1234567800000000 + k*4)
|
||||
await tb.axil_master.write_dword(tbl_offset+k*16+8, k)
|
||||
await tb.axil_master.write_dword(tbl_offset+k*16+12, 0)
|
||||
|
||||
tb.log.info("Test unmasked interrupts")
|
||||
|
||||
for k in range(8):
|
||||
await tb.irq_source.send([k])
|
||||
|
||||
for k in range(8):
|
||||
frame = await tb.tlp_sink.recv()
|
||||
tlp = frame.to_tlp()
|
||||
|
||||
tb.log.info("TLP: %s", tlp)
|
||||
|
||||
assert tlp.address == 0x1234567800000000 + k*4
|
||||
assert tlp.data == k.to_bytes(4, 'little')
|
||||
assert tlp.first_be == 0xf
|
||||
|
||||
val = await tb.axil_master.read_dword(pba_offset+0)
|
||||
|
||||
tb.log.info("PBA value: 0x%02x", val)
|
||||
|
||||
assert val == 0x00
|
||||
|
||||
tb.log.info("Test global mask")
|
||||
|
||||
dut.msix_mask.value = 1
|
||||
|
||||
for k in range(8):
|
||||
await tb.irq_source.send([k])
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
while int(dut.s_axis_irq.tvalid.value):
|
||||
await RisingEdge(dut.clk)
|
||||
for k in range(10):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
val = await tb.axil_master.read_dword(pba_offset+0)
|
||||
|
||||
tb.log.info("PBA value: 0x%02x", val)
|
||||
|
||||
assert val == 0xff
|
||||
|
||||
dut.msix_mask.value = 0
|
||||
|
||||
for k in range(8):
|
||||
frame = await tb.tlp_sink.recv()
|
||||
tlp = frame.to_tlp()
|
||||
|
||||
tb.log.info("TLP: %s", tlp)
|
||||
|
||||
assert tlp.address == 0x1234567800000000 + k*4
|
||||
assert tlp.data == k.to_bytes(4, 'little')
|
||||
assert tlp.first_be == 0xf
|
||||
|
||||
val = await tb.axil_master.read_dword(pba_offset+0)
|
||||
|
||||
tb.log.info("PBA value: 0x%02x", val)
|
||||
|
||||
assert val == 0x00
|
||||
|
||||
tb.log.info("Test vector masks")
|
||||
|
||||
for k in range(8):
|
||||
await tb.axil_master.write_dword(tbl_offset+k*16+12, 1)
|
||||
|
||||
for k in range(8):
|
||||
await tb.irq_source.send([k])
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
while int(dut.s_axis_irq.tvalid.value):
|
||||
await RisingEdge(dut.clk)
|
||||
for k in range(10):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
val = await tb.axil_master.read_dword(pba_offset+0)
|
||||
|
||||
tb.log.info("PBA value: 0x%02x", val)
|
||||
|
||||
assert val == 0xff
|
||||
|
||||
for k in range(8):
|
||||
await tb.axil_master.write_dword(tbl_offset+k*16+12, 0)
|
||||
|
||||
for k in range(8):
|
||||
frame = await tb.tlp_sink.recv()
|
||||
tlp = frame.to_tlp()
|
||||
|
||||
tb.log.info("TLP: %s", tlp)
|
||||
|
||||
assert tlp.address == 0x1234567800000000 + k*4
|
||||
assert tlp.data == k.to_bytes(4, 'little')
|
||||
assert tlp.first_be == 0xf
|
||||
|
||||
val = await tb.axil_master.read_dword(pba_offset+0)
|
||||
|
||||
tb.log.info("PBA value: 0x%02x", val)
|
||||
|
||||
assert val == 0x00
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
if getattr(cocotb, 'top', None) is not None:
|
||||
|
||||
for test in [
|
||||
run_test_table_write,
|
||||
run_test_table_read,
|
||||
run_test_msix
|
||||
]:
|
||||
|
||||
factory = TestFactory(test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("axil_data_w", [32, 64])
|
||||
def test_taxi_pcie_msix_axil(request, axil_data_w):
|
||||
dut = "taxi_pcie_msix_axil"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
os.path.join(rtl_dir, "taxi_pcie_tlp_if.sv"),
|
||||
os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"),
|
||||
os.path.join(taxi_src_dir, "axi", "rtl", "taxi_axil_if.sv"),
|
||||
]
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['IRQ_INDEX_W'] = 11
|
||||
parameters['AXIL_DATA_W'] = axil_data_w
|
||||
parameters['AXIL_ADDR_W'] = parameters['IRQ_INDEX_W']+5
|
||||
parameters['TLP_FORCE_64_BIT_ADDR'] = 0
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
95
src/pcie/tb/taxi_pcie_msix_axil/test_taxi_pcie_msix_axil.sv
Normal file
95
src/pcie/tb/taxi_pcie_msix_axil/test_taxi_pcie_msix_axil.sv
Normal file
@@ -0,0 +1,95 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2026 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* PCIe MSI-X module testbench
|
||||
*/
|
||||
module test_taxi_pcie_msix_axil #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter IRQ_INDEX_W = 11,
|
||||
parameter TLP_SEG_DATA_W = 64,
|
||||
parameter TLP_SEGS = 1,
|
||||
parameter AXIL_DATA_W = 32,
|
||||
parameter AXIL_ADDR_W = IRQ_INDEX_W+5,
|
||||
parameter logic TLP_FORCE_64_BIT_ADDR = 1'b0
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axil_if #(
|
||||
.DATA_W(AXIL_DATA_W),
|
||||
.ADDR_W(AXIL_ADDR_W),
|
||||
.AWUSER_EN(1'b0),
|
||||
.WUSER_EN(1'b0),
|
||||
.BUSER_EN(1'b0),
|
||||
.ARUSER_EN(1'b0),
|
||||
.RUSER_EN(1'b0)
|
||||
) s_axil();
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(IRQ_INDEX_W),
|
||||
.KEEP_EN(0),
|
||||
.KEEP_W(1)
|
||||
) s_axis_irq();
|
||||
|
||||
taxi_pcie_tlp_if #(
|
||||
.SEGS(TLP_SEGS),
|
||||
.SEG_DATA_W(TLP_SEG_DATA_W),
|
||||
.FUNC_NUM_W(8)
|
||||
) tx_wr_req_tlp();
|
||||
|
||||
logic [7:0] bus_num;
|
||||
logic [7:0] func_num;
|
||||
logic msix_enable;
|
||||
logic msix_mask;
|
||||
|
||||
taxi_pcie_msix_axil #(
|
||||
.TLP_FORCE_64_BIT_ADDR(TLP_FORCE_64_BIT_ADDR)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI lite interface for MSI-X tables
|
||||
*/
|
||||
.s_axil_wr(s_axil),
|
||||
.s_axil_rd(s_axil),
|
||||
|
||||
/*
|
||||
* Interrupt request input
|
||||
*/
|
||||
.s_axis_irq(s_axis_irq),
|
||||
|
||||
/*
|
||||
* Memory write TLP output
|
||||
*/
|
||||
.tx_wr_req_tlp(tx_wr_req_tlp),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.bus_num(bus_num),
|
||||
.func_num(func_num),
|
||||
.msix_enable(msix_enable),
|
||||
.msix_mask(msix_mask)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user