eth: Clean up testbench parameters

Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-02-11 22:35:18 -08:00
parent 04b73e7ddf
commit 8a67eaa220
16 changed files with 10 additions and 24 deletions

View File

@@ -31,7 +31,6 @@ VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_DATA_W := 32
export PARAM_CTRL_W := $(shell expr $(PARAM_DATA_W) / 8 )
export PARAM_PTP_TS_EN := 1
export PARAM_PTP_TS_W := 96

View File

@@ -150,7 +150,6 @@ def test_taxi_axis_xgmii_rx_32(request):
parameters = {}
parameters['DATA_W'] = 32
parameters['CTRL_W'] = parameters['DATA_W'] // 8
parameters['PTP_TS_EN'] = 1
parameters['PTP_TS_W'] = 96

View File

@@ -19,13 +19,13 @@ module test_taxi_axis_xgmii_rx_32 #
(
/* verilator lint_off WIDTHTRUNC */
parameter DATA_W = 32,
parameter CTRL_W = (DATA_W/8),
parameter logic PTP_TS_EN = 1'b0,
parameter PTP_TS_W = 96
/* verilator lint_on WIDTHTRUNC */
)
();
localparam CTRL_W = DATA_W/8;
localparam USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1;
logic clk;