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pcie: Fix parametrization issues in MSI-X modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
@@ -71,7 +71,8 @@ localparam PBA_ADDR_W_INT = PBA_ADDR_W > 0 ? PBA_ADDR_W : 1;
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localparam INDEX_SHIFT = $clog2(64/8);
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localparam INDEX_SHIFT = $clog2(64/8);
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localparam WORD_SELECT_SHIFT = $clog2(APB_DATA_W/8);
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localparam WORD_SELECT_SHIFT = $clog2(APB_DATA_W/8);
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localparam WORD_SELECT_W = 64 > APB_DATA_W ? $clog2((64+7)/8) - $clog2(APB_DATA_W/8) : 0;
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localparam WORD_SELECT_W = 64 > APB_DATA_W ? $clog2((64+7)/8) - $clog2(APB_DATA_W/8) : 1;
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localparam RATIO = 64/APB_DATA_W;
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// bus width assertions
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// bus width assertions
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if (APB_STRB_W * 8 != APB_DATA_W)
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if (APB_STRB_W * 8 != APB_DATA_W)
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@@ -381,7 +382,7 @@ always_comb begin
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tbl_apb_mem_rd_en = 1'b0;
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tbl_apb_mem_rd_en = 1'b0;
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tbl_apb_mem_wr_en = 1'b0;
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tbl_apb_mem_wr_en = 1'b0;
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tbl_apb_mem_wr_be = 8'(s_apb.pstrb << (s_apb_paddr_word * APB_STRB_W));
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tbl_apb_mem_wr_be = 8'(s_apb.pstrb << (s_apb_paddr_word * APB_STRB_W));
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tbl_apb_mem_wr_data = {2**WORD_SELECT_W{s_apb.pwdata}};
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tbl_apb_mem_wr_data = {RATIO{s_apb.pwdata}};
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pba_apb_mem_rd_en = 1'b0;
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pba_apb_mem_rd_en = 1'b0;
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tbl_rd_data_valid_next = 1'b0;
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tbl_rd_data_valid_next = 1'b0;
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@@ -72,7 +72,8 @@ localparam PBA_ADDR_W_INT = PBA_ADDR_W > 0 ? PBA_ADDR_W : 1;
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localparam INDEX_SHIFT = $clog2(64/8);
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localparam INDEX_SHIFT = $clog2(64/8);
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localparam WORD_SELECT_SHIFT = $clog2(AXIL_DATA_W/8);
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localparam WORD_SELECT_SHIFT = $clog2(AXIL_DATA_W/8);
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localparam WORD_SELECT_W = 64 > AXIL_DATA_W ? $clog2((64+7)/8) - $clog2(AXIL_DATA_W/8) : 0;
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localparam WORD_SELECT_W = 64 > AXIL_DATA_W ? $clog2((64+7)/8) - $clog2(AXIL_DATA_W/8) : 1;
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localparam RATIO = 64/AXIL_DATA_W;
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// bus width assertions
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// bus width assertions
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if (AXIL_STRB_W * 8 != AXIL_DATA_W)
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if (AXIL_STRB_W * 8 != AXIL_DATA_W)
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@@ -399,7 +400,7 @@ always_comb begin
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tbl_axil_mem_rd_en = 1'b0;
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tbl_axil_mem_rd_en = 1'b0;
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tbl_axil_mem_wr_en = 1'b0;
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tbl_axil_mem_wr_en = 1'b0;
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tbl_axil_mem_wr_be = 8'(s_axil_wr.wstrb << (s_axil_awaddr_word * AXIL_STRB_W));
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tbl_axil_mem_wr_be = 8'(s_axil_wr.wstrb << (s_axil_awaddr_word * AXIL_STRB_W));
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tbl_axil_mem_wr_data = {2**WORD_SELECT_W{s_axil_wr.wdata}};
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tbl_axil_mem_wr_data = {RATIO{s_axil_wr.wdata}};
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pba_axil_mem_rd_en = 1'b0;
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pba_axil_mem_rd_en = 1'b0;
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tbl_rd_data_valid_next = tbl_rd_data_valid_reg;
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tbl_rd_data_valid_next = tbl_rd_data_valid_reg;
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