mirror of
https://github.com/fpganinja/taxi.git
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eth: Add UltraScale GT wrappers for 1000BASE-X MAC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
6
src/eth/rtl/us/taxi_eth_mac_1g_basex_us.f
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6
src/eth/rtl/us/taxi_eth_mac_1g_basex_us.f
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@@ -0,0 +1,6 @@
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taxi_eth_mac_1g_basex_us.sv
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taxi_eth_mac_1g_basex_us_ch.sv
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taxi_eth_phy_1g_basex_us_gt.f
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taxi_eth_phy_1g_basex_us_gt_ll.f
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../taxi_eth_mac_phy_1g_basex.f
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../../lib/taxi/src/apb/rtl/taxi_apb_interconnect_1s.sv
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669
src/eth/rtl/us/taxi_eth_mac_1g_basex_us.sv
Normal file
669
src/eth/rtl/us/taxi_eth_mac_1g_basex_us.sv
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@@ -0,0 +1,669 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2026 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Transceiver and MAC/PHY quad wrapper for UltraScale/UltraScale+
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*/
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module taxi_eth_mac_1g_basex_us #
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(
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parameter logic SIM = 1'b0,
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parameter string VENDOR = "XILINX",
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parameter string FAMILY = "virtexuplus",
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parameter CNT = 4,
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// GT config
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parameter logic CFG_LOW_LATENCY = 0,
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// GT type
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parameter string GT_TYPE = "GTY",
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// PLL parameters
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parameter logic QPLL0_PD = 1'b0,
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parameter logic QPLL1_PD = 1'b1,
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parameter logic QPLL0_EXT_CTRL = 1'b0,
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parameter logic QPLL1_EXT_CTRL = 1'b0,
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// GT parameters
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// TODO switch to packed arrays; blocked on Verilator bug
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parameter logic [CNT-1:0] GT_TX_PD = '0,
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parameter logic [CNT-1:0] GT_TX_QPLL_SEL = '0,
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parameter logic [CNT-1:0] GT_TX_POLARITY = '0,
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parameter logic [CNT-1:0] GT_TX_ELECIDLE = '0,
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parameter logic [CNT-1:0] GT_TX_INHIBIT = '0,
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parameter logic [CNT-1:0][4:0] GT_TX_DIFFCTRL = '{CNT{5'd16}},
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parameter logic [CNT-1:0][6:0] GT_TX_MAINCURSOR = '{CNT{7'd64}},
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parameter logic [CNT-1:0][4:0] GT_TX_POSTCURSOR = '{CNT{5'd0}},
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parameter logic [CNT-1:0][4:0] GT_TX_PRECURSOR = '{CNT{5'd0}},
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parameter logic [CNT-1:0] GT_RX_PD = '0,
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parameter logic [CNT-1:0] GT_RX_QPLL_SEL = '0,
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parameter logic [CNT-1:0] GT_RX_LPM_EN = '0,
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parameter logic [CNT-1:0] GT_RX_POLARITY = '0,
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// MAC/PHY parameters
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parameter logic COMBINED_MAC_PCS = 1'b1,
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parameter logic DIC_EN = 1'b1,
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parameter logic PTP_TS_EN = 1'b0,
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parameter logic PTP_TD_EN = PTP_TS_EN,
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parameter logic PTP_TS_FMT_TOD = 1'b1,
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parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64,
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parameter PTP_TD_SDI_PIPELINE = 2,
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parameter logic PRBS31_EN = 1'b0,
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parameter TX_SERDES_PIPELINE = 1,
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parameter RX_SERDES_PIPELINE = 1,
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parameter COUNT_125US = 125000/16,
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parameter logic PFC_EN = 1'b0,
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parameter logic PAUSE_EN = PFC_EN,
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parameter logic STAT_EN = 1'b0,
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parameter STAT_TX_LEVEL = 1,
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parameter STAT_RX_LEVEL = 1,
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parameter STAT_ID_BASE = 0,
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parameter STAT_UPDATE_PERIOD = 1024,
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parameter logic STAT_STR_EN = 1'b0,
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parameter logic [8*8-1:0] STAT_PREFIX_STR[CNT] = '{CNT{"MAC"}}
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)
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(
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input wire logic xcvr_ctrl_clk,
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input wire logic xcvr_ctrl_rst,
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/*
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* Transceiver control
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*/
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taxi_apb_if.slv s_apb_ctrl,
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/*
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* Common
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*/
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output wire logic xcvr_gtpowergood_out,
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input wire logic xcvr_gtrefclk00_in = 1'b0,
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input wire logic xcvr_qpll0pd_in = 1'b0,
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input wire logic xcvr_qpll0reset_in = 1'b0,
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input wire logic [2:0] xcvr_qpll0pcierate_in = 3'd0,
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output wire logic xcvr_qpll0lock_out,
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output wire logic xcvr_qpll0clk_out,
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output wire logic xcvr_qpll0refclk_out,
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input wire logic xcvr_gtrefclk01_in = 1'b0,
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input wire logic xcvr_qpll1pd_in = 1'b0,
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input wire logic xcvr_qpll1reset_in = 1'b0,
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input wire logic [2:0] xcvr_qpll1pcierate_in = 3'd0,
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output wire logic xcvr_qpll1lock_out,
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output wire logic xcvr_qpll1clk_out,
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output wire logic xcvr_qpll1refclk_out,
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/*
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* Serial data
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*/
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output wire logic xcvr_txp[CNT],
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output wire logic xcvr_txn[CNT],
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input wire logic xcvr_rxp[CNT],
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input wire logic xcvr_rxn[CNT],
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/*
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* MAC clocks
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*/
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output wire logic rx_clk[CNT],
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input wire logic rx_rst_in[CNT] = '{CNT{1'b0}},
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output wire logic rx_rst_out[CNT],
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output wire logic tx_clk[CNT],
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input wire logic tx_rst_in[CNT] = '{CNT{1'b0}},
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output wire logic tx_rst_out[CNT],
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/*
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* Transmit interface (AXI stream)
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*/
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taxi_axis_if.snk s_axis_tx[CNT],
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taxi_axis_if.src m_axis_tx_cpl[CNT],
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/*
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* Receive interface (AXI stream)
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*/
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taxi_axis_if.src m_axis_rx[CNT],
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/*
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* PTP clock
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*/
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input wire logic ptp_clk = 1'b0,
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input wire logic ptp_rst = 1'b0,
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input wire logic ptp_sample_clk = 1'b0,
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input wire logic ptp_td_sdi = 1'b0,
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input wire logic [PTP_TS_W-1:0] tx_ptp_ts_in[CNT] = '{CNT{'0}},
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output wire logic [PTP_TS_W-1:0] tx_ptp_ts_out[CNT],
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output wire logic tx_ptp_ts_step_out[CNT],
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output wire logic tx_ptp_locked[CNT],
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input wire logic [PTP_TS_W-1:0] rx_ptp_ts_in[CNT] = '{CNT{'0}},
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output wire logic [PTP_TS_W-1:0] rx_ptp_ts_out[CNT],
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output wire logic rx_ptp_ts_step_out[CNT],
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output wire logic rx_ptp_locked[CNT],
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/*
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* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
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*/
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input wire logic tx_lfc_req[CNT] = '{CNT{1'b0}},
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input wire logic tx_lfc_resend[CNT] = '{CNT{1'b0}},
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input wire logic rx_lfc_en[CNT] = '{CNT{1'b0}},
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output wire logic rx_lfc_req[CNT],
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input wire logic rx_lfc_ack[CNT] = '{CNT{1'b0}},
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/*
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* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
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*/
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input wire logic [7:0] tx_pfc_req[CNT] = '{CNT{'0}},
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input wire logic tx_pfc_resend[CNT] = '{CNT{1'b0}},
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input wire logic [7:0] rx_pfc_en[CNT] = '{CNT{'0}},
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output wire logic [7:0] rx_pfc_req[CNT],
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input wire logic [7:0] rx_pfc_ack[CNT] = '{CNT{'0}},
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/*
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* Pause interface
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*/
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input wire logic tx_lfc_pause_en[CNT] = '{CNT{1'b0}},
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input wire logic tx_pause_req[CNT] = '{CNT{1'b0}},
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output wire logic tx_pause_ack[CNT],
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/*
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* Statistics
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*/
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input wire logic stat_clk,
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input wire logic stat_rst,
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taxi_axis_if.src m_axis_stat,
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/*
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* Status
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*/
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output wire logic [1:0] tx_start_packet[CNT],
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output wire logic [1:0] stat_tx_byte[CNT],
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output wire logic [15:0] stat_tx_pkt_len[CNT],
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output wire logic stat_tx_pkt_ucast[CNT],
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output wire logic stat_tx_pkt_mcast[CNT],
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output wire logic stat_tx_pkt_bcast[CNT],
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output wire logic stat_tx_pkt_vlan[CNT],
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output wire logic stat_tx_pkt_good[CNT],
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output wire logic stat_tx_pkt_bad[CNT],
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output wire logic stat_tx_pad_frame[CNT],
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output wire logic stat_tx_err_oversize[CNT],
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output wire logic stat_tx_err_user[CNT],
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output wire logic stat_tx_err_underflow[CNT],
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output wire logic [1:0] rx_start_packet[CNT],
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output wire logic [4:0] rx_error_count[CNT],
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output wire logic rx_block_lock[CNT],
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output wire logic rx_high_ber[CNT],
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output wire logic rx_status[CNT],
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output wire logic [1:0] stat_rx_byte[CNT],
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output wire logic [15:0] stat_rx_pkt_len[CNT],
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output wire logic stat_rx_pkt_fragment[CNT],
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output wire logic stat_rx_pkt_jabber[CNT],
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output wire logic stat_rx_pkt_ucast[CNT],
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output wire logic stat_rx_pkt_mcast[CNT],
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output wire logic stat_rx_pkt_bcast[CNT],
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output wire logic stat_rx_pkt_vlan[CNT],
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output wire logic stat_rx_pkt_good[CNT],
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output wire logic stat_rx_pkt_bad[CNT],
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output wire logic stat_rx_err_oversize[CNT],
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output wire logic stat_rx_err_bad_fcs[CNT],
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output wire logic stat_rx_err_bad_block[CNT],
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output wire logic stat_rx_err_framing[CNT],
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output wire logic stat_rx_err_preamble[CNT],
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input wire logic stat_rx_fifo_drop[CNT] = '{CNT{1'b0}},
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output wire logic stat_tx_mcf[CNT],
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output wire logic stat_rx_mcf[CNT],
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output wire logic stat_tx_lfc_pkt[CNT],
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output wire logic stat_tx_lfc_xon[CNT],
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output wire logic stat_tx_lfc_xoff[CNT],
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output wire logic stat_tx_lfc_paused[CNT],
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output wire logic stat_tx_pfc_pkt[CNT],
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output wire logic [7:0] stat_tx_pfc_xon[CNT],
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output wire logic [7:0] stat_tx_pfc_xoff[CNT],
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output wire logic [7:0] stat_tx_pfc_paused[CNT],
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output wire logic stat_rx_lfc_pkt[CNT],
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output wire logic stat_rx_lfc_xon[CNT],
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output wire logic stat_rx_lfc_xoff[CNT],
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output wire logic stat_rx_lfc_paused[CNT],
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output wire logic stat_rx_pfc_pkt[CNT],
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output wire logic [7:0] stat_rx_pfc_xon[CNT],
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output wire logic [7:0] stat_rx_pfc_xoff[CNT],
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output wire logic [7:0] stat_rx_pfc_paused[CNT],
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/*
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* Configuration
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*/
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input wire logic cfg_tx_pad_en[CNT] = '{CNT{1'b1}},
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input wire logic [7:0] cfg_tx_min_pkt_len[CNT] = '{CNT{8'd60-1}},
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input wire logic [15:0] cfg_tx_max_pkt_len[CNT] = '{CNT{16'd1518-1}},
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input wire logic [7:0] cfg_tx_ifg[CNT] = '{CNT{8'd12}},
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input wire logic cfg_tx_enable[CNT] = '{CNT{1'b1}},
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input wire logic [15:0] cfg_rx_max_pkt_len[CNT] = '{CNT{16'd1518-1}},
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input wire logic cfg_rx_enable[CNT] = '{CNT{1'b1}},
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input wire logic [7:0] cfg_ifg[CNT] = '{CNT{8'd12}},
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input wire logic cfg_tx_prbs31_enable[CNT] = '{CNT{1'b0}},
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input wire logic cfg_rx_prbs31_enable[CNT] = '{CNT{1'b0}},
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input wire logic [47:0] cfg_mcf_rx_eth_dst_mcast[CNT] = '{CNT{48'h01_80_C2_00_00_01}},
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input wire logic cfg_mcf_rx_check_eth_dst_mcast[CNT] = '{CNT{1'b1}},
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input wire logic [47:0] cfg_mcf_rx_eth_dst_ucast[CNT] = '{CNT{48'd0}},
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input wire logic cfg_mcf_rx_check_eth_dst_ucast[CNT] = '{CNT{1'b0}},
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input wire logic [47:0] cfg_mcf_rx_eth_src[CNT] = '{CNT{48'd0}},
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input wire logic cfg_mcf_rx_check_eth_src[CNT] = '{CNT{1'b0}},
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input wire logic [15:0] cfg_mcf_rx_eth_type[CNT] = '{CNT{16'h8808}},
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input wire logic [15:0] cfg_mcf_rx_opcode_lfc[CNT] = '{CNT{16'h0001}},
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input wire logic cfg_mcf_rx_check_opcode_lfc[CNT] = '{CNT{1'b1}},
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input wire logic [15:0] cfg_mcf_rx_opcode_pfc[CNT] = '{CNT{16'h0101}},
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input wire logic cfg_mcf_rx_check_opcode_pfc[CNT] = '{CNT{1'b1}},
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input wire logic cfg_mcf_rx_forward[CNT] = '{CNT{1'b0}},
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input wire logic cfg_mcf_rx_enable[CNT] = '{CNT{1'b0}},
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input wire logic [47:0] cfg_tx_lfc_eth_dst[CNT] = '{CNT{48'h01_80_C2_00_00_01}},
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input wire logic [47:0] cfg_tx_lfc_eth_src[CNT] = '{CNT{48'h80_23_31_43_54_4C}},
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input wire logic [15:0] cfg_tx_lfc_eth_type[CNT] = '{CNT{16'h8808}},
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input wire logic [15:0] cfg_tx_lfc_opcode[CNT] = '{CNT{16'h0001}},
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input wire logic cfg_tx_lfc_en[CNT] = '{CNT{1'b0}},
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input wire logic [15:0] cfg_tx_lfc_quanta[CNT] = '{CNT{16'hffff}},
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input wire logic [15:0] cfg_tx_lfc_refresh[CNT] = '{CNT{16'h7fff}},
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input wire logic [47:0] cfg_tx_pfc_eth_dst[CNT] = '{CNT{48'h01_80_C2_00_00_01}},
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input wire logic [47:0] cfg_tx_pfc_eth_src[CNT] = '{CNT{48'h80_23_31_43_54_4C}},
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input wire logic [15:0] cfg_tx_pfc_eth_type[CNT] = '{CNT{16'h8808}},
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input wire logic [15:0] cfg_tx_pfc_opcode[CNT] = '{CNT{16'h0101}},
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input wire logic cfg_tx_pfc_en[CNT] = '{CNT{1'b0}},
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input wire logic [15:0] cfg_tx_pfc_quanta[CNT][8] = '{CNT{'{8{16'hffff}}}},
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input wire logic [15:0] cfg_tx_pfc_refresh[CNT][8] = '{CNT{'{8{16'h7fff}}}},
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input wire logic [15:0] cfg_rx_lfc_opcode[CNT] = '{CNT{16'h0001}},
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input wire logic cfg_rx_lfc_en[CNT] = '{CNT{1'b0}},
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input wire logic [15:0] cfg_rx_pfc_opcode[CNT] = '{CNT{16'h0101}},
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input wire logic cfg_rx_pfc_en[CNT] = '{CNT{1'b0}}
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);
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wire xcvr_ctrl_rst_sync;
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taxi_sync_reset #(
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.N(4)
|
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)
|
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reset_sync_inst (
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.clk(xcvr_ctrl_clk),
|
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.rst(xcvr_ctrl_rst),
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.out(xcvr_ctrl_rst_sync)
|
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);
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|
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// transceiver control
|
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taxi_apb_if #(
|
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.ADDR_W(16),
|
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.DATA_W(16)
|
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)
|
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ch_apb_ctrl[CNT]();
|
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|
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taxi_apb_interconnect_1s #(
|
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.M_CNT(CNT),
|
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.ADDR_W(s_apb_ctrl.ADDR_W),
|
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.M_REGIONS(1),
|
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.M_BASE_ADDR('0),
|
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.M_ADDR_W({CNT{{1{32'd16}}}})
|
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)
|
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ctrl_intercon_inst (
|
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.clk(xcvr_ctrl_clk),
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.rst(xcvr_ctrl_rst_sync),
|
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|
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/*
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* APB slave interface
|
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*/
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.s_apb(s_apb_ctrl),
|
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|
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/*
|
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* APB master interface
|
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*/
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.m_apb(ch_apb_ctrl)
|
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);
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// statistics
|
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localparam STAT_TX_CNT = STAT_TX_LEVEL == 0 ? 8 : (STAT_TX_LEVEL == 1 ? 16: 32);
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localparam STAT_RX_CNT = STAT_RX_LEVEL == 0 ? 8 : (STAT_RX_LEVEL == 1 ? 16: 32);
|
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|
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taxi_axis_if #(
|
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.DATA_W(m_axis_stat.DATA_W),
|
||||
.KEEP_EN(m_axis_stat.KEEP_EN),
|
||||
.KEEP_W(m_axis_stat.KEEP_W),
|
||||
.LAST_EN(m_axis_stat.LAST_EN),
|
||||
.ID_EN(m_axis_stat.ID_EN),
|
||||
.ID_W(m_axis_stat.ID_W),
|
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.USER_EN(m_axis_stat.USER_EN),
|
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.USER_W(m_axis_stat.USER_W)
|
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)
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axis_stat_int[CNT]();
|
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|
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if (STAT_EN) begin : stats
|
||||
|
||||
taxi_axis_arb_mux #(
|
||||
.S_COUNT(CNT),
|
||||
.UPDATE_TID(1'b0),
|
||||
.ARB_ROUND_ROBIN(1'b1),
|
||||
.ARB_LSB_HIGH_PRIO(1'b0)
|
||||
)
|
||||
stat_mux_inst (
|
||||
.clk(stat_clk),
|
||||
.rst(stat_rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream inputs (sink)
|
||||
*/
|
||||
.s_axis(axis_stat_int),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(m_axis_stat)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
for (genvar n = 0; n < CNT; n = n + 1) begin : ch
|
||||
|
||||
localparam HAS_COMMON = n == 0;
|
||||
|
||||
wire ch_gtpowergood_out;
|
||||
|
||||
wire ch_qpll0lock_out;
|
||||
wire ch_qpll0clk_out;
|
||||
wire ch_qpll0refclk_out;
|
||||
wire ch_qpll1lock_out;
|
||||
wire ch_qpll1clk_out;
|
||||
wire ch_qpll1refclk_out;
|
||||
|
||||
if (HAS_COMMON) begin
|
||||
// drive outputs from common
|
||||
assign xcvr_gtpowergood_out = ch_gtpowergood_out;
|
||||
|
||||
assign xcvr_qpll0lock_out = ch_qpll0lock_out;
|
||||
assign xcvr_qpll0clk_out = ch_qpll0clk_out;
|
||||
assign xcvr_qpll0refclk_out = ch_qpll0refclk_out;
|
||||
assign xcvr_qpll1lock_out = ch_qpll1lock_out;
|
||||
assign xcvr_qpll1clk_out = ch_qpll1clk_out;
|
||||
assign xcvr_qpll1refclk_out = ch_qpll1refclk_out;
|
||||
end
|
||||
|
||||
taxi_eth_mac_1g_basex_us_ch #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
|
||||
.HAS_COMMON(HAS_COMMON),
|
||||
|
||||
// GT config
|
||||
.CFG_LOW_LATENCY(CFG_LOW_LATENCY),
|
||||
|
||||
// GT type
|
||||
.GT_TYPE(GT_TYPE),
|
||||
|
||||
// PLL parameters
|
||||
.QPLL0_PD(QPLL0_PD),
|
||||
.QPLL1_PD(QPLL1_PD),
|
||||
.QPLL0_EXT_CTRL(QPLL0_EXT_CTRL),
|
||||
.QPLL1_EXT_CTRL(QPLL1_EXT_CTRL),
|
||||
|
||||
// GT parameters
|
||||
.GT_TX_PD(GT_TX_PD[n]),
|
||||
.GT_TX_QPLL_SEL(GT_TX_QPLL_SEL[n]),
|
||||
.GT_TX_POLARITY(GT_TX_POLARITY[n]),
|
||||
.GT_TX_ELECIDLE(GT_TX_ELECIDLE[n]),
|
||||
.GT_TX_INHIBIT(GT_TX_INHIBIT[n]),
|
||||
.GT_TX_DIFFCTRL(GT_TX_DIFFCTRL[n]),
|
||||
.GT_TX_MAINCURSOR(GT_TX_MAINCURSOR[n]),
|
||||
.GT_TX_POSTCURSOR(GT_TX_POSTCURSOR[n]),
|
||||
.GT_TX_PRECURSOR(GT_TX_PRECURSOR[n]),
|
||||
.GT_RX_PD(GT_RX_PD[n]),
|
||||
.GT_RX_QPLL_SEL(GT_RX_QPLL_SEL[n]),
|
||||
.GT_RX_LPM_EN(GT_RX_LPM_EN[n]),
|
||||
.GT_RX_POLARITY(GT_RX_POLARITY[n]),
|
||||
|
||||
// MAC/PHY parameters
|
||||
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
|
||||
.DIC_EN(DIC_EN),
|
||||
.PTP_TS_EN(PTP_TS_EN),
|
||||
.PTP_TD_EN(PTP_TD_EN),
|
||||
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
|
||||
.PTP_TS_W(PTP_TS_W),
|
||||
.PTP_TD_SDI_PIPELINE(PTP_TD_SDI_PIPELINE),
|
||||
.PRBS31_EN(PRBS31_EN),
|
||||
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
|
||||
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
|
||||
.COUNT_125US(COUNT_125US),
|
||||
.PFC_EN(PFC_EN),
|
||||
.PAUSE_EN(PAUSE_EN),
|
||||
.STAT_EN(STAT_EN),
|
||||
.STAT_TX_LEVEL(STAT_TX_LEVEL),
|
||||
.STAT_RX_LEVEL(STAT_RX_LEVEL),
|
||||
.STAT_ID_BASE(STAT_ID_BASE + n*(STAT_TX_CNT+STAT_RX_CNT)),
|
||||
.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD),
|
||||
.STAT_STR_EN(STAT_STR_EN),
|
||||
.STAT_PREFIX_STR(STAT_PREFIX_STR[n])
|
||||
)
|
||||
ch_inst (
|
||||
.xcvr_ctrl_clk(xcvr_ctrl_clk),
|
||||
.xcvr_ctrl_rst(xcvr_ctrl_rst_sync),
|
||||
|
||||
/*
|
||||
* Transceiver control
|
||||
*/
|
||||
.s_apb_ctrl(ch_apb_ctrl[n]),
|
||||
|
||||
/*
|
||||
* Common
|
||||
*/
|
||||
.xcvr_gtpowergood_out(ch_gtpowergood_out),
|
||||
|
||||
/*
|
||||
* PLL out
|
||||
*/
|
||||
.xcvr_gtrefclk00_in(xcvr_gtrefclk00_in),
|
||||
.xcvr_qpll0pd_in(xcvr_qpll0pd_in),
|
||||
.xcvr_qpll0reset_in(xcvr_qpll0reset_in),
|
||||
.xcvr_qpll0pcierate_in(xcvr_qpll0pcierate_in),
|
||||
.xcvr_qpll0lock_out(ch_qpll0lock_out),
|
||||
.xcvr_qpll0clk_out(ch_qpll0clk_out),
|
||||
.xcvr_qpll0refclk_out(ch_qpll0refclk_out),
|
||||
.xcvr_gtrefclk01_in(xcvr_gtrefclk01_in),
|
||||
.xcvr_qpll1pd_in(xcvr_qpll1pd_in),
|
||||
.xcvr_qpll1reset_in(xcvr_qpll1reset_in),
|
||||
.xcvr_qpll1pcierate_in(xcvr_qpll1pcierate_in),
|
||||
.xcvr_qpll1lock_out(ch_qpll1lock_out),
|
||||
.xcvr_qpll1clk_out(ch_qpll1clk_out),
|
||||
.xcvr_qpll1refclk_out(ch_qpll1refclk_out),
|
||||
|
||||
/*
|
||||
* PLL in
|
||||
*/
|
||||
.xcvr_qpll0lock_in(xcvr_qpll0lock_out),
|
||||
.xcvr_qpll0clk_in(xcvr_qpll0clk_out),
|
||||
.xcvr_qpll0refclk_in(xcvr_qpll0refclk_out),
|
||||
.xcvr_qpll1lock_in(xcvr_qpll1lock_out),
|
||||
.xcvr_qpll1clk_in(xcvr_qpll1clk_out),
|
||||
.xcvr_qpll1refclk_in(xcvr_qpll1refclk_out),
|
||||
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp(xcvr_txp[n]),
|
||||
.xcvr_txn(xcvr_txn[n]),
|
||||
.xcvr_rxp(xcvr_rxp[n]),
|
||||
.xcvr_rxn(xcvr_rxn[n]),
|
||||
|
||||
/*
|
||||
* MAC clocks
|
||||
*/
|
||||
.rx_clk(rx_clk[n]),
|
||||
.rx_rst_in(rx_rst_in[n]),
|
||||
.rx_rst_out(rx_rst_out[n]),
|
||||
.tx_clk(tx_clk[n]),
|
||||
.tx_rst_in(tx_rst_in[n]),
|
||||
.tx_rst_out(tx_rst_out[n]),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(s_axis_tx[n]),
|
||||
.m_axis_tx_cpl(m_axis_tx_cpl[n]),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(m_axis_rx[n]),
|
||||
|
||||
/*
|
||||
* PTP clock
|
||||
*/
|
||||
.ptp_clk(ptp_clk),
|
||||
.ptp_rst(ptp_rst),
|
||||
.ptp_sample_clk(ptp_sample_clk),
|
||||
.ptp_td_sdi(ptp_td_sdi),
|
||||
.tx_ptp_ts_in(tx_ptp_ts_in[n]),
|
||||
.tx_ptp_ts_out(tx_ptp_ts_out[n]),
|
||||
.tx_ptp_ts_step_out(tx_ptp_ts_step_out[n]),
|
||||
.tx_ptp_locked(tx_ptp_locked[n]),
|
||||
.rx_ptp_ts_in(rx_ptp_ts_in[n]),
|
||||
.rx_ptp_ts_out(rx_ptp_ts_out[n]),
|
||||
.rx_ptp_ts_step_out(rx_ptp_ts_step_out[n]),
|
||||
.rx_ptp_locked(rx_ptp_locked[n]),
|
||||
|
||||
/*
|
||||
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
|
||||
*/
|
||||
.tx_lfc_req(tx_lfc_req[n]),
|
||||
.tx_lfc_resend(tx_lfc_resend[n]),
|
||||
.rx_lfc_en(rx_lfc_en[n]),
|
||||
.rx_lfc_req(rx_lfc_req[n]),
|
||||
.rx_lfc_ack(rx_lfc_ack[n]),
|
||||
|
||||
/*
|
||||
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
|
||||
*/
|
||||
.tx_pfc_req(tx_pfc_req[n]),
|
||||
.tx_pfc_resend(tx_pfc_resend[n]),
|
||||
.rx_pfc_en(rx_pfc_en[n]),
|
||||
.rx_pfc_req(rx_pfc_req[n]),
|
||||
.rx_pfc_ack(rx_pfc_ack[n]),
|
||||
|
||||
/*
|
||||
* Pause interface
|
||||
*/
|
||||
.tx_lfc_pause_en(tx_lfc_pause_en[n]),
|
||||
.tx_pause_req(tx_pause_req[n]),
|
||||
.tx_pause_ack(tx_pause_ack[n]),
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
.stat_clk(stat_clk),
|
||||
.stat_rst(stat_rst),
|
||||
.m_axis_stat(axis_stat_int[n]),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_start_packet(tx_start_packet[n]),
|
||||
.stat_tx_byte(stat_tx_byte[n]),
|
||||
.stat_tx_pkt_len(stat_tx_pkt_len[n]),
|
||||
.stat_tx_pkt_ucast(stat_tx_pkt_ucast[n]),
|
||||
.stat_tx_pkt_mcast(stat_tx_pkt_mcast[n]),
|
||||
.stat_tx_pkt_bcast(stat_tx_pkt_bcast[n]),
|
||||
.stat_tx_pkt_vlan(stat_tx_pkt_vlan[n]),
|
||||
.stat_tx_pkt_good(stat_tx_pkt_good[n]),
|
||||
.stat_tx_pkt_bad(stat_tx_pkt_bad[n]),
|
||||
.stat_tx_pad_frame(stat_tx_pad_frame[n]),
|
||||
.stat_tx_err_oversize(stat_tx_err_oversize[n]),
|
||||
.stat_tx_err_user(stat_tx_err_user[n]),
|
||||
.stat_tx_err_underflow(stat_tx_err_underflow[n]),
|
||||
.rx_start_packet(rx_start_packet[n]),
|
||||
.rx_error_count(rx_error_count[n]),
|
||||
.rx_block_lock(rx_block_lock[n]),
|
||||
.rx_high_ber(rx_high_ber[n]),
|
||||
.rx_status(rx_status[n]),
|
||||
.stat_rx_byte(stat_rx_byte[n]),
|
||||
.stat_rx_pkt_len(stat_rx_pkt_len[n]),
|
||||
.stat_rx_pkt_fragment(stat_rx_pkt_fragment[n]),
|
||||
.stat_rx_pkt_jabber(stat_rx_pkt_jabber[n]),
|
||||
.stat_rx_pkt_ucast(stat_rx_pkt_ucast[n]),
|
||||
.stat_rx_pkt_mcast(stat_rx_pkt_mcast[n]),
|
||||
.stat_rx_pkt_bcast(stat_rx_pkt_bcast[n]),
|
||||
.stat_rx_pkt_vlan(stat_rx_pkt_vlan[n]),
|
||||
.stat_rx_pkt_good(stat_rx_pkt_good[n]),
|
||||
.stat_rx_pkt_bad(stat_rx_pkt_bad[n]),
|
||||
.stat_rx_err_oversize(stat_rx_err_oversize[n]),
|
||||
.stat_rx_err_bad_fcs(stat_rx_err_bad_fcs[n]),
|
||||
.stat_rx_err_bad_block(stat_rx_err_bad_block[n]),
|
||||
.stat_rx_err_framing(stat_rx_err_framing[n]),
|
||||
.stat_rx_err_preamble(stat_rx_err_preamble[n]),
|
||||
.stat_rx_fifo_drop(stat_rx_fifo_drop[n]),
|
||||
.stat_tx_mcf(stat_tx_mcf[n]),
|
||||
.stat_rx_mcf(stat_rx_mcf[n]),
|
||||
.stat_tx_lfc_pkt(stat_tx_lfc_pkt[n]),
|
||||
.stat_tx_lfc_xon(stat_tx_lfc_xon[n]),
|
||||
.stat_tx_lfc_xoff(stat_tx_lfc_xoff[n]),
|
||||
.stat_tx_lfc_paused(stat_tx_lfc_paused[n]),
|
||||
.stat_tx_pfc_pkt(stat_tx_pfc_pkt[n]),
|
||||
.stat_tx_pfc_xon(stat_tx_pfc_xon[n]),
|
||||
.stat_tx_pfc_xoff(stat_tx_pfc_xoff[n]),
|
||||
.stat_tx_pfc_paused(stat_tx_pfc_paused[n]),
|
||||
.stat_rx_lfc_pkt(stat_rx_lfc_pkt[n]),
|
||||
.stat_rx_lfc_xon(stat_rx_lfc_xon[n]),
|
||||
.stat_rx_lfc_xoff(stat_rx_lfc_xoff[n]),
|
||||
.stat_rx_lfc_paused(stat_rx_lfc_paused[n]),
|
||||
.stat_rx_pfc_pkt(stat_rx_pfc_pkt[n]),
|
||||
.stat_rx_pfc_xon(stat_rx_pfc_xon[n]),
|
||||
.stat_rx_pfc_xoff(stat_rx_pfc_xoff[n]),
|
||||
.stat_rx_pfc_paused(stat_rx_pfc_paused[n]),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_tx_pad_en(cfg_tx_pad_en[n]),
|
||||
.cfg_tx_min_pkt_len(cfg_tx_min_pkt_len[n]),
|
||||
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len[n]),
|
||||
.cfg_tx_ifg(cfg_tx_ifg[n]),
|
||||
.cfg_tx_enable(cfg_tx_enable[n]),
|
||||
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len[n]),
|
||||
.cfg_rx_enable(cfg_rx_enable[n]),
|
||||
.cfg_tx_prbs31_enable(cfg_tx_prbs31_enable[n]),
|
||||
.cfg_rx_prbs31_enable(cfg_rx_prbs31_enable[n]),
|
||||
.cfg_mcf_rx_eth_dst_mcast(cfg_mcf_rx_eth_dst_mcast[n]),
|
||||
.cfg_mcf_rx_check_eth_dst_mcast(cfg_mcf_rx_check_eth_dst_mcast[n]),
|
||||
.cfg_mcf_rx_eth_dst_ucast(cfg_mcf_rx_eth_dst_ucast[n]),
|
||||
.cfg_mcf_rx_check_eth_dst_ucast(cfg_mcf_rx_check_eth_dst_ucast[n]),
|
||||
.cfg_mcf_rx_eth_src(cfg_mcf_rx_eth_src[n]),
|
||||
.cfg_mcf_rx_check_eth_src(cfg_mcf_rx_check_eth_src[n]),
|
||||
.cfg_mcf_rx_eth_type(cfg_mcf_rx_eth_type[n]),
|
||||
.cfg_mcf_rx_opcode_lfc(cfg_mcf_rx_opcode_lfc[n]),
|
||||
.cfg_mcf_rx_check_opcode_lfc(cfg_mcf_rx_check_opcode_lfc[n]),
|
||||
.cfg_mcf_rx_opcode_pfc(cfg_mcf_rx_opcode_pfc[n]),
|
||||
.cfg_mcf_rx_check_opcode_pfc(cfg_mcf_rx_check_opcode_pfc[n]),
|
||||
.cfg_mcf_rx_forward(cfg_mcf_rx_forward[n]),
|
||||
.cfg_mcf_rx_enable(cfg_mcf_rx_enable[n]),
|
||||
.cfg_tx_lfc_eth_dst(cfg_tx_lfc_eth_dst[n]),
|
||||
.cfg_tx_lfc_eth_src(cfg_tx_lfc_eth_src[n]),
|
||||
.cfg_tx_lfc_eth_type(cfg_tx_lfc_eth_type[n]),
|
||||
.cfg_tx_lfc_opcode(cfg_tx_lfc_opcode[n]),
|
||||
.cfg_tx_lfc_en(cfg_tx_lfc_en[n]),
|
||||
.cfg_tx_lfc_quanta(cfg_tx_lfc_quanta[n]),
|
||||
.cfg_tx_lfc_refresh(cfg_tx_lfc_refresh[n]),
|
||||
.cfg_tx_pfc_eth_dst(cfg_tx_pfc_eth_dst[n]),
|
||||
.cfg_tx_pfc_eth_src(cfg_tx_pfc_eth_src[n]),
|
||||
.cfg_tx_pfc_eth_type(cfg_tx_pfc_eth_type[n]),
|
||||
.cfg_tx_pfc_opcode(cfg_tx_pfc_opcode[n]),
|
||||
.cfg_tx_pfc_en(cfg_tx_pfc_en[n]),
|
||||
.cfg_tx_pfc_quanta(cfg_tx_pfc_quanta[n]),
|
||||
.cfg_tx_pfc_refresh(cfg_tx_pfc_refresh[n]),
|
||||
.cfg_rx_lfc_opcode(cfg_rx_lfc_opcode[n]),
|
||||
.cfg_rx_lfc_en(cfg_rx_lfc_en[n]),
|
||||
.cfg_rx_pfc_opcode(cfg_rx_pfc_opcode[n]),
|
||||
.cfg_rx_pfc_en(cfg_rx_pfc_en[n])
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
768
src/eth/rtl/us/taxi_eth_mac_1g_basex_us_ch.sv
Normal file
768
src/eth/rtl/us/taxi_eth_mac_1g_basex_us_ch.sv
Normal file
@@ -0,0 +1,768 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* Transceiver and MAC/PHY wrapper for UltraScale/UltraScale+
|
||||
*/
|
||||
module taxi_eth_mac_1g_basex_us_ch #
|
||||
(
|
||||
parameter logic SIM = 1'b0,
|
||||
parameter string VENDOR = "XILINX",
|
||||
parameter string FAMILY = "virtexuplus",
|
||||
|
||||
parameter logic HAS_COMMON = 1'b1,
|
||||
|
||||
// GT config
|
||||
parameter logic CFG_LOW_LATENCY = 0,
|
||||
|
||||
// GT type
|
||||
parameter string GT_TYPE = "GTY",
|
||||
|
||||
// PLL parameters
|
||||
parameter logic QPLL0_PD = 1'b0,
|
||||
parameter logic QPLL1_PD = 1'b1,
|
||||
parameter logic QPLL0_EXT_CTRL = 1'b0,
|
||||
parameter logic QPLL1_EXT_CTRL = 1'b0,
|
||||
|
||||
// GT parameters
|
||||
parameter logic GT_TX_PD = 1'b0,
|
||||
parameter logic GT_TX_QPLL_SEL = 1'b0,
|
||||
parameter logic GT_TX_POLARITY = 1'b0,
|
||||
parameter logic GT_TX_ELECIDLE = 1'b0,
|
||||
parameter logic GT_TX_INHIBIT = 1'b0,
|
||||
parameter logic [4:0] GT_TX_DIFFCTRL = 5'd16,
|
||||
parameter logic [6:0] GT_TX_MAINCURSOR = 7'd64,
|
||||
parameter logic [4:0] GT_TX_POSTCURSOR = 5'd0,
|
||||
parameter logic [4:0] GT_TX_PRECURSOR = 5'd0,
|
||||
parameter logic GT_RX_PD = 1'b0,
|
||||
parameter logic GT_RX_QPLL_SEL = 1'b0,
|
||||
parameter logic GT_RX_LPM_EN = 1'b0,
|
||||
parameter logic GT_RX_POLARITY = 1'b0,
|
||||
|
||||
// MAC/PHY parameters
|
||||
parameter logic COMBINED_MAC_PCS = 1'b1,
|
||||
parameter logic DIC_EN = 1'b1,
|
||||
parameter logic PTP_TS_EN = 1'b0,
|
||||
parameter logic PTP_TD_EN = PTP_TS_EN,
|
||||
parameter logic PTP_TS_FMT_TOD = 1'b1,
|
||||
parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64,
|
||||
parameter PTP_TD_SDI_PIPELINE = 2,
|
||||
parameter logic PRBS31_EN = 1'b0,
|
||||
parameter TX_SERDES_PIPELINE = 1,
|
||||
parameter RX_SERDES_PIPELINE = 1,
|
||||
parameter COUNT_125US = 125000/16,
|
||||
parameter logic PFC_EN = 1'b0,
|
||||
parameter logic PAUSE_EN = PFC_EN,
|
||||
parameter logic STAT_EN = 1'b0,
|
||||
parameter STAT_TX_LEVEL = 1,
|
||||
parameter STAT_RX_LEVEL = 1,
|
||||
parameter STAT_ID_BASE = 0,
|
||||
parameter STAT_UPDATE_PERIOD = 1024,
|
||||
parameter logic STAT_STR_EN = 1'b0,
|
||||
parameter logic [8*8-1:0] STAT_PREFIX_STR = "MAC"
|
||||
)
|
||||
(
|
||||
input wire logic xcvr_ctrl_clk,
|
||||
input wire logic xcvr_ctrl_rst,
|
||||
|
||||
/*
|
||||
* Transceiver control
|
||||
*/
|
||||
taxi_apb_if.slv s_apb_ctrl,
|
||||
|
||||
/*
|
||||
* Common
|
||||
*/
|
||||
output wire logic xcvr_gtpowergood_out,
|
||||
|
||||
/*
|
||||
* PLL out
|
||||
*/
|
||||
input wire logic xcvr_gtrefclk00_in = 1'b0,
|
||||
input wire logic xcvr_qpll0pd_in = 1'b0,
|
||||
input wire logic xcvr_qpll0reset_in = 1'b0,
|
||||
input wire logic [2:0] xcvr_qpll0pcierate_in = 3'd0,
|
||||
output wire logic xcvr_qpll0lock_out,
|
||||
output wire logic xcvr_qpll0clk_out,
|
||||
output wire logic xcvr_qpll0refclk_out,
|
||||
input wire logic xcvr_gtrefclk01_in = 1'b0,
|
||||
input wire logic xcvr_qpll1pd_in = 1'b0,
|
||||
input wire logic xcvr_qpll1reset_in = 1'b0,
|
||||
input wire logic [2:0] xcvr_qpll1pcierate_in = 3'd0,
|
||||
output wire logic xcvr_qpll1lock_out,
|
||||
output wire logic xcvr_qpll1clk_out,
|
||||
output wire logic xcvr_qpll1refclk_out,
|
||||
|
||||
/*
|
||||
* PLL in
|
||||
*/
|
||||
input wire logic xcvr_qpll0lock_in = 1'b0,
|
||||
input wire logic xcvr_qpll0clk_in = 1'b0,
|
||||
input wire logic xcvr_qpll0refclk_in = 1'b0,
|
||||
input wire logic xcvr_qpll1lock_in = 1'b0,
|
||||
input wire logic xcvr_qpll1clk_in = 1'b0,
|
||||
input wire logic xcvr_qpll1refclk_in = 1'b0,
|
||||
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
output wire logic xcvr_txp,
|
||||
output wire logic xcvr_txn,
|
||||
input wire logic xcvr_rxp,
|
||||
input wire logic xcvr_rxn,
|
||||
|
||||
/*
|
||||
* MAC clocks
|
||||
*/
|
||||
output wire logic rx_clk,
|
||||
input wire logic rx_rst_in = 1'b0,
|
||||
output wire logic rx_rst_out,
|
||||
output wire logic tx_clk,
|
||||
input wire logic tx_rst_in = 1'b0,
|
||||
output wire logic tx_rst_out,
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
taxi_axis_if.snk s_axis_tx,
|
||||
taxi_axis_if.src m_axis_tx_cpl,
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
taxi_axis_if.src m_axis_rx,
|
||||
|
||||
/*
|
||||
* PTP clock
|
||||
*/
|
||||
input wire logic ptp_clk = 1'b0,
|
||||
input wire logic ptp_rst = 1'b0,
|
||||
input wire logic ptp_sample_clk = 1'b0,
|
||||
input wire logic ptp_td_sdi = 1'b0,
|
||||
input wire logic [PTP_TS_W-1:0] tx_ptp_ts_in = '0,
|
||||
output wire logic [PTP_TS_W-1:0] tx_ptp_ts_out,
|
||||
output wire logic tx_ptp_ts_step_out,
|
||||
output wire logic tx_ptp_locked,
|
||||
input wire logic [PTP_TS_W-1:0] rx_ptp_ts_in = '0,
|
||||
output wire logic [PTP_TS_W-1:0] rx_ptp_ts_out,
|
||||
output wire logic rx_ptp_ts_step_out,
|
||||
output wire logic rx_ptp_locked,
|
||||
|
||||
/*
|
||||
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
|
||||
*/
|
||||
input wire logic tx_lfc_req = 1'b0,
|
||||
input wire logic tx_lfc_resend = 1'b0,
|
||||
input wire logic rx_lfc_en = 1'b0,
|
||||
output wire logic rx_lfc_req,
|
||||
input wire logic rx_lfc_ack = 1'b0,
|
||||
|
||||
/*
|
||||
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
|
||||
*/
|
||||
input wire logic [7:0] tx_pfc_req = '0,
|
||||
input wire logic tx_pfc_resend = 1'b0,
|
||||
input wire logic [7:0] rx_pfc_en = '0,
|
||||
output wire logic [7:0] rx_pfc_req,
|
||||
input wire logic [7:0] rx_pfc_ack = '0,
|
||||
|
||||
/*
|
||||
* Pause interface
|
||||
*/
|
||||
input wire logic tx_lfc_pause_en = 1'b0,
|
||||
input wire logic tx_pause_req = 1'b0,
|
||||
output wire logic tx_pause_ack,
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
input wire logic stat_clk,
|
||||
input wire logic stat_rst,
|
||||
taxi_axis_if.src m_axis_stat,
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
output wire logic [1:0] tx_start_packet,
|
||||
output wire logic [1:0] stat_tx_byte,
|
||||
output wire logic [15:0] stat_tx_pkt_len,
|
||||
output wire logic stat_tx_pkt_ucast,
|
||||
output wire logic stat_tx_pkt_mcast,
|
||||
output wire logic stat_tx_pkt_bcast,
|
||||
output wire logic stat_tx_pkt_vlan,
|
||||
output wire logic stat_tx_pkt_good,
|
||||
output wire logic stat_tx_pkt_bad,
|
||||
output wire logic stat_tx_pad_frame,
|
||||
output wire logic stat_tx_err_oversize,
|
||||
output wire logic stat_tx_err_user,
|
||||
output wire logic stat_tx_err_underflow,
|
||||
output wire logic [1:0] rx_start_packet,
|
||||
output wire logic [4:0] rx_error_count,
|
||||
output wire logic rx_block_lock,
|
||||
output wire logic rx_high_ber,
|
||||
output wire logic rx_status,
|
||||
output wire logic [1:0] stat_rx_byte,
|
||||
output wire logic [15:0] stat_rx_pkt_len,
|
||||
output wire logic stat_rx_pkt_fragment,
|
||||
output wire logic stat_rx_pkt_jabber,
|
||||
output wire logic stat_rx_pkt_ucast,
|
||||
output wire logic stat_rx_pkt_mcast,
|
||||
output wire logic stat_rx_pkt_bcast,
|
||||
output wire logic stat_rx_pkt_vlan,
|
||||
output wire logic stat_rx_pkt_good,
|
||||
output wire logic stat_rx_pkt_bad,
|
||||
output wire logic stat_rx_err_oversize,
|
||||
output wire logic stat_rx_err_bad_fcs,
|
||||
output wire logic stat_rx_err_bad_block,
|
||||
output wire logic stat_rx_err_framing,
|
||||
output wire logic stat_rx_err_preamble,
|
||||
input wire logic stat_rx_fifo_drop = 1'b0,
|
||||
output wire logic stat_tx_mcf,
|
||||
output wire logic stat_rx_mcf,
|
||||
output wire logic stat_tx_lfc_pkt,
|
||||
output wire logic stat_tx_lfc_xon,
|
||||
output wire logic stat_tx_lfc_xoff,
|
||||
output wire logic stat_tx_lfc_paused,
|
||||
output wire logic stat_tx_pfc_pkt,
|
||||
output wire logic [7:0] stat_tx_pfc_xon,
|
||||
output wire logic [7:0] stat_tx_pfc_xoff,
|
||||
output wire logic [7:0] stat_tx_pfc_paused,
|
||||
output wire logic stat_rx_lfc_pkt,
|
||||
output wire logic stat_rx_lfc_xon,
|
||||
output wire logic stat_rx_lfc_xoff,
|
||||
output wire logic stat_rx_lfc_paused,
|
||||
output wire logic stat_rx_pfc_pkt,
|
||||
output wire logic [7:0] stat_rx_pfc_xon,
|
||||
output wire logic [7:0] stat_rx_pfc_xoff,
|
||||
output wire logic [7:0] stat_rx_pfc_paused,
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
input wire logic cfg_tx_pad_en = 1'b1,
|
||||
input wire logic [7:0] cfg_tx_min_pkt_len = 8'd60-1,
|
||||
input wire logic [15:0] cfg_tx_max_pkt_len = 16'd1518-1,
|
||||
input wire logic [7:0] cfg_tx_ifg = 8'd12,
|
||||
input wire logic cfg_tx_enable = 1'b1,
|
||||
input wire logic [15:0] cfg_rx_max_pkt_len = 16'd1518-1,
|
||||
input wire logic cfg_rx_enable = 1'b1,
|
||||
input wire logic cfg_tx_prbs31_enable = 1'b0,
|
||||
input wire logic cfg_rx_prbs31_enable = 1'b0,
|
||||
input wire logic [47:0] cfg_mcf_rx_eth_dst_mcast = 48'h01_80_C2_00_00_01,
|
||||
input wire logic cfg_mcf_rx_check_eth_dst_mcast = 1'b1,
|
||||
input wire logic [47:0] cfg_mcf_rx_eth_dst_ucast = 48'd0,
|
||||
input wire logic cfg_mcf_rx_check_eth_dst_ucast = 1'b0,
|
||||
input wire logic [47:0] cfg_mcf_rx_eth_src = 48'd0,
|
||||
input wire logic cfg_mcf_rx_check_eth_src = 1'b0,
|
||||
input wire logic [15:0] cfg_mcf_rx_eth_type = 16'h8808,
|
||||
input wire logic [15:0] cfg_mcf_rx_opcode_lfc = 16'h0001,
|
||||
input wire logic cfg_mcf_rx_check_opcode_lfc = 1'b1,
|
||||
input wire logic [15:0] cfg_mcf_rx_opcode_pfc = 16'h0101,
|
||||
input wire logic cfg_mcf_rx_check_opcode_pfc = 1'b1,
|
||||
input wire logic cfg_mcf_rx_forward = 1'b0,
|
||||
input wire logic cfg_mcf_rx_enable = 1'b0,
|
||||
input wire logic [47:0] cfg_tx_lfc_eth_dst = 48'h01_80_C2_00_00_01,
|
||||
input wire logic [47:0] cfg_tx_lfc_eth_src = 48'h80_23_31_43_54_4C,
|
||||
input wire logic [15:0] cfg_tx_lfc_eth_type = 16'h8808,
|
||||
input wire logic [15:0] cfg_tx_lfc_opcode = 16'h0001,
|
||||
input wire logic cfg_tx_lfc_en = 1'b0,
|
||||
input wire logic [15:0] cfg_tx_lfc_quanta = 16'hffff,
|
||||
input wire logic [15:0] cfg_tx_lfc_refresh = 16'h7fff,
|
||||
input wire logic [47:0] cfg_tx_pfc_eth_dst = 48'h01_80_C2_00_00_01,
|
||||
input wire logic [47:0] cfg_tx_pfc_eth_src = 48'h80_23_31_43_54_4C,
|
||||
input wire logic [15:0] cfg_tx_pfc_eth_type = 16'h8808,
|
||||
input wire logic [15:0] cfg_tx_pfc_opcode = 16'h0101,
|
||||
input wire logic cfg_tx_pfc_en = 1'b0,
|
||||
input wire logic [15:0] cfg_tx_pfc_quanta[8] = '{8{16'hffff}},
|
||||
input wire logic [15:0] cfg_tx_pfc_refresh[8] = '{8{16'h7fff}},
|
||||
input wire logic [15:0] cfg_rx_lfc_opcode = 16'h0001,
|
||||
input wire logic cfg_rx_lfc_en = 1'b0,
|
||||
input wire logic [15:0] cfg_rx_pfc_opcode = 16'h0101,
|
||||
input wire logic cfg_rx_pfc_en = 1'b0
|
||||
);
|
||||
|
||||
localparam GT_7 = FAMILY == "virtex7" || FAMILY == "kintex7" || FAMILY == "artix7";
|
||||
localparam GBX_EN = 0;
|
||||
|
||||
localparam DATA_W = 16;
|
||||
localparam CTRL_W = DATA_W/8;
|
||||
|
||||
wire rx_reset_req;
|
||||
|
||||
wire [DATA_W-1:0] serdes_tx_data;
|
||||
wire [CTRL_W-1:0] serdes_tx_data_k;
|
||||
wire [CTRL_W-1:0] serdes_tx_data_dm;
|
||||
wire [CTRL_W-1:0] serdes_tx_data_dv;
|
||||
wire serdes_tx_data_valid;
|
||||
wire serdes_tx_gbx_req_sync;
|
||||
wire serdes_tx_gbx_req_stall;
|
||||
wire serdes_tx_gbx_sync;
|
||||
wire [DATA_W-1:0] serdes_rx_data;
|
||||
wire [CTRL_W-1:0] serdes_rx_data_k;
|
||||
wire serdes_rx_data_valid;
|
||||
|
||||
if (GT_7) begin : gt
|
||||
|
||||
$fatal(0, "Error: configuration not currently supported (%m)");
|
||||
|
||||
end else if (CFG_LOW_LATENCY) begin : gt
|
||||
|
||||
taxi_eth_phy_1g_basex_us_gt_ll #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
|
||||
.HAS_COMMON(HAS_COMMON),
|
||||
|
||||
// GT type
|
||||
.GT_TYPE(GT_TYPE),
|
||||
|
||||
// PLL parameters
|
||||
.QPLL0_PD(QPLL0_PD),
|
||||
.QPLL1_PD(QPLL1_PD),
|
||||
.QPLL0_EXT_CTRL(QPLL0_EXT_CTRL),
|
||||
.QPLL1_EXT_CTRL(QPLL1_EXT_CTRL),
|
||||
|
||||
// GT parameters
|
||||
.GT_TX_PD(GT_TX_PD),
|
||||
.GT_TX_QPLL_SEL(GT_TX_QPLL_SEL),
|
||||
.GT_TX_POLARITY(GT_TX_POLARITY),
|
||||
.GT_TX_ELECIDLE(GT_TX_ELECIDLE),
|
||||
.GT_TX_INHIBIT(GT_TX_INHIBIT),
|
||||
.GT_TX_DIFFCTRL(GT_TX_DIFFCTRL),
|
||||
.GT_TX_MAINCURSOR(GT_TX_MAINCURSOR),
|
||||
.GT_TX_POSTCURSOR(GT_TX_POSTCURSOR),
|
||||
.GT_TX_PRECURSOR(GT_TX_PRECURSOR),
|
||||
.GT_RX_PD(GT_RX_PD),
|
||||
.GT_RX_QPLL_SEL(GT_RX_QPLL_SEL),
|
||||
.GT_RX_LPM_EN(GT_RX_LPM_EN),
|
||||
.GT_RX_POLARITY(GT_RX_POLARITY),
|
||||
|
||||
// MAC/PHY parameters
|
||||
.DATA_W(DATA_W),
|
||||
.CTRL_W(CTRL_W)
|
||||
)
|
||||
gt_inst (
|
||||
.xcvr_ctrl_clk(xcvr_ctrl_clk),
|
||||
.xcvr_ctrl_rst(xcvr_ctrl_rst),
|
||||
|
||||
/*
|
||||
* Transceiver control
|
||||
*/
|
||||
.s_apb_ctrl(s_apb_ctrl),
|
||||
|
||||
/*
|
||||
* Common
|
||||
*/
|
||||
.xcvr_gtpowergood_out(xcvr_gtpowergood_out),
|
||||
|
||||
/*
|
||||
* PLL out
|
||||
*/
|
||||
.xcvr_gtrefclk00_in(xcvr_gtrefclk00_in),
|
||||
.xcvr_qpll0pd_in(xcvr_qpll0pd_in),
|
||||
.xcvr_qpll0reset_in(xcvr_qpll0reset_in),
|
||||
.xcvr_qpll0pcierate_in(xcvr_qpll0pcierate_in),
|
||||
.xcvr_qpll0lock_out(xcvr_qpll0lock_out),
|
||||
.xcvr_qpll0clk_out(xcvr_qpll0clk_out),
|
||||
.xcvr_qpll0refclk_out(xcvr_qpll0refclk_out),
|
||||
.xcvr_gtrefclk01_in(xcvr_gtrefclk01_in),
|
||||
.xcvr_qpll1pd_in(xcvr_qpll1pd_in),
|
||||
.xcvr_qpll1reset_in(xcvr_qpll1reset_in),
|
||||
.xcvr_qpll1pcierate_in(xcvr_qpll1pcierate_in),
|
||||
.xcvr_qpll1lock_out(xcvr_qpll1lock_out),
|
||||
.xcvr_qpll1clk_out(xcvr_qpll1clk_out),
|
||||
.xcvr_qpll1refclk_out(xcvr_qpll1refclk_out),
|
||||
|
||||
/*
|
||||
* PLL in
|
||||
*/
|
||||
.xcvr_qpll0lock_in(xcvr_qpll0lock_in),
|
||||
.xcvr_qpll0clk_in(xcvr_qpll0clk_in),
|
||||
.xcvr_qpll0refclk_in(xcvr_qpll0refclk_in),
|
||||
.xcvr_qpll1lock_in(xcvr_qpll1lock_in),
|
||||
.xcvr_qpll1clk_in(xcvr_qpll1clk_in),
|
||||
.xcvr_qpll1refclk_in(xcvr_qpll1refclk_in),
|
||||
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp(xcvr_txp),
|
||||
.xcvr_txn(xcvr_txn),
|
||||
.xcvr_rxp(xcvr_rxp),
|
||||
.xcvr_rxn(xcvr_rxn),
|
||||
|
||||
/*
|
||||
* GT user clocks
|
||||
*/
|
||||
.rx_clk(rx_clk),
|
||||
.rx_rst_in(rx_rst_in || rx_reset_req),
|
||||
.rx_rst_out(rx_rst_out),
|
||||
.tx_clk(tx_clk),
|
||||
.tx_rst_in(tx_rst_in),
|
||||
.tx_rst_out(tx_rst_out),
|
||||
|
||||
/*
|
||||
* Serdes interface
|
||||
*/
|
||||
.serdes_tx_data(serdes_tx_data),
|
||||
.serdes_tx_data_k(serdes_tx_data_k),
|
||||
.serdes_tx_data_dm(serdes_tx_data_dm),
|
||||
.serdes_tx_data_dv(serdes_tx_data_dv),
|
||||
.serdes_tx_data_valid(serdes_tx_data_valid),
|
||||
.serdes_tx_gbx_req_sync(serdes_tx_gbx_req_sync),
|
||||
.serdes_tx_gbx_req_stall(serdes_tx_gbx_req_stall),
|
||||
.serdes_tx_gbx_sync(serdes_tx_gbx_sync),
|
||||
.serdes_rx_data(serdes_rx_data),
|
||||
.serdes_rx_data_k(serdes_rx_data_k),
|
||||
.serdes_rx_data_valid(serdes_rx_data_valid)
|
||||
);
|
||||
|
||||
end else if (!CFG_LOW_LATENCY) begin : gt
|
||||
|
||||
taxi_eth_phy_1g_basex_us_gt #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
|
||||
.HAS_COMMON(HAS_COMMON),
|
||||
|
||||
// GT type
|
||||
.GT_TYPE(GT_TYPE),
|
||||
|
||||
// PLL parameters
|
||||
.QPLL0_PD(QPLL0_PD),
|
||||
.QPLL1_PD(QPLL1_PD),
|
||||
.QPLL0_EXT_CTRL(QPLL0_EXT_CTRL),
|
||||
.QPLL1_EXT_CTRL(QPLL1_EXT_CTRL),
|
||||
|
||||
// GT parameters
|
||||
.GT_TX_PD(GT_TX_PD),
|
||||
.GT_TX_QPLL_SEL(GT_TX_QPLL_SEL),
|
||||
.GT_TX_POLARITY(GT_TX_POLARITY),
|
||||
.GT_TX_ELECIDLE(GT_TX_ELECIDLE),
|
||||
.GT_TX_INHIBIT(GT_TX_INHIBIT),
|
||||
.GT_TX_DIFFCTRL(GT_TX_DIFFCTRL),
|
||||
.GT_TX_MAINCURSOR(GT_TX_MAINCURSOR),
|
||||
.GT_TX_POSTCURSOR(GT_TX_POSTCURSOR),
|
||||
.GT_TX_PRECURSOR(GT_TX_PRECURSOR),
|
||||
.GT_RX_PD(GT_RX_PD),
|
||||
.GT_RX_QPLL_SEL(GT_RX_QPLL_SEL),
|
||||
.GT_RX_LPM_EN(GT_RX_LPM_EN),
|
||||
.GT_RX_POLARITY(GT_RX_POLARITY),
|
||||
|
||||
// MAC/PHY parameters
|
||||
.DATA_W(DATA_W),
|
||||
.CTRL_W(CTRL_W)
|
||||
)
|
||||
gt_inst (
|
||||
.xcvr_ctrl_clk(xcvr_ctrl_clk),
|
||||
.xcvr_ctrl_rst(xcvr_ctrl_rst),
|
||||
|
||||
/*
|
||||
* Transceiver control
|
||||
*/
|
||||
.s_apb_ctrl(s_apb_ctrl),
|
||||
|
||||
/*
|
||||
* Common
|
||||
*/
|
||||
.xcvr_gtpowergood_out(xcvr_gtpowergood_out),
|
||||
|
||||
/*
|
||||
* PLL out
|
||||
*/
|
||||
.xcvr_gtrefclk00_in(xcvr_gtrefclk00_in),
|
||||
.xcvr_qpll0pd_in(xcvr_qpll0pd_in),
|
||||
.xcvr_qpll0reset_in(xcvr_qpll0reset_in),
|
||||
.xcvr_qpll0pcierate_in(xcvr_qpll0pcierate_in),
|
||||
.xcvr_qpll0lock_out(xcvr_qpll0lock_out),
|
||||
.xcvr_qpll0clk_out(xcvr_qpll0clk_out),
|
||||
.xcvr_qpll0refclk_out(xcvr_qpll0refclk_out),
|
||||
.xcvr_gtrefclk01_in(xcvr_gtrefclk01_in),
|
||||
.xcvr_qpll1pd_in(xcvr_qpll1pd_in),
|
||||
.xcvr_qpll1reset_in(xcvr_qpll1reset_in),
|
||||
.xcvr_qpll1pcierate_in(xcvr_qpll1pcierate_in),
|
||||
.xcvr_qpll1lock_out(xcvr_qpll1lock_out),
|
||||
.xcvr_qpll1clk_out(xcvr_qpll1clk_out),
|
||||
.xcvr_qpll1refclk_out(xcvr_qpll1refclk_out),
|
||||
|
||||
/*
|
||||
* PLL in
|
||||
*/
|
||||
.xcvr_qpll0lock_in(xcvr_qpll0lock_in),
|
||||
.xcvr_qpll0clk_in(xcvr_qpll0clk_in),
|
||||
.xcvr_qpll0refclk_in(xcvr_qpll0refclk_in),
|
||||
.xcvr_qpll1lock_in(xcvr_qpll1lock_in),
|
||||
.xcvr_qpll1clk_in(xcvr_qpll1clk_in),
|
||||
.xcvr_qpll1refclk_in(xcvr_qpll1refclk_in),
|
||||
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp(xcvr_txp),
|
||||
.xcvr_txn(xcvr_txn),
|
||||
.xcvr_rxp(xcvr_rxp),
|
||||
.xcvr_rxn(xcvr_rxn),
|
||||
|
||||
/*
|
||||
* GT user clocks
|
||||
*/
|
||||
.rx_clk(rx_clk),
|
||||
.rx_rst_in(rx_rst_in || rx_reset_req),
|
||||
.rx_rst_out(rx_rst_out),
|
||||
.tx_clk(tx_clk),
|
||||
.tx_rst_in(tx_rst_in),
|
||||
.tx_rst_out(tx_rst_out),
|
||||
|
||||
/*
|
||||
* Serdes interface
|
||||
*/
|
||||
.serdes_tx_data(serdes_tx_data),
|
||||
.serdes_tx_data_k(serdes_tx_data_k),
|
||||
.serdes_tx_data_dm(serdes_tx_data_dm),
|
||||
.serdes_tx_data_dv(serdes_tx_data_dv),
|
||||
.serdes_tx_data_valid(serdes_tx_data_valid),
|
||||
.serdes_tx_gbx_req_sync(serdes_tx_gbx_req_sync),
|
||||
.serdes_tx_gbx_req_stall(serdes_tx_gbx_req_stall),
|
||||
.serdes_tx_gbx_sync(serdes_tx_gbx_sync),
|
||||
.serdes_rx_data(serdes_rx_data),
|
||||
.serdes_rx_data_k(serdes_rx_data_k),
|
||||
.serdes_rx_data_valid(serdes_rx_data_valid)
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
$fatal(0, "Error: invalid configuration (%m)");
|
||||
|
||||
end
|
||||
|
||||
if (COMBINED_MAC_PCS) begin : mac
|
||||
|
||||
taxi_eth_mac_phy_1g_basex #(
|
||||
.DATA_W(DATA_W),
|
||||
.CTRL_W(CTRL_W),
|
||||
.TX_GBX_IF_EN(GBX_EN),
|
||||
.RX_GBX_IF_EN(GBX_EN),
|
||||
.DIC_EN(DIC_EN),
|
||||
.PTP_TS_EN(PTP_TS_EN),
|
||||
.PTP_TD_EN(PTP_TD_EN),
|
||||
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
|
||||
.PTP_TS_W(PTP_TS_W),
|
||||
.PTP_TD_SDI_PIPELINE(PTP_TD_SDI_PIPELINE),
|
||||
.BIT_REVERSE(1'b0),
|
||||
.ENC_8B10B_EN(1'b0),
|
||||
.DEC_8B10B_EN(1'b0),
|
||||
.PRBS31_EN(PRBS31_EN),
|
||||
.PFC_EN(PFC_EN),
|
||||
.PAUSE_EN(PAUSE_EN),
|
||||
.STAT_EN(STAT_EN),
|
||||
.STAT_TX_LEVEL(STAT_TX_LEVEL),
|
||||
.STAT_RX_LEVEL(STAT_RX_LEVEL),
|
||||
.STAT_ID_BASE(STAT_ID_BASE),
|
||||
.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD),
|
||||
.STAT_STR_EN(STAT_STR_EN),
|
||||
.STAT_PREFIX_STR(STAT_PREFIX_STR)
|
||||
)
|
||||
mac_phy_inst (
|
||||
.tx_clk(tx_clk),
|
||||
.tx_rst(tx_rst_out),
|
||||
.rx_clk(rx_clk),
|
||||
.rx_rst(rx_rst_out),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(s_axis_tx),
|
||||
.m_axis_tx_cpl(m_axis_tx_cpl),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(m_axis_rx),
|
||||
|
||||
/*
|
||||
* Serdes interface
|
||||
*/
|
||||
.serdes_tx_data(serdes_tx_data),
|
||||
.serdes_tx_data_k(serdes_tx_data_k),
|
||||
.serdes_tx_data_dm(serdes_tx_data_dm),
|
||||
.serdes_tx_data_dv(serdes_tx_data_dv),
|
||||
.serdes_tx_data_valid(serdes_tx_data_valid),
|
||||
.serdes_tx_gbx_req_sync(serdes_tx_gbx_req_sync),
|
||||
.serdes_tx_gbx_req_stall(serdes_tx_gbx_req_stall),
|
||||
.serdes_tx_gbx_sync(serdes_tx_gbx_sync),
|
||||
.serdes_rx_data(serdes_rx_data),
|
||||
.serdes_rx_data_k(serdes_rx_data_k),
|
||||
.serdes_rx_data_valid(serdes_rx_data_valid),
|
||||
.serdes_rx_reset_req(rx_reset_req),
|
||||
|
||||
/*
|
||||
* PTP
|
||||
*/
|
||||
.ptp_clk(ptp_clk),
|
||||
.ptp_rst(ptp_rst),
|
||||
.ptp_sample_clk(ptp_sample_clk),
|
||||
.ptp_td_sdi(ptp_td_sdi),
|
||||
.tx_ptp_ts_in(tx_ptp_ts_in),
|
||||
.tx_ptp_ts_out(tx_ptp_ts_out),
|
||||
.tx_ptp_ts_step_out(tx_ptp_ts_step_out),
|
||||
.tx_ptp_locked(tx_ptp_locked),
|
||||
.rx_ptp_ts_in(rx_ptp_ts_in),
|
||||
.rx_ptp_ts_out(rx_ptp_ts_out),
|
||||
.rx_ptp_ts_step_out(rx_ptp_ts_step_out),
|
||||
.rx_ptp_locked(rx_ptp_locked),
|
||||
|
||||
/*
|
||||
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
|
||||
*/
|
||||
.tx_lfc_req(tx_lfc_req),
|
||||
.tx_lfc_resend(tx_lfc_resend),
|
||||
.rx_lfc_en(rx_lfc_en),
|
||||
.rx_lfc_req(rx_lfc_req),
|
||||
.rx_lfc_ack(rx_lfc_ack),
|
||||
|
||||
/*
|
||||
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
|
||||
*/
|
||||
.tx_pfc_req(tx_pfc_req),
|
||||
.tx_pfc_resend(tx_pfc_resend),
|
||||
.rx_pfc_en(rx_pfc_en),
|
||||
.rx_pfc_req(rx_pfc_req),
|
||||
.rx_pfc_ack(rx_pfc_ack),
|
||||
|
||||
/*
|
||||
* Pause interface
|
||||
*/
|
||||
.tx_lfc_pause_en(tx_lfc_pause_en),
|
||||
.tx_pause_req(tx_pause_req),
|
||||
.tx_pause_ack(tx_pause_ack),
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
.stat_clk(stat_clk),
|
||||
.stat_rst(stat_rst),
|
||||
.m_axis_stat(m_axis_stat),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_start_packet(tx_start_packet),
|
||||
.stat_tx_byte(stat_tx_byte),
|
||||
.stat_tx_pkt_len(stat_tx_pkt_len),
|
||||
.stat_tx_pkt_ucast(stat_tx_pkt_ucast),
|
||||
.stat_tx_pkt_mcast(stat_tx_pkt_mcast),
|
||||
.stat_tx_pkt_bcast(stat_tx_pkt_bcast),
|
||||
.stat_tx_pkt_vlan(stat_tx_pkt_vlan),
|
||||
.stat_tx_pkt_good(stat_tx_pkt_good),
|
||||
.stat_tx_pkt_bad(stat_tx_pkt_bad),
|
||||
.stat_tx_pad_frame(stat_tx_pad_frame),
|
||||
.stat_tx_err_oversize(stat_tx_err_oversize),
|
||||
.stat_tx_err_user(stat_tx_err_user),
|
||||
.stat_tx_err_underflow(stat_tx_err_underflow),
|
||||
.rx_start_packet(rx_start_packet),
|
||||
.rx_error_count(rx_error_count),
|
||||
.rx_block_lock(rx_block_lock),
|
||||
.rx_high_ber(rx_high_ber),
|
||||
.rx_status(rx_status),
|
||||
.stat_rx_byte(stat_rx_byte),
|
||||
.stat_rx_pkt_len(stat_rx_pkt_len),
|
||||
.stat_rx_pkt_fragment(stat_rx_pkt_fragment),
|
||||
.stat_rx_pkt_jabber(stat_rx_pkt_jabber),
|
||||
.stat_rx_pkt_ucast(stat_rx_pkt_ucast),
|
||||
.stat_rx_pkt_mcast(stat_rx_pkt_mcast),
|
||||
.stat_rx_pkt_bcast(stat_rx_pkt_bcast),
|
||||
.stat_rx_pkt_vlan(stat_rx_pkt_vlan),
|
||||
.stat_rx_pkt_good(stat_rx_pkt_good),
|
||||
.stat_rx_pkt_bad(stat_rx_pkt_bad),
|
||||
.stat_rx_err_oversize(stat_rx_err_oversize),
|
||||
.stat_rx_err_bad_fcs(stat_rx_err_bad_fcs),
|
||||
.stat_rx_err_bad_block(stat_rx_err_bad_block),
|
||||
.stat_rx_err_framing(stat_rx_err_framing),
|
||||
.stat_rx_err_preamble(stat_rx_err_preamble),
|
||||
.stat_rx_fifo_drop(stat_rx_fifo_drop),
|
||||
.stat_tx_mcf(stat_tx_mcf),
|
||||
.stat_rx_mcf(stat_rx_mcf),
|
||||
.stat_tx_lfc_pkt(stat_tx_lfc_pkt),
|
||||
.stat_tx_lfc_xon(stat_tx_lfc_xon),
|
||||
.stat_tx_lfc_xoff(stat_tx_lfc_xoff),
|
||||
.stat_tx_lfc_paused(stat_tx_lfc_paused),
|
||||
.stat_tx_pfc_pkt(stat_tx_pfc_pkt),
|
||||
.stat_tx_pfc_xon(stat_tx_pfc_xon),
|
||||
.stat_tx_pfc_xoff(stat_tx_pfc_xoff),
|
||||
.stat_tx_pfc_paused(stat_tx_pfc_paused),
|
||||
.stat_rx_lfc_pkt(stat_rx_lfc_pkt),
|
||||
.stat_rx_lfc_xon(stat_rx_lfc_xon),
|
||||
.stat_rx_lfc_xoff(stat_rx_lfc_xoff),
|
||||
.stat_rx_lfc_paused(stat_rx_lfc_paused),
|
||||
.stat_rx_pfc_pkt(stat_rx_pfc_pkt),
|
||||
.stat_rx_pfc_xon(stat_rx_pfc_xon),
|
||||
.stat_rx_pfc_xoff(stat_rx_pfc_xoff),
|
||||
.stat_rx_pfc_paused(stat_rx_pfc_paused),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_tx_pad_en(cfg_tx_pad_en),
|
||||
.cfg_tx_min_pkt_len(cfg_tx_min_pkt_len),
|
||||
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
|
||||
.cfg_tx_ifg(cfg_tx_ifg),
|
||||
.cfg_tx_enable(cfg_tx_enable),
|
||||
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
|
||||
.cfg_rx_enable(cfg_rx_enable),
|
||||
.cfg_tx_prbs31_enable(cfg_tx_prbs31_enable),
|
||||
.cfg_rx_prbs31_enable(cfg_rx_prbs31_enable),
|
||||
.cfg_mcf_rx_eth_dst_mcast(cfg_mcf_rx_eth_dst_mcast),
|
||||
.cfg_mcf_rx_check_eth_dst_mcast(cfg_mcf_rx_check_eth_dst_mcast),
|
||||
.cfg_mcf_rx_eth_dst_ucast(cfg_mcf_rx_eth_dst_ucast),
|
||||
.cfg_mcf_rx_check_eth_dst_ucast(cfg_mcf_rx_check_eth_dst_ucast),
|
||||
.cfg_mcf_rx_eth_src(cfg_mcf_rx_eth_src),
|
||||
.cfg_mcf_rx_check_eth_src(cfg_mcf_rx_check_eth_src),
|
||||
.cfg_mcf_rx_eth_type(cfg_mcf_rx_eth_type),
|
||||
.cfg_mcf_rx_opcode_lfc(cfg_mcf_rx_opcode_lfc),
|
||||
.cfg_mcf_rx_check_opcode_lfc(cfg_mcf_rx_check_opcode_lfc),
|
||||
.cfg_mcf_rx_opcode_pfc(cfg_mcf_rx_opcode_pfc),
|
||||
.cfg_mcf_rx_check_opcode_pfc(cfg_mcf_rx_check_opcode_pfc),
|
||||
.cfg_mcf_rx_forward(cfg_mcf_rx_forward),
|
||||
.cfg_mcf_rx_enable(cfg_mcf_rx_enable),
|
||||
.cfg_tx_lfc_eth_dst(cfg_tx_lfc_eth_dst),
|
||||
.cfg_tx_lfc_eth_src(cfg_tx_lfc_eth_src),
|
||||
.cfg_tx_lfc_eth_type(cfg_tx_lfc_eth_type),
|
||||
.cfg_tx_lfc_opcode(cfg_tx_lfc_opcode),
|
||||
.cfg_tx_lfc_en(cfg_tx_lfc_en),
|
||||
.cfg_tx_lfc_quanta(cfg_tx_lfc_quanta),
|
||||
.cfg_tx_lfc_refresh(cfg_tx_lfc_refresh),
|
||||
.cfg_tx_pfc_eth_dst(cfg_tx_pfc_eth_dst),
|
||||
.cfg_tx_pfc_eth_src(cfg_tx_pfc_eth_src),
|
||||
.cfg_tx_pfc_eth_type(cfg_tx_pfc_eth_type),
|
||||
.cfg_tx_pfc_opcode(cfg_tx_pfc_opcode),
|
||||
.cfg_tx_pfc_en(cfg_tx_pfc_en),
|
||||
.cfg_tx_pfc_quanta(cfg_tx_pfc_quanta),
|
||||
.cfg_tx_pfc_refresh(cfg_tx_pfc_refresh),
|
||||
.cfg_rx_lfc_opcode(cfg_rx_lfc_opcode),
|
||||
.cfg_rx_lfc_en(cfg_rx_lfc_en),
|
||||
.cfg_rx_pfc_opcode(cfg_rx_pfc_opcode),
|
||||
.cfg_rx_pfc_en(cfg_rx_pfc_en)
|
||||
);
|
||||
|
||||
end else begin : mac
|
||||
|
||||
$fatal(0, "Error: configuration not currently supported (%m)");
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
8
src/eth/rtl/us/taxi_eth_phy_1g_basex_us_gt.f
Normal file
8
src/eth/rtl/us/taxi_eth_phy_1g_basex_us_gt.f
Normal file
@@ -0,0 +1,8 @@
|
||||
taxi_eth_phy_1g_basex_us_gt.sv
|
||||
taxi_eth_phy_25g_us_gt_apb.sv
|
||||
../../lib/taxi/src/sync/rtl/taxi_sync_reset.sv
|
||||
../../lib/taxi/src/sync/rtl/taxi_sync_signal.sv
|
||||
../../lib/taxi/src/hip/rtl/us/taxi_gt_qpll_reset.sv
|
||||
../../lib/taxi/src/hip/rtl/us/taxi_gt_rx_reset.sv
|
||||
../../lib/taxi/src/hip/rtl/us/taxi_gt_tx_reset.sv
|
||||
../../lib/taxi/src/apb/rtl/taxi_apb_if.sv
|
||||
1366
src/eth/rtl/us/taxi_eth_phy_1g_basex_us_gt.sv
Normal file
1366
src/eth/rtl/us/taxi_eth_phy_1g_basex_us_gt.sv
Normal file
File diff suppressed because it is too large
Load Diff
8
src/eth/rtl/us/taxi_eth_phy_1g_basex_us_gt_ll.f
Normal file
8
src/eth/rtl/us/taxi_eth_phy_1g_basex_us_gt_ll.f
Normal file
@@ -0,0 +1,8 @@
|
||||
taxi_eth_phy_1g_basex_us_gt_ll.sv
|
||||
taxi_eth_phy_25g_us_gt_apb.sv
|
||||
../../lib/taxi/src/sync/rtl/taxi_sync_reset.sv
|
||||
../../lib/taxi/src/sync/rtl/taxi_sync_signal.sv
|
||||
../../lib/taxi/src/hip/rtl/us/taxi_gt_qpll_reset.sv
|
||||
../../lib/taxi/src/hip/rtl/us/taxi_gt_rx_reset.sv
|
||||
../../lib/taxi/src/hip/rtl/us/taxi_gt_tx_reset.sv
|
||||
../../lib/taxi/src/apb/rtl/taxi_apb_if.sv
|
||||
1392
src/eth/rtl/us/taxi_eth_phy_1g_basex_us_gt_ll.sv
Normal file
1392
src/eth/rtl/us/taxi_eth_phy_1g_basex_us_gt_ll.sv
Normal file
File diff suppressed because it is too large
Load Diff
137
src/eth/rtl/us/taxi_eth_phy_1g_basex_us_gth_125.tcl
Normal file
137
src/eth/rtl/us/taxi_eth_phy_1g_basex_us_gth_125.tcl
Normal file
@@ -0,0 +1,137 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2026 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
set base_name {taxi_eth_phy_1g_basex_us_gth}
|
||||
|
||||
set preset {GTH-Gigabit_Ethernet}
|
||||
|
||||
set freerun_freq {62.5}
|
||||
set line_rate {1.25}
|
||||
set refclk_freq {125}
|
||||
set sec_line_rate {0}
|
||||
set sec_refclk_freq $refclk_freq
|
||||
set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
|
||||
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}]
|
||||
set user_data_width {16}
|
||||
set int_data_width {20}
|
||||
set rx_eq_mode {AUTO}
|
||||
set extra_ports [list]
|
||||
set extra_pll_ports [list]
|
||||
# DRP connections
|
||||
lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out
|
||||
lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out
|
||||
# PLL reset and power down
|
||||
lappend extra_pll_ports qpll0reset_in qpll1reset_in
|
||||
lappend extra_pll_ports qpll0pd_in qpll1pd_in
|
||||
# PLL clocking
|
||||
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
|
||||
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
|
||||
# PCIe
|
||||
if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} {
|
||||
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
|
||||
} else {
|
||||
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
|
||||
}
|
||||
# channel reset
|
||||
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txprogdivreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out
|
||||
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxprogdivreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out
|
||||
# channel power down
|
||||
lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
|
||||
# channel clock selection
|
||||
lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in
|
||||
# channel polarity
|
||||
lappend extra_ports txpolarity_in rxpolarity_in
|
||||
# channel TX driver
|
||||
lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in
|
||||
# channel CDR
|
||||
lappend extra_ports rxcdrlock_out rxcdrhold_in rxcdrovrden_in
|
||||
# channel EQ
|
||||
lappend extra_ports rxlpmen_in
|
||||
|
||||
set config [dict create]
|
||||
|
||||
dict set config TX_LINE_RATE $line_rate
|
||||
dict set config TX_PLL_TYPE {QPLL0}
|
||||
dict set config TX_REFCLK_FREQUENCY $refclk_freq
|
||||
dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn
|
||||
dict set config TX_USER_DATA_WIDTH $user_data_width
|
||||
dict set config TX_INT_DATA_WIDTH $int_data_width
|
||||
dict set config RX_LINE_RATE $line_rate
|
||||
dict set config RX_PLL_TYPE {QPLL0}
|
||||
dict set config RX_REFCLK_FREQUENCY $refclk_freq
|
||||
dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn
|
||||
dict set config RX_USER_DATA_WIDTH $user_data_width
|
||||
dict set config RX_INT_DATA_WIDTH $int_data_width
|
||||
dict set config RX_EQ_MODE $rx_eq_mode
|
||||
if {$sec_line_rate != 0} {
|
||||
dict set config SECONDARY_QPLL_ENABLE true
|
||||
dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
|
||||
dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
|
||||
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq
|
||||
} else {
|
||||
dict set config SECONDARY_QPLL_ENABLE false
|
||||
}
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
|
||||
dict set config LOCATE_TX_USER_CLOCKING {CORE}
|
||||
dict set config LOCATE_RX_USER_CLOCKING {CORE}
|
||||
dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE}
|
||||
dict set config FREERUN_FREQUENCY $freerun_freq
|
||||
dict set config DISABLE_LOC_XDC {1}
|
||||
|
||||
proc create_gtwizard_ip {name preset config} {
|
||||
create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name
|
||||
set ip [get_ips $name]
|
||||
set_property CONFIG.preset $preset $ip
|
||||
set config_list {}
|
||||
dict for {name value} $config {
|
||||
lappend config_list "CONFIG.${name}" $value
|
||||
}
|
||||
set_property -dict $config_list $ip
|
||||
}
|
||||
|
||||
# normal latency (async gearbox)
|
||||
dict set config TX_DATA_ENCODING {8B10B}
|
||||
dict set config TX_BUFFER_MODE {1}
|
||||
dict set config TX_OUTCLK_SOURCE {TXOUTCLKPMA}
|
||||
dict set config RX_DATA_DECODING {8B10B}
|
||||
dict set config RX_BUFFER_MODE {1}
|
||||
dict set config RX_OUTCLK_SOURCE {RXOUTCLKPMA}
|
||||
|
||||
# variant with channel and common
|
||||
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
|
||||
create_gtwizard_ip "${base_name}_full" $preset $config
|
||||
|
||||
# variant with channel only
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
|
||||
|
||||
create_gtwizard_ip "${base_name}_ch" $preset $config
|
||||
|
||||
# low latency (async gearbox with buffer bypass)
|
||||
dict set config TX_DATA_ENCODING {8B10B}
|
||||
dict set config TX_BUFFER_MODE {0}
|
||||
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
|
||||
dict set config RX_DATA_DECODING {8B10B}
|
||||
dict set config RX_BUFFER_MODE {0}
|
||||
dict set config RX_OUTCLK_SOURCE {RXOUTCLKPMA}
|
||||
|
||||
# variant with channel and common
|
||||
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
|
||||
create_gtwizard_ip "${base_name}_ll_full" $preset $config
|
||||
|
||||
# variant with channel only
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
|
||||
|
||||
create_gtwizard_ip "${base_name}_ll_ch" $preset $config
|
||||
137
src/eth/rtl/us/taxi_eth_phy_1g_basex_us_gth_156.tcl
Normal file
137
src/eth/rtl/us/taxi_eth_phy_1g_basex_us_gth_156.tcl
Normal file
@@ -0,0 +1,137 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2026 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
set base_name {taxi_eth_phy_1g_basex_us_gth}
|
||||
|
||||
set preset {GTH-Gigabit_Ethernet}
|
||||
|
||||
set freerun_freq {62.5}
|
||||
set line_rate {1.25}
|
||||
set refclk_freq {156.25}
|
||||
set sec_line_rate {0}
|
||||
set sec_refclk_freq $refclk_freq
|
||||
set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
|
||||
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}]
|
||||
set user_data_width {16}
|
||||
set int_data_width {20}
|
||||
set rx_eq_mode {AUTO}
|
||||
set extra_ports [list]
|
||||
set extra_pll_ports [list]
|
||||
# DRP connections
|
||||
lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out
|
||||
lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out
|
||||
# PLL reset and power down
|
||||
lappend extra_pll_ports qpll0reset_in qpll1reset_in
|
||||
lappend extra_pll_ports qpll0pd_in qpll1pd_in
|
||||
# PLL clocking
|
||||
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
|
||||
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
|
||||
# PCIe
|
||||
if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} {
|
||||
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
|
||||
} else {
|
||||
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
|
||||
}
|
||||
# channel reset
|
||||
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txprogdivreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out
|
||||
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxprogdivreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out
|
||||
# channel power down
|
||||
lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
|
||||
# channel clock selection
|
||||
lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in
|
||||
# channel polarity
|
||||
lappend extra_ports txpolarity_in rxpolarity_in
|
||||
# channel TX driver
|
||||
lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in
|
||||
# channel CDR
|
||||
lappend extra_ports rxcdrlock_out rxcdrhold_in rxcdrovrden_in
|
||||
# channel EQ
|
||||
lappend extra_ports rxlpmen_in
|
||||
|
||||
set config [dict create]
|
||||
|
||||
dict set config TX_LINE_RATE $line_rate
|
||||
dict set config TX_PLL_TYPE {QPLL0}
|
||||
dict set config TX_REFCLK_FREQUENCY $refclk_freq
|
||||
dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn
|
||||
dict set config TX_USER_DATA_WIDTH $user_data_width
|
||||
dict set config TX_INT_DATA_WIDTH $int_data_width
|
||||
dict set config RX_LINE_RATE $line_rate
|
||||
dict set config RX_PLL_TYPE {QPLL0}
|
||||
dict set config RX_REFCLK_FREQUENCY $refclk_freq
|
||||
dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn
|
||||
dict set config RX_USER_DATA_WIDTH $user_data_width
|
||||
dict set config RX_INT_DATA_WIDTH $int_data_width
|
||||
dict set config RX_EQ_MODE $rx_eq_mode
|
||||
if {$sec_line_rate != 0} {
|
||||
dict set config SECONDARY_QPLL_ENABLE true
|
||||
dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
|
||||
dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
|
||||
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq
|
||||
} else {
|
||||
dict set config SECONDARY_QPLL_ENABLE false
|
||||
}
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
|
||||
dict set config LOCATE_TX_USER_CLOCKING {CORE}
|
||||
dict set config LOCATE_RX_USER_CLOCKING {CORE}
|
||||
dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE}
|
||||
dict set config FREERUN_FREQUENCY $freerun_freq
|
||||
dict set config DISABLE_LOC_XDC {1}
|
||||
|
||||
proc create_gtwizard_ip {name preset config} {
|
||||
create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name
|
||||
set ip [get_ips $name]
|
||||
set_property CONFIG.preset $preset $ip
|
||||
set config_list {}
|
||||
dict for {name value} $config {
|
||||
lappend config_list "CONFIG.${name}" $value
|
||||
}
|
||||
set_property -dict $config_list $ip
|
||||
}
|
||||
|
||||
# normal latency (async gearbox)
|
||||
dict set config TX_DATA_ENCODING {8B10B}
|
||||
dict set config TX_BUFFER_MODE {1}
|
||||
dict set config TX_OUTCLK_SOURCE {TXOUTCLKPMA}
|
||||
dict set config RX_DATA_DECODING {8B10B}
|
||||
dict set config RX_BUFFER_MODE {1}
|
||||
dict set config RX_OUTCLK_SOURCE {RXOUTCLKPMA}
|
||||
|
||||
# variant with channel and common
|
||||
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
|
||||
create_gtwizard_ip "${base_name}_full" $preset $config
|
||||
|
||||
# variant with channel only
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
|
||||
|
||||
create_gtwizard_ip "${base_name}_ch" $preset $config
|
||||
|
||||
# low latency (async gearbox with buffer bypass)
|
||||
dict set config TX_DATA_ENCODING {8B10B}
|
||||
dict set config TX_BUFFER_MODE {0}
|
||||
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
|
||||
dict set config RX_DATA_DECODING {8B10B}
|
||||
dict set config RX_BUFFER_MODE {0}
|
||||
dict set config RX_OUTCLK_SOURCE {RXOUTCLKPMA}
|
||||
|
||||
# variant with channel and common
|
||||
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
|
||||
create_gtwizard_ip "${base_name}_ll_full" $preset $config
|
||||
|
||||
# variant with channel only
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
|
||||
|
||||
create_gtwizard_ip "${base_name}_ll_ch" $preset $config
|
||||
137
src/eth/rtl/us/taxi_eth_phy_1g_basex_us_gty_125.tcl
Normal file
137
src/eth/rtl/us/taxi_eth_phy_1g_basex_us_gty_125.tcl
Normal file
@@ -0,0 +1,137 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2026 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
set base_name {taxi_eth_phy_1g_basex_us_gty}
|
||||
|
||||
set preset {GTY-Gigabit_Ethernet}
|
||||
|
||||
set freerun_freq {62.5}
|
||||
set line_rate {1.25}
|
||||
set refclk_freq {125}
|
||||
set sec_line_rate {0}
|
||||
set sec_refclk_freq $refclk_freq
|
||||
set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
|
||||
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}]
|
||||
set user_data_width {16}
|
||||
set int_data_width {20}
|
||||
set rx_eq_mode {AUTO}
|
||||
set extra_ports [list]
|
||||
set extra_pll_ports [list]
|
||||
# DRP connections
|
||||
lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out
|
||||
lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out
|
||||
# PLL reset and power down
|
||||
lappend extra_pll_ports qpll0reset_in qpll1reset_in
|
||||
lappend extra_pll_ports qpll0pd_in qpll1pd_in
|
||||
# PLL clocking
|
||||
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
|
||||
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
|
||||
# PCIe
|
||||
if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} {
|
||||
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
|
||||
} else {
|
||||
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
|
||||
}
|
||||
# channel reset
|
||||
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txprogdivreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out
|
||||
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxprogdivreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out
|
||||
# channel power down
|
||||
lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
|
||||
# channel clock selection
|
||||
lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in
|
||||
# channel polarity
|
||||
lappend extra_ports txpolarity_in rxpolarity_in
|
||||
# channel TX driver
|
||||
lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in
|
||||
# channel CDR
|
||||
lappend extra_ports rxcdrlock_out rxcdrhold_in rxcdrovrden_in
|
||||
# channel EQ
|
||||
lappend extra_ports rxlpmen_in
|
||||
|
||||
set config [dict create]
|
||||
|
||||
dict set config TX_LINE_RATE $line_rate
|
||||
dict set config TX_PLL_TYPE {QPLL0}
|
||||
dict set config TX_REFCLK_FREQUENCY $refclk_freq
|
||||
dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn
|
||||
dict set config TX_USER_DATA_WIDTH $user_data_width
|
||||
dict set config TX_INT_DATA_WIDTH $int_data_width
|
||||
dict set config RX_LINE_RATE $line_rate
|
||||
dict set config RX_PLL_TYPE {QPLL0}
|
||||
dict set config RX_REFCLK_FREQUENCY $refclk_freq
|
||||
dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn
|
||||
dict set config RX_USER_DATA_WIDTH $user_data_width
|
||||
dict set config RX_INT_DATA_WIDTH $int_data_width
|
||||
dict set config RX_EQ_MODE $rx_eq_mode
|
||||
if {$sec_line_rate != 0} {
|
||||
dict set config SECONDARY_QPLL_ENABLE true
|
||||
dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
|
||||
dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
|
||||
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq
|
||||
} else {
|
||||
dict set config SECONDARY_QPLL_ENABLE false
|
||||
}
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
|
||||
dict set config LOCATE_TX_USER_CLOCKING {CORE}
|
||||
dict set config LOCATE_RX_USER_CLOCKING {CORE}
|
||||
dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE}
|
||||
dict set config FREERUN_FREQUENCY $freerun_freq
|
||||
dict set config DISABLE_LOC_XDC {1}
|
||||
|
||||
proc create_gtwizard_ip {name preset config} {
|
||||
create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name
|
||||
set ip [get_ips $name]
|
||||
set_property CONFIG.preset $preset $ip
|
||||
set config_list {}
|
||||
dict for {name value} $config {
|
||||
lappend config_list "CONFIG.${name}" $value
|
||||
}
|
||||
set_property -dict $config_list $ip
|
||||
}
|
||||
|
||||
# normal latency (async gearbox)
|
||||
dict set config TX_DATA_ENCODING {8B10B}
|
||||
dict set config TX_BUFFER_MODE {1}
|
||||
dict set config TX_OUTCLK_SOURCE {TXOUTCLKPMA}
|
||||
dict set config RX_DATA_DECODING {8B10B}
|
||||
dict set config RX_BUFFER_MODE {1}
|
||||
dict set config RX_OUTCLK_SOURCE {RXOUTCLKPMA}
|
||||
|
||||
# variant with channel and common
|
||||
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
|
||||
create_gtwizard_ip "${base_name}_full" $preset $config
|
||||
|
||||
# variant with channel only
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
|
||||
|
||||
create_gtwizard_ip "${base_name}_ch" $preset $config
|
||||
|
||||
# low latency (async gearbox with buffer bypass)
|
||||
dict set config TX_DATA_ENCODING {8B10B}
|
||||
dict set config TX_BUFFER_MODE {0}
|
||||
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
|
||||
dict set config RX_DATA_DECODING {8B10B}
|
||||
dict set config RX_BUFFER_MODE {0}
|
||||
dict set config RX_OUTCLK_SOURCE {RXOUTCLKPMA}
|
||||
|
||||
# variant with channel and common
|
||||
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
|
||||
create_gtwizard_ip "${base_name}_ll_full" $preset $config
|
||||
|
||||
# variant with channel only
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
|
||||
|
||||
create_gtwizard_ip "${base_name}_ll_ch" $preset $config
|
||||
137
src/eth/rtl/us/taxi_eth_phy_1g_basex_us_gty_156.tcl
Normal file
137
src/eth/rtl/us/taxi_eth_phy_1g_basex_us_gty_156.tcl
Normal file
@@ -0,0 +1,137 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2026 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
set base_name {taxi_eth_phy_1g_basex_us_gty}
|
||||
|
||||
set preset {GTY-Gigabit_Ethernet}
|
||||
|
||||
set freerun_freq {62.5}
|
||||
set line_rate {1.25}
|
||||
set refclk_freq {156.25}
|
||||
set sec_line_rate {0}
|
||||
set sec_refclk_freq $refclk_freq
|
||||
set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
|
||||
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}]
|
||||
set user_data_width {16}
|
||||
set int_data_width {20}
|
||||
set rx_eq_mode {AUTO}
|
||||
set extra_ports [list]
|
||||
set extra_pll_ports [list]
|
||||
# DRP connections
|
||||
lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out
|
||||
lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out
|
||||
# PLL reset and power down
|
||||
lappend extra_pll_ports qpll0reset_in qpll1reset_in
|
||||
lappend extra_pll_ports qpll0pd_in qpll1pd_in
|
||||
# PLL clocking
|
||||
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
|
||||
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
|
||||
# PCIe
|
||||
if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} {
|
||||
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
|
||||
} else {
|
||||
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
|
||||
}
|
||||
# channel reset
|
||||
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txprogdivreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out
|
||||
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxprogdivreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out
|
||||
# channel power down
|
||||
lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
|
||||
# channel clock selection
|
||||
lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in
|
||||
# channel polarity
|
||||
lappend extra_ports txpolarity_in rxpolarity_in
|
||||
# channel TX driver
|
||||
lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in
|
||||
# channel CDR
|
||||
lappend extra_ports rxcdrlock_out rxcdrhold_in rxcdrovrden_in
|
||||
# channel EQ
|
||||
lappend extra_ports rxlpmen_in
|
||||
|
||||
set config [dict create]
|
||||
|
||||
dict set config TX_LINE_RATE $line_rate
|
||||
dict set config TX_PLL_TYPE {QPLL0}
|
||||
dict set config TX_REFCLK_FREQUENCY $refclk_freq
|
||||
dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn
|
||||
dict set config TX_USER_DATA_WIDTH $user_data_width
|
||||
dict set config TX_INT_DATA_WIDTH $int_data_width
|
||||
dict set config RX_LINE_RATE $line_rate
|
||||
dict set config RX_PLL_TYPE {QPLL0}
|
||||
dict set config RX_REFCLK_FREQUENCY $refclk_freq
|
||||
dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn
|
||||
dict set config RX_USER_DATA_WIDTH $user_data_width
|
||||
dict set config RX_INT_DATA_WIDTH $int_data_width
|
||||
dict set config RX_EQ_MODE $rx_eq_mode
|
||||
if {$sec_line_rate != 0} {
|
||||
dict set config SECONDARY_QPLL_ENABLE true
|
||||
dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
|
||||
dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
|
||||
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq
|
||||
} else {
|
||||
dict set config SECONDARY_QPLL_ENABLE false
|
||||
}
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
|
||||
dict set config LOCATE_TX_USER_CLOCKING {CORE}
|
||||
dict set config LOCATE_RX_USER_CLOCKING {CORE}
|
||||
dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE}
|
||||
dict set config FREERUN_FREQUENCY $freerun_freq
|
||||
dict set config DISABLE_LOC_XDC {1}
|
||||
|
||||
proc create_gtwizard_ip {name preset config} {
|
||||
create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name
|
||||
set ip [get_ips $name]
|
||||
set_property CONFIG.preset $preset $ip
|
||||
set config_list {}
|
||||
dict for {name value} $config {
|
||||
lappend config_list "CONFIG.${name}" $value
|
||||
}
|
||||
set_property -dict $config_list $ip
|
||||
}
|
||||
|
||||
# normal latency (async gearbox)
|
||||
dict set config TX_DATA_ENCODING {8B10B}
|
||||
dict set config TX_BUFFER_MODE {1}
|
||||
dict set config TX_OUTCLK_SOURCE {TXOUTCLKPMA}
|
||||
dict set config RX_DATA_DECODING {8B10B}
|
||||
dict set config RX_BUFFER_MODE {1}
|
||||
dict set config RX_OUTCLK_SOURCE {RXOUTCLKPMA}
|
||||
|
||||
# variant with channel and common
|
||||
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
|
||||
create_gtwizard_ip "${base_name}_full" $preset $config
|
||||
|
||||
# variant with channel only
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
|
||||
|
||||
create_gtwizard_ip "${base_name}_ch" $preset $config
|
||||
|
||||
# low latency (async gearbox with buffer bypass)
|
||||
dict set config TX_DATA_ENCODING {8B10B}
|
||||
dict set config TX_BUFFER_MODE {0}
|
||||
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
|
||||
dict set config RX_DATA_DECODING {8B10B}
|
||||
dict set config RX_BUFFER_MODE {0}
|
||||
dict set config RX_OUTCLK_SOURCE {RXOUTCLKPMA}
|
||||
|
||||
# variant with channel and common
|
||||
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
|
||||
create_gtwizard_ip "${base_name}_ll_full" $preset $config
|
||||
|
||||
# variant with channel only
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
|
||||
|
||||
create_gtwizard_ip "${base_name}_ll_ch" $preset $config
|
||||
79
src/eth/tb/taxi_eth_mac_1g_basex_us/Makefile
Normal file
79
src/eth/tb/taxi_eth_mac_1g_basex_us/Makefile
Normal file
@@ -0,0 +1,79 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2021-2026 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_eth_mac_1g_basex_us
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/us/$(DUT).f
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_SIM := 1
|
||||
export PARAM_VENDOR := "\"XILINX\""
|
||||
export PARAM_FAMILY := "\"virtexuplus\""
|
||||
export PARAM_CNT := 4
|
||||
export PARAM_CFG_LOW_LATENCY := 1
|
||||
export PARAM_GT_TYPE := "\"GTY\""
|
||||
export PARAM_QPLL0_PD := 0
|
||||
export PARAM_QPLL1_PD := 1
|
||||
export PARAM_QPLL0_EXT_CTRL := 0
|
||||
export PARAM_QPLL1_EXT_CTRL := 0
|
||||
export PARAM_COMBINED_MAC_PCS := 1
|
||||
export PARAM_DIC_EN := 1
|
||||
export PARAM_PTP_TS_EN := 1
|
||||
export PARAM_PTP_TD_EN := $(PARAM_PTP_TS_EN)
|
||||
export PARAM_PTP_TS_FMT_TOD := 1
|
||||
export PARAM_PTP_TS_W := $(if $(filter-out 1,$(PARAM_PTP_TS_FMT_TOD)),64,96)
|
||||
export PARAM_PTP_TD_SDI_PIPELINE := 2
|
||||
export PARAM_TX_TAG_W := 16
|
||||
export PARAM_PRBS31_EN := 1
|
||||
export PARAM_TX_SERDES_PIPELINE := 2
|
||||
export PARAM_RX_SERDES_PIPELINE := 2
|
||||
export PARAM_COUNT_125US := 195
|
||||
export PARAM_PFC_EN := 1
|
||||
export PARAM_PAUSE_EN := $(PARAM_PFC_EN)
|
||||
export PARAM_STAT_EN := 1
|
||||
export PARAM_STAT_TX_LEVEL := 2
|
||||
export PARAM_STAT_RX_LEVEL := $(PARAM_STAT_TX_LEVEL)
|
||||
export PARAM_STAT_ID_BASE := 0
|
||||
export PARAM_STAT_UPDATE_PERIOD := 1024
|
||||
export PARAM_STAT_STR_EN := 1
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
1
src/eth/tb/taxi_eth_mac_1g_basex_us/basex.py
Symbolic link
1
src/eth/tb/taxi_eth_mac_1g_basex_us/basex.py
Symbolic link
@@ -0,0 +1 @@
|
||||
../basex.py
|
||||
1
src/eth/tb/taxi_eth_mac_1g_basex_us/ptp_td.py
Symbolic link
1
src/eth/tb/taxi_eth_mac_1g_basex_us/ptp_td.py
Symbolic link
@@ -0,0 +1 @@
|
||||
../../lib/taxi/src/ptp/tb/ptp_td.py
|
||||
@@ -0,0 +1,897 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2021-2026 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import struct
|
||||
import sys
|
||||
|
||||
from scapy.layers.l2 import Ether
|
||||
|
||||
import pytest
|
||||
import cocotb_test.simulator
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge
|
||||
from cocotb.utils import get_time_from_sim_steps
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.eth import GmiiFrame, PtpClockSimTime
|
||||
from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame
|
||||
from cocotbext.axi import ApbBus, ApbMaster
|
||||
|
||||
try:
|
||||
from basex import BaseXSerdesSource, BaseXSerdesSink
|
||||
from ptp_td import PtpTdSource
|
||||
except ImportError:
|
||||
# attempt import from current directory
|
||||
sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
|
||||
try:
|
||||
from basex import BaseXSerdesSource, BaseXSerdesSink
|
||||
from ptp_td import PtpTdSource
|
||||
finally:
|
||||
del sys.path[0]
|
||||
|
||||
|
||||
class TB:
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.xcvr_ctrl_clk, 8, units="ns").start())
|
||||
cocotb.start_soon(Clock(dut.stat_clk, 8, units="ns").start())
|
||||
cocotb.start_soon(Clock(dut.xcvr_gtrefclk00_in, 6.206, units="ns").start())
|
||||
|
||||
self.apb_ctrl = ApbMaster(ApbBus.from_entity(dut.s_apb_ctrl), dut.xcvr_ctrl_clk, dut.xcvr_ctrl_rst)
|
||||
|
||||
self.serdes_sources = []
|
||||
self.serdes_sinks = []
|
||||
|
||||
self.clk_period = []
|
||||
|
||||
for ch in dut.uut.ch:
|
||||
gt_inst = ch.ch_inst.gt.gt_inst
|
||||
|
||||
if ch.ch_inst.CFG_LOW_LATENCY.value:
|
||||
clk = 16
|
||||
gbx_cfg = None
|
||||
else:
|
||||
clk = 16
|
||||
gbx_cfg = None
|
||||
|
||||
self.clk_period.append(clk)
|
||||
|
||||
cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start())
|
||||
cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start())
|
||||
|
||||
self.serdes_sources.append(BaseXSerdesSource(
|
||||
data=gt_inst.serdes_rx_data,
|
||||
data_k=gt_inst.serdes_rx_data_k,
|
||||
data_valid=gt_inst.serdes_rx_data_valid,
|
||||
clock=gt_inst.rx_clk,
|
||||
enc_8b10b=False,
|
||||
gbx_cfg=gbx_cfg
|
||||
))
|
||||
self.serdes_sinks.append(BaseXSerdesSink(
|
||||
data=gt_inst.serdes_tx_data,
|
||||
data_k=gt_inst.serdes_tx_data_k,
|
||||
data_valid=gt_inst.serdes_tx_data_valid,
|
||||
gbx_sync=gt_inst.serdes_tx_gbx_sync,
|
||||
clock=gt_inst.tx_clk,
|
||||
dec_8b10b=False,
|
||||
gbx_cfg=gbx_cfg
|
||||
))
|
||||
|
||||
self.axis_sources = []
|
||||
self.tx_cpl_sinks = []
|
||||
self.axis_sinks = []
|
||||
|
||||
for k in range(4):
|
||||
self.axis_sources.append(AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_tx[k]), dut.uut.ch[k].ch_inst.gt.gt_inst.tx_clk, dut.tx_rst_out[k]))
|
||||
self.tx_cpl_sinks.append(AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl[k]), dut.uut.ch[k].ch_inst.gt.gt_inst.tx_clk, dut.tx_rst_out[k]))
|
||||
self.axis_sinks.append(AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx[k]), dut.uut.ch[k].ch_inst.gt.gt_inst.rx_clk, dut.rx_rst_out[k]))
|
||||
|
||||
self.stat_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_stat), dut.stat_clk, dut.stat_rst)
|
||||
|
||||
self.rx_ptp_clocks = []
|
||||
self.tx_ptp_clocks = []
|
||||
|
||||
for k in range(4):
|
||||
self.rx_ptp_clocks.append(PtpClockSimTime(ts_tod=dut.rx_ptp_ts_in[k], clock=dut.uut.ch[k].ch_inst.gt.gt_inst.rx_clk))
|
||||
self.tx_ptp_clocks.append(PtpClockSimTime(ts_tod=dut.tx_ptp_ts_in[k], clock=dut.uut.ch[k].ch_inst.gt.gt_inst.tx_clk))
|
||||
|
||||
self.ptp_clk_period = self.clk_period[0]
|
||||
|
||||
cocotb.start_soon(Clock(dut.ptp_clk, self.ptp_clk_period, units="ns").start())
|
||||
cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start())
|
||||
|
||||
self.ptp_td_source = PtpTdSource(
|
||||
data=dut.ptp_td_sdi,
|
||||
clock=dut.ptp_clk,
|
||||
reset=dut.ptp_rst,
|
||||
period_ns=self.ptp_clk_period
|
||||
)
|
||||
|
||||
dut.rx_rst_in.setimmediatevalue([0]*4)
|
||||
dut.tx_rst_in.setimmediatevalue([0]*4)
|
||||
|
||||
dut.stat_rx_fifo_drop.setimmediatevalue([0]*4)
|
||||
|
||||
dut.cfg_tx_pad_en.setimmediatevalue([0]*4)
|
||||
dut.cfg_tx_min_pkt_len.setimmediatevalue([0]*4)
|
||||
dut.cfg_tx_max_pkt_len.setimmediatevalue([0]*4)
|
||||
dut.cfg_tx_ifg.setimmediatevalue([0]*4)
|
||||
dut.cfg_tx_enable.setimmediatevalue([0]*4)
|
||||
dut.cfg_rx_max_pkt_len.setimmediatevalue([0]*4)
|
||||
dut.cfg_rx_enable.setimmediatevalue([0]*4)
|
||||
dut.cfg_tx_prbs31_enable.setimmediatevalue([0]*4)
|
||||
dut.cfg_rx_prbs31_enable.setimmediatevalue([0]*4)
|
||||
dut.cfg_mcf_rx_eth_dst_mcast.setimmediatevalue([0]*4)
|
||||
dut.cfg_mcf_rx_check_eth_dst_mcast.setimmediatevalue([0]*4)
|
||||
dut.cfg_mcf_rx_eth_dst_ucast.setimmediatevalue([0]*4)
|
||||
dut.cfg_mcf_rx_check_eth_dst_ucast.setimmediatevalue([0]*4)
|
||||
dut.cfg_mcf_rx_eth_src.setimmediatevalue([0]*4)
|
||||
dut.cfg_mcf_rx_check_eth_src.setimmediatevalue([0]*4)
|
||||
dut.cfg_mcf_rx_eth_type.setimmediatevalue([0]*4)
|
||||
dut.cfg_mcf_rx_opcode_lfc.setimmediatevalue([0]*4)
|
||||
dut.cfg_mcf_rx_check_opcode_lfc.setimmediatevalue([0]*4)
|
||||
dut.cfg_mcf_rx_opcode_pfc.setimmediatevalue([0]*4)
|
||||
dut.cfg_mcf_rx_check_opcode_pfc.setimmediatevalue([0]*4)
|
||||
dut.cfg_mcf_rx_forward.setimmediatevalue([0]*4)
|
||||
dut.cfg_mcf_rx_enable.setimmediatevalue([0]*4)
|
||||
dut.cfg_tx_lfc_eth_dst.setimmediatevalue([0]*4)
|
||||
dut.cfg_tx_lfc_eth_src.setimmediatevalue([0]*4)
|
||||
dut.cfg_tx_lfc_eth_type.setimmediatevalue([0]*4)
|
||||
dut.cfg_tx_lfc_opcode.setimmediatevalue([0]*4)
|
||||
dut.cfg_tx_lfc_en.setimmediatevalue([0]*4)
|
||||
dut.cfg_tx_lfc_quanta.setimmediatevalue([0]*4)
|
||||
dut.cfg_tx_lfc_refresh.setimmediatevalue([0]*4)
|
||||
dut.cfg_tx_pfc_eth_dst.setimmediatevalue([0]*4)
|
||||
dut.cfg_tx_pfc_eth_src.setimmediatevalue([0]*4)
|
||||
dut.cfg_tx_pfc_eth_type.setimmediatevalue([0]*4)
|
||||
dut.cfg_tx_pfc_opcode.setimmediatevalue([0]*4)
|
||||
dut.cfg_tx_pfc_en.setimmediatevalue([0]*4)
|
||||
for x in range(4):
|
||||
for y in range(8):
|
||||
dut.cfg_tx_pfc_quanta[x][y].setimmediatevalue(0)
|
||||
dut.cfg_tx_pfc_refresh[x][y].setimmediatevalue(0)
|
||||
dut.cfg_rx_lfc_opcode.setimmediatevalue([0]*4)
|
||||
dut.cfg_rx_lfc_en.setimmediatevalue([0]*4)
|
||||
dut.cfg_rx_pfc_opcode.setimmediatevalue([0]*4)
|
||||
dut.cfg_rx_pfc_en.setimmediatevalue([0]*4)
|
||||
|
||||
async def reset(self):
|
||||
self.dut.xcvr_ctrl_rst.setimmediatevalue(0)
|
||||
self.dut.ptp_rst.setimmediatevalue(0)
|
||||
self.dut.stat_rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.xcvr_ctrl_clk)
|
||||
await RisingEdge(self.dut.xcvr_ctrl_clk)
|
||||
self.dut.xcvr_ctrl_rst.value = 1
|
||||
self.dut.ptp_rst.value = 1
|
||||
self.dut.stat_rst.value = 1
|
||||
await RisingEdge(self.dut.xcvr_ctrl_clk)
|
||||
await RisingEdge(self.dut.xcvr_ctrl_clk)
|
||||
self.dut.xcvr_ctrl_rst.value = 0
|
||||
self.dut.ptp_rst.value = 0
|
||||
self.dut.stat_rst.value = 0
|
||||
await RisingEdge(self.dut.xcvr_ctrl_clk)
|
||||
await RisingEdge(self.dut.xcvr_ctrl_clk)
|
||||
|
||||
self.ptp_td_source.set_ts_tod_sim_time()
|
||||
self.ptp_td_source.set_ts_rel_sim_time()
|
||||
|
||||
|
||||
async def run_test_regs(dut):
|
||||
tb = TB(dut)
|
||||
await tb.reset()
|
||||
|
||||
data = await tb.apb_ctrl.read(0x00000, 2)
|
||||
data = await tb.apb_ctrl.read(0x04000, 2)
|
||||
data = await tb.apb_ctrl.read(0x08000, 2)
|
||||
data = await tb.apb_ctrl.read(0x0C000, 2)
|
||||
|
||||
data = await tb.apb_ctrl.read(0x10000, 2)
|
||||
data = await tb.apb_ctrl.read(0x14000, 2)
|
||||
data = await tb.apb_ctrl.read(0x18000, 2)
|
||||
data = await tb.apb_ctrl.read(0x1C000, 2)
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(dut.xcvr_ctrl_clk)
|
||||
|
||||
|
||||
async def run_test_rx(dut, port=0, payload_lengths=None, payload_data=None, ifg=12):
|
||||
|
||||
if dut.COMBINED_MAC_PCS.value:
|
||||
pipe_delay = 3
|
||||
else:
|
||||
pipe_delay = 3
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
tb.serdes_sources[port].ifg = ifg
|
||||
tb.dut.cfg_tx_ifg[port].value = ifg
|
||||
tb.dut.cfg_rx_max_pkt_len[port].value = 9218-1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.dut.cfg_rx_enable[port].value = 0
|
||||
|
||||
tb.log.info("Wait for reset")
|
||||
while int(dut.rx_rst_out[port].value):
|
||||
await RisingEdge(dut.xcvr_ctrl_clk)
|
||||
|
||||
tb.log.info("Wait for block lock")
|
||||
while not int(dut.rx_block_lock[port].value):
|
||||
await RisingEdge(dut.xcvr_ctrl_clk)
|
||||
|
||||
tb.log.info("Wait for PTP CDC lock")
|
||||
while not int(dut.rx_ptp_locked[port].value):
|
||||
await RisingEdge(dut.xcvr_ctrl_clk)
|
||||
for k in range(2000):
|
||||
await RisingEdge(dut.xcvr_ctrl_clk)
|
||||
|
||||
tb.dut.cfg_rx_enable[port].value = 1
|
||||
|
||||
test_frames = [payload_data(x) for x in payload_lengths()]
|
||||
tx_frames = []
|
||||
|
||||
for test_data in test_frames:
|
||||
test_frame = GmiiFrame.from_payload(test_data, tx_complete=tx_frames.append)
|
||||
await tb.serdes_sources[port].send(test_frame)
|
||||
|
||||
for test_data in test_frames:
|
||||
rx_frame = await tb.axis_sinks[port].recv()
|
||||
tx_frame = tx_frames.pop(0)
|
||||
|
||||
frame_error = rx_frame.tuser & 1
|
||||
ptp_ts = rx_frame.tuser >> 1
|
||||
ptp_ts_ns = ptp_ts / 2**16
|
||||
|
||||
print(tx_frame)
|
||||
|
||||
tx_frame_sfd_ns = get_time_from_sim_steps(tx_frame.sim_time_sfd, "ns")
|
||||
|
||||
tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns)
|
||||
tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns)
|
||||
tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns))
|
||||
tb.log.info("Error: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns - tb.clk_period[port]*pipe_delay))
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert frame_error == 0
|
||||
if not tb.serdes_sources[port].gbx_seq_len:
|
||||
if dut.PTP_TD_EN.value:
|
||||
assert abs(ptp_ts_ns - tx_frame_sfd_ns - tb.clk_period[port]*pipe_delay) < tb.clk_period[port]*5
|
||||
else:
|
||||
assert abs(ptp_ts_ns - tx_frame_sfd_ns - tb.clk_period[port]*pipe_delay) < 0.01
|
||||
|
||||
assert tb.axis_sinks[port].empty()
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(dut.xcvr_ctrl_clk)
|
||||
|
||||
|
||||
async def run_test_tx(dut, port=0, payload_lengths=None, payload_data=None, ifg=12):
|
||||
|
||||
if dut.COMBINED_MAC_PCS.value:
|
||||
pipe_delay = 4
|
||||
else:
|
||||
pipe_delay = 4
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
tb.serdes_sources[port].ifg = ifg
|
||||
tb.dut.cfg_tx_pad_en[port].value = 1
|
||||
tb.dut.cfg_tx_min_pkt_len[port].value = 60-1
|
||||
tb.dut.cfg_tx_max_pkt_len[port].value = 9218-1
|
||||
tb.dut.cfg_tx_ifg[port].value = ifg
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.log.info("Wait for reset")
|
||||
while int(dut.tx_rst_out[port].value):
|
||||
await RisingEdge(dut.xcvr_ctrl_clk)
|
||||
|
||||
tb.log.info("Wait for PTP CDC lock")
|
||||
while not int(dut.tx_ptp_locked[port].value):
|
||||
await RisingEdge(dut.xcvr_ctrl_clk)
|
||||
for k in range(2000):
|
||||
await RisingEdge(dut.xcvr_ctrl_clk)
|
||||
|
||||
tb.dut.cfg_tx_enable[port].value = 1
|
||||
|
||||
for p in tb.serdes_sinks:
|
||||
p.clear()
|
||||
|
||||
test_frames = [payload_data(x) for x in payload_lengths()]
|
||||
|
||||
for test_data in test_frames:
|
||||
await tb.axis_sources[port].send(AxiStreamFrame(test_data, tid=0, tuser=0))
|
||||
|
||||
for test_data in test_frames:
|
||||
rx_frame = await tb.serdes_sinks[port].recv()
|
||||
tx_cpl = await tb.tx_cpl_sinks[port].recv()
|
||||
|
||||
ptp_ts_ns = int(tx_cpl.tdata[0]) / 2**16
|
||||
|
||||
rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
|
||||
|
||||
tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
|
||||
tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
|
||||
tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))
|
||||
tb.log.info("Error: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period[port]*pipe_delay))
|
||||
|
||||
assert rx_frame.get_payload() == test_data
|
||||
assert rx_frame.check_fcs()
|
||||
assert rx_frame.error is None
|
||||
if not tb.serdes_sinks[port].gbx_seq_len:
|
||||
if dut.PTP_TD_EN.value:
|
||||
assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period[port]*pipe_delay) < tb.clk_period[port]*5
|
||||
else:
|
||||
assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period[port]*pipe_delay) < 0.01
|
||||
|
||||
assert tb.serdes_sinks[port].empty()
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(dut.xcvr_ctrl_clk)
|
||||
|
||||
|
||||
async def run_test_tx_underrun(dut, port=0, ifg=12):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
tb.serdes_sources[port].ifg = ifg
|
||||
tb.dut.cfg_tx_pad_en[port].value = 1
|
||||
tb.dut.cfg_tx_min_pkt_len[port].value = 60-1
|
||||
tb.dut.cfg_tx_max_pkt_len[port].value = 9218-1
|
||||
tb.dut.cfg_tx_ifg[port].value = ifg
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.log.info("Wait for reset")
|
||||
while int(dut.tx_rst_out[port].value):
|
||||
await RisingEdge(dut.xcvr_ctrl_clk)
|
||||
|
||||
for k in range(100):
|
||||
await RisingEdge(dut.xcvr_ctrl_clk)
|
||||
|
||||
tb.dut.cfg_tx_enable[port].value = 1
|
||||
|
||||
for p in tb.serdes_sinks:
|
||||
p.clear()
|
||||
|
||||
test_data = bytes(x for x in range(60))
|
||||
|
||||
for k in range(3):
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.axis_sources[port].send(test_frame)
|
||||
|
||||
for k in range(64*16 // tb.axis_sources[port].width):
|
||||
await RisingEdge(dut.tx_clk[port])
|
||||
|
||||
tb.axis_sources[port].pause = True
|
||||
|
||||
for k in range(4):
|
||||
await RisingEdge(dut.tx_clk[port])
|
||||
|
||||
tb.axis_sources[port].pause = False
|
||||
|
||||
for k in range(3):
|
||||
rx_frame = await tb.serdes_sinks[port].recv()
|
||||
|
||||
if k == 1:
|
||||
assert rx_frame.data[-1] == 0xFE
|
||||
assert rx_frame.error[-1] == 1
|
||||
else:
|
||||
assert rx_frame.get_payload() == test_data
|
||||
assert rx_frame.check_fcs()
|
||||
assert rx_frame.error is None
|
||||
|
||||
assert tb.serdes_sinks[port].empty()
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(dut.xcvr_ctrl_clk)
|
||||
|
||||
|
||||
async def run_test_tx_error(dut, port=0, ifg=12):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
tb.serdes_sources[port].ifg = ifg
|
||||
tb.dut.cfg_tx_pad_en[port].value = 1
|
||||
tb.dut.cfg_tx_min_pkt_len[port].value = 60-1
|
||||
tb.dut.cfg_tx_max_pkt_len[port].value = 9218-1
|
||||
tb.dut.cfg_tx_ifg[port].value = ifg
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.log.info("Wait for reset")
|
||||
while int(dut.tx_rst_out[port].value):
|
||||
await RisingEdge(dut.xcvr_ctrl_clk)
|
||||
|
||||
for k in range(100):
|
||||
await RisingEdge(dut.xcvr_ctrl_clk)
|
||||
|
||||
tb.dut.cfg_tx_enable[port].value = 1
|
||||
|
||||
for p in tb.serdes_sinks:
|
||||
p.clear()
|
||||
|
||||
test_data = bytes(x for x in range(60))
|
||||
|
||||
for k in range(3):
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
if k == 1:
|
||||
test_frame.tuser = 1
|
||||
await tb.axis_sources[port].send(test_frame)
|
||||
|
||||
for k in range(3):
|
||||
rx_frame = await tb.serdes_sinks[port].recv()
|
||||
|
||||
if k == 1:
|
||||
assert rx_frame.data[-1] == 0xFE
|
||||
assert rx_frame.error[-1] == 1
|
||||
else:
|
||||
assert rx_frame.get_payload() == test_data
|
||||
assert rx_frame.check_fcs()
|
||||
assert rx_frame.error is None
|
||||
|
||||
assert tb.serdes_sinks[port].empty()
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(dut.xcvr_ctrl_clk)
|
||||
|
||||
|
||||
async def run_test_lfc(dut, port=0, ifg=12):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
tb.serdes_sources[port].ifg = ifg
|
||||
tb.dut.cfg_tx_pad_en[port].value = 1
|
||||
tb.dut.cfg_tx_min_pkt_len[port].value = 60-1
|
||||
tb.dut.cfg_tx_max_pkt_len[port].value = 9218-1
|
||||
tb.dut.cfg_tx_ifg[port].value = ifg
|
||||
tb.dut.cfg_rx_max_pkt_len[port].value = 9218-1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.log.info("Wait for reset")
|
||||
while int(dut.rx_rst_out[port].value):
|
||||
await RisingEdge(dut.xcvr_ctrl_clk)
|
||||
|
||||
tb.log.info("Wait for block lock")
|
||||
while not int(dut.rx_block_lock[port].value):
|
||||
await RisingEdge(dut.xcvr_ctrl_clk)
|
||||
|
||||
for k in range(100):
|
||||
await RisingEdge(dut.xcvr_ctrl_clk)
|
||||
|
||||
tb.dut.cfg_tx_enable[port].value = 1
|
||||
tb.dut.cfg_rx_enable[port].value = 1
|
||||
|
||||
for p in tb.serdes_sinks:
|
||||
p.clear()
|
||||
|
||||
dut.tx_lfc_req[port].value = 0
|
||||
dut.tx_lfc_resend[port].value = 0
|
||||
dut.rx_lfc_en[port].value = 1
|
||||
dut.rx_lfc_ack[port].value = 0
|
||||
|
||||
dut.tx_lfc_pause_en[port].value = 1
|
||||
dut.tx_pause_req[port].value = 0
|
||||
|
||||
dut.cfg_mcf_rx_eth_dst_mcast[port].value = 0x0180C2000001
|
||||
dut.cfg_mcf_rx_check_eth_dst_mcast[port].value = 1
|
||||
dut.cfg_mcf_rx_eth_dst_ucast[port].value = 0xDAD1D2D3D4D5
|
||||
dut.cfg_mcf_rx_check_eth_dst_ucast[port].value = 0
|
||||
dut.cfg_mcf_rx_eth_src[port].value = 0x5A5152535455
|
||||
dut.cfg_mcf_rx_check_eth_src[port].value = 0
|
||||
dut.cfg_mcf_rx_eth_type[port].value = 0x8808
|
||||
dut.cfg_mcf_rx_opcode_lfc[port].value = 0x0001
|
||||
dut.cfg_mcf_rx_check_opcode_lfc[port].value = 1
|
||||
dut.cfg_mcf_rx_opcode_pfc[port].value = 0x0101
|
||||
dut.cfg_mcf_rx_check_opcode_pfc[port].value = 1
|
||||
|
||||
dut.cfg_mcf_rx_forward[port].value = 0
|
||||
dut.cfg_mcf_rx_enable[port].value = 1
|
||||
|
||||
dut.cfg_tx_lfc_eth_dst[port].value = 0x0180C2000001
|
||||
dut.cfg_tx_lfc_eth_src[port].value = 0x5A5152535455
|
||||
dut.cfg_tx_lfc_eth_type[port].value = 0x8808
|
||||
dut.cfg_tx_lfc_opcode[port].value = 0x0001
|
||||
dut.cfg_tx_lfc_en[port].value = 1
|
||||
dut.cfg_tx_lfc_quanta[port].value = 0xFFFF
|
||||
dut.cfg_tx_lfc_refresh[port].value = 0x7F00
|
||||
|
||||
dut.cfg_rx_lfc_opcode[port].value = 0x0001
|
||||
dut.cfg_rx_lfc_en[port].value = 1
|
||||
|
||||
test_tx_pkts = []
|
||||
test_rx_pkts = []
|
||||
|
||||
for k in range(32):
|
||||
length = 512
|
||||
payload = bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000)
|
||||
test_pkt = eth / payload
|
||||
test_tx_pkts.append(test_pkt.copy())
|
||||
|
||||
await tb.axis_sources[port].send(bytes(test_pkt))
|
||||
|
||||
eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='5A:51:52:53:54:55', type=0x8000)
|
||||
test_pkt = eth / payload
|
||||
test_rx_pkts.append(test_pkt.copy())
|
||||
|
||||
test_frame = GmiiFrame.from_payload(bytes(test_pkt))
|
||||
await tb.serdes_sources[port].send(test_frame)
|
||||
|
||||
if k == 16:
|
||||
eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808)
|
||||
test_pkt = eth / struct.pack('!HH', 0x0001, 100)
|
||||
test_rx_pkts.append(test_pkt.copy())
|
||||
|
||||
test_frame = GmiiFrame.from_payload(bytes(test_pkt))
|
||||
await tb.serdes_sources[port].send(test_frame)
|
||||
|
||||
for k in range(200):
|
||||
await RisingEdge(dut.xcvr_ctrl_clk)
|
||||
|
||||
dut.tx_lfc_req[port].value = 1
|
||||
|
||||
for k in range(200):
|
||||
await RisingEdge(dut.xcvr_ctrl_clk)
|
||||
|
||||
dut.tx_lfc_req[port].value = 0
|
||||
|
||||
while not int(dut.rx_lfc_req[port].value):
|
||||
await RisingEdge(dut.xcvr_ctrl_clk)
|
||||
|
||||
for k in range(200):
|
||||
await RisingEdge(dut.xcvr_ctrl_clk)
|
||||
|
||||
dut.tx_lfc_req[port].value = 1
|
||||
|
||||
for k in range(200):
|
||||
await RisingEdge(dut.xcvr_ctrl_clk)
|
||||
|
||||
dut.tx_lfc_req[port].value = 0
|
||||
|
||||
while test_rx_pkts:
|
||||
rx_frame = await tb.axis_sinks[port].recv()
|
||||
|
||||
rx_pkt = Ether(bytes(rx_frame))
|
||||
|
||||
tb.log.info("RX packet: %s", repr(rx_pkt))
|
||||
|
||||
if rx_pkt.type == 0x8808:
|
||||
test_pkt = test_rx_pkts.pop(0)
|
||||
# check prefix as frame gets zero-padded
|
||||
assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
|
||||
if isinstance(rx_frame.tuser, list):
|
||||
assert rx_frame.tuser[-1] & 1
|
||||
else:
|
||||
assert rx_frame.tuser & 1
|
||||
else:
|
||||
test_pkt = test_rx_pkts.pop(0)
|
||||
# check prefix as frame gets zero-padded
|
||||
assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
|
||||
if isinstance(rx_frame.tuser, list):
|
||||
assert not rx_frame.tuser[-1] & 1
|
||||
else:
|
||||
assert not rx_frame.tuser & 1
|
||||
|
||||
tx_lfc_cnt = 0
|
||||
|
||||
while test_tx_pkts:
|
||||
tx_frame = await tb.serdes_sinks[port].recv()
|
||||
|
||||
tx_pkt = Ether(bytes(tx_frame.get_payload()))
|
||||
|
||||
tb.log.info("TX packet: %s", repr(tx_pkt))
|
||||
|
||||
if tx_pkt.type == 0x8808:
|
||||
tx_lfc_cnt += 1
|
||||
else:
|
||||
test_pkt = test_tx_pkts.pop(0)
|
||||
# check prefix as frame gets zero-padded
|
||||
assert bytes(tx_pkt).find(bytes(test_pkt)) == 0
|
||||
|
||||
assert tx_lfc_cnt == 4
|
||||
|
||||
assert tb.axis_sinks[port].empty()
|
||||
assert tb.serdes_sinks[port].empty()
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(dut.xcvr_ctrl_clk)
|
||||
|
||||
|
||||
async def run_test_pfc(dut, port=0, ifg=12):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
tb.serdes_sources[port].ifg = ifg
|
||||
tb.dut.cfg_tx_pad_en[port].value = 1
|
||||
tb.dut.cfg_tx_min_pkt_len[port].value = 60-1
|
||||
tb.dut.cfg_tx_max_pkt_len[port].value = 9218-1
|
||||
tb.dut.cfg_tx_ifg[port].value = ifg
|
||||
tb.dut.cfg_rx_max_pkt_len[port].value = 9218-1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.log.info("Wait for reset")
|
||||
while int(dut.rx_rst_out[port].value):
|
||||
await RisingEdge(dut.xcvr_ctrl_clk)
|
||||
|
||||
tb.log.info("Wait for block lock")
|
||||
while not int(dut.rx_block_lock[port].value):
|
||||
await RisingEdge(dut.xcvr_ctrl_clk)
|
||||
|
||||
for k in range(100):
|
||||
await RisingEdge(dut.xcvr_ctrl_clk)
|
||||
|
||||
tb.dut.cfg_tx_enable[port].value = 1
|
||||
tb.dut.cfg_rx_enable[port].value = 1
|
||||
|
||||
for p in tb.serdes_sinks:
|
||||
p.clear()
|
||||
|
||||
dut.tx_pfc_req[port].value = 0x00
|
||||
dut.tx_pfc_resend[port].value = 0
|
||||
dut.rx_pfc_en[port].value = 0xff
|
||||
dut.rx_pfc_ack[port].value = 0x00
|
||||
|
||||
dut.tx_lfc_pause_en[port].value = 0
|
||||
dut.tx_pause_req[port].value = 0
|
||||
|
||||
dut.cfg_mcf_rx_eth_dst_mcast[port].value = 0x0180C2000001
|
||||
dut.cfg_mcf_rx_check_eth_dst_mcast[port].value = 1
|
||||
dut.cfg_mcf_rx_eth_dst_ucast[port].value = 0xDAD1D2D3D4D5
|
||||
dut.cfg_mcf_rx_check_eth_dst_ucast[port].value = 0
|
||||
dut.cfg_mcf_rx_eth_src[port].value = 0x5A5152535455
|
||||
dut.cfg_mcf_rx_check_eth_src[port].value = 0
|
||||
dut.cfg_mcf_rx_eth_type[port].value = 0x8808
|
||||
dut.cfg_mcf_rx_opcode_lfc[port].value = 0x0001
|
||||
dut.cfg_mcf_rx_check_opcode_lfc[port].value = 1
|
||||
dut.cfg_mcf_rx_opcode_pfc[port].value = 0x0101
|
||||
dut.cfg_mcf_rx_check_opcode_pfc[port].value = 1
|
||||
|
||||
dut.cfg_mcf_rx_forward[port].value = 0
|
||||
dut.cfg_mcf_rx_enable[port].value = 1
|
||||
|
||||
dut.cfg_tx_pfc_eth_dst[port].value = 0x0180C2000001
|
||||
dut.cfg_tx_pfc_eth_src[port].value = 0x5A5152535455
|
||||
dut.cfg_tx_pfc_eth_type[port].value = 0x8808
|
||||
dut.cfg_tx_pfc_opcode[port].value = 0x0101
|
||||
dut.cfg_tx_pfc_en[port].value = 1
|
||||
for k in range(8):
|
||||
dut.cfg_tx_pfc_quanta[port][k].value = 0xFFFF
|
||||
dut.cfg_tx_pfc_refresh[port][k].value = 0x7FF0
|
||||
|
||||
dut.cfg_rx_pfc_opcode[port].value = 0x0101
|
||||
dut.cfg_rx_pfc_en[port].value = 1
|
||||
|
||||
test_tx_pkts = []
|
||||
test_rx_pkts = []
|
||||
|
||||
for k in range(32):
|
||||
length = 512
|
||||
payload = bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000)
|
||||
test_pkt = eth / payload
|
||||
test_tx_pkts.append(test_pkt.copy())
|
||||
|
||||
await tb.axis_sources[port].send(bytes(test_pkt))
|
||||
|
||||
eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='5A:51:52:53:54:55', type=0x8000)
|
||||
test_pkt = eth / payload
|
||||
test_rx_pkts.append(test_pkt.copy())
|
||||
|
||||
test_frame = GmiiFrame.from_payload(bytes(test_pkt))
|
||||
await tb.serdes_sources[port].send(test_frame)
|
||||
|
||||
if k == 16:
|
||||
eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808)
|
||||
test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x00FF, 10, 20, 30, 40, 50, 60, 70, 80)
|
||||
test_rx_pkts.append(test_pkt.copy())
|
||||
|
||||
test_frame = GmiiFrame.from_payload(bytes(test_pkt))
|
||||
await tb.serdes_sources[port].send(test_frame)
|
||||
|
||||
dut.rx_pfc_ack[port].value = 0xff
|
||||
|
||||
for i in range(8):
|
||||
for k in range(500):
|
||||
await RisingEdge(dut.tx_clk[port])
|
||||
|
||||
dut.tx_pfc_req[port].value = 0xff >> (7-i)
|
||||
|
||||
for k in range(500):
|
||||
await RisingEdge(dut.tx_clk[port])
|
||||
|
||||
dut.tx_pfc_req[port].value = 0x00
|
||||
|
||||
while test_rx_pkts:
|
||||
rx_frame = await tb.axis_sinks[port].recv()
|
||||
|
||||
rx_pkt = Ether(bytes(rx_frame))
|
||||
|
||||
tb.log.info("RX packet: %s", repr(rx_pkt))
|
||||
|
||||
if rx_pkt.type == 0x8808:
|
||||
test_pkt = test_rx_pkts.pop(0)
|
||||
# check prefix as frame gets zero-padded
|
||||
assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
|
||||
if isinstance(rx_frame.tuser, list):
|
||||
assert rx_frame.tuser[-1] & 1
|
||||
else:
|
||||
assert rx_frame.tuser & 1
|
||||
else:
|
||||
test_pkt = test_rx_pkts.pop(0)
|
||||
# check prefix as frame gets zero-padded
|
||||
assert bytes(rx_pkt).find(bytes(test_pkt)) == 0
|
||||
if isinstance(rx_frame.tuser, list):
|
||||
assert not rx_frame.tuser[-1] & 1
|
||||
else:
|
||||
assert not rx_frame.tuser & 1
|
||||
|
||||
tx_pfc_cnt = 0
|
||||
|
||||
while test_tx_pkts:
|
||||
tx_frame = await tb.serdes_sinks[port].recv()
|
||||
|
||||
tx_pkt = Ether(bytes(tx_frame.get_payload()))
|
||||
|
||||
tb.log.info("TX packet: %s", repr(tx_pkt))
|
||||
|
||||
if tx_pkt.type == 0x8808:
|
||||
tx_pfc_cnt += 1
|
||||
else:
|
||||
test_pkt = test_tx_pkts.pop(0)
|
||||
# check prefix as frame gets zero-padded
|
||||
assert bytes(tx_pkt).find(bytes(test_pkt)) == 0
|
||||
|
||||
# TODO adjust this; possible verilator bug
|
||||
#assert tx_pfc_cnt == 9
|
||||
assert tx_pfc_cnt >= 9
|
||||
|
||||
assert tb.axis_sinks[port].empty()
|
||||
assert tb.serdes_sinks[port].empty()
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(dut.xcvr_ctrl_clk)
|
||||
|
||||
|
||||
def size_list():
|
||||
return list(range(60, 128)) + [512, 1514, 9214] + [60]*10
|
||||
|
||||
|
||||
def incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
|
||||
def cycle_en():
|
||||
return itertools.cycle([0, 0, 0, 1])
|
||||
|
||||
|
||||
if getattr(cocotb, 'top', None) is not None:
|
||||
|
||||
factory = TestFactory(run_test_regs)
|
||||
factory.generate_tests()
|
||||
|
||||
for test in [run_test_rx, run_test_tx]:
|
||||
|
||||
factory = TestFactory(test)
|
||||
factory.add_option("payload_lengths", [size_list])
|
||||
factory.add_option("payload_data", [incrementing_payload])
|
||||
factory.add_option("ifg", [12, 0])
|
||||
factory.generate_tests()
|
||||
|
||||
for test in [run_test_tx_underrun, run_test_tx_error]:
|
||||
|
||||
factory = TestFactory(test)
|
||||
factory.add_option("ifg", [12])
|
||||
factory.generate_tests()
|
||||
|
||||
if cocotb.top.PFC_EN.value:
|
||||
for test in [run_test_lfc, run_test_pfc]:
|
||||
factory = TestFactory(test)
|
||||
factory.add_option("ifg", [12])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize(("dic_en", "pfc_en"), [(1, 1), (1, 0), (0, 0)])
|
||||
@pytest.mark.parametrize("low_latency", [1, 0])
|
||||
def test_taxi_eth_mac_1g_basex_us(request, low_latency, dic_en, pfc_en):
|
||||
dut = "taxi_eth_mac_1g_basex_us"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, "us", f"{dut}.f"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['SIM'] = 1
|
||||
parameters['VENDOR'] = "\"XILINX\""
|
||||
parameters['FAMILY'] = "\"virtexuplus\""
|
||||
parameters['CNT'] = 4
|
||||
parameters['CFG_LOW_LATENCY'] = low_latency
|
||||
parameters['GT_TYPE'] = "\"GTY\""
|
||||
parameters['QPLL0_PD'] = 0
|
||||
parameters['QPLL1_PD'] = 1
|
||||
parameters['QPLL0_EXT_CTRL'] = 0
|
||||
parameters['QPLL1_EXT_CTRL'] = 0
|
||||
parameters['COMBINED_MAC_PCS'] = 1
|
||||
parameters['DIC_EN'] = dic_en
|
||||
parameters['PTP_TS_EN'] = 1
|
||||
parameters['PTP_TD_EN'] = parameters['PTP_TS_EN']
|
||||
parameters['PTP_TS_FMT_TOD'] = 1
|
||||
parameters['PTP_TS_W'] = 96 if parameters['PTP_TS_FMT_TOD'] else 64
|
||||
parameters['PTP_TD_SDI_PIPELINE'] = 2
|
||||
parameters['TX_TAG_W'] = 16
|
||||
parameters['PRBS31_EN'] = 1
|
||||
parameters['TX_SERDES_PIPELINE'] = 2
|
||||
parameters['RX_SERDES_PIPELINE'] = 2
|
||||
parameters['COUNT_125US'] = int(1250/6.4)
|
||||
parameters['PFC_EN'] = pfc_en
|
||||
parameters['PAUSE_EN'] = parameters['PFC_EN']
|
||||
parameters['STAT_EN'] = 1
|
||||
parameters['STAT_TX_LEVEL'] = 2
|
||||
parameters['STAT_RX_LEVEL'] = parameters['STAT_TX_LEVEL']
|
||||
parameters['STAT_ID_BASE'] = 0
|
||||
parameters['STAT_UPDATE_PERIOD'] = 1024
|
||||
parameters['STAT_STR_EN'] = 1
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
@@ -0,0 +1,494 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2026 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* Transceiver and MAC/PHY quad wrapper for UltraScale/UltraScale+ testbench
|
||||
*/
|
||||
module test_taxi_eth_mac_1g_basex_us #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter logic SIM = 1'b1,
|
||||
parameter string VENDOR = "XILINX",
|
||||
parameter string FAMILY = "virtexuplus",
|
||||
parameter CNT = 4,
|
||||
parameter logic CFG_LOW_LATENCY = 1'b0,
|
||||
parameter string GT_TYPE = "GTY",
|
||||
parameter logic QPLL0_PD = 1'b0,
|
||||
parameter logic QPLL1_PD = 1'b1,
|
||||
parameter logic QPLL0_EXT_CTRL = 1'b0,
|
||||
parameter logic QPLL1_EXT_CTRL = 1'b0,
|
||||
parameter logic [CNT-1:0] GT_TX_PD = '0,
|
||||
parameter logic [CNT-1:0] GT_TX_QPLL_SEL = '0,
|
||||
parameter logic [CNT-1:0] GT_TX_POLARITY = '0,
|
||||
parameter logic [CNT-1:0] GT_TX_ELECIDLE = '0,
|
||||
parameter logic [CNT-1:0] GT_TX_INHIBIT = '0,
|
||||
parameter logic [CNT-1:0][4:0] GT_TX_DIFFCTRL = '{CNT{5'd16}},
|
||||
parameter logic [CNT-1:0][6:0] GT_TX_MAINCURSOR = '{CNT{7'd64}},
|
||||
parameter logic [CNT-1:0][4:0] GT_TX_POSTCURSOR = '{CNT{5'd0}},
|
||||
parameter logic [CNT-1:0][4:0] GT_TX_PRECURSOR = '{CNT{5'd0}},
|
||||
parameter logic [CNT-1:0] GT_RX_PD = '0,
|
||||
parameter logic [CNT-1:0] GT_RX_QPLL_SEL = '0,
|
||||
parameter logic [CNT-1:0] GT_RX_LPM_EN = '0,
|
||||
parameter logic [CNT-1:0] GT_RX_POLARITY = '0,
|
||||
parameter logic COMBINED_MAC_PCS = 1'b1,
|
||||
parameter logic DIC_EN = 1'b1,
|
||||
parameter logic PTP_TS_EN = 1'b0,
|
||||
parameter logic PTP_TD_EN = PTP_TS_EN,
|
||||
parameter logic PTP_TS_FMT_TOD = 1'b1,
|
||||
parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64,
|
||||
parameter PTP_TD_SDI_PIPELINE = 2,
|
||||
parameter TX_TAG_W = 16,
|
||||
parameter logic PRBS31_EN = 1'b0,
|
||||
parameter TX_SERDES_PIPELINE = 1,
|
||||
parameter RX_SERDES_PIPELINE = 1,
|
||||
parameter COUNT_125US = 125000/6.4,
|
||||
parameter logic PFC_EN = 1'b0,
|
||||
parameter logic PAUSE_EN = PFC_EN,
|
||||
parameter logic STAT_EN = 1'b0,
|
||||
parameter STAT_TX_LEVEL = 1,
|
||||
parameter STAT_RX_LEVEL = 1,
|
||||
parameter STAT_ID_BASE = 0,
|
||||
parameter STAT_UPDATE_PERIOD = 1024,
|
||||
parameter logic STAT_STR_EN = 1'b0,
|
||||
parameter logic [8*8-1:0] STAT_PREFIX_STR[CNT] = '{CNT{"MAC"}}
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
localparam DATA_W = 16;
|
||||
localparam TX_USER_W = 1;
|
||||
localparam RX_USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1;
|
||||
|
||||
logic xcvr_ctrl_clk;
|
||||
logic xcvr_ctrl_rst;
|
||||
|
||||
// transceiver control
|
||||
taxi_apb_if #(
|
||||
.ADDR_W(24),
|
||||
.DATA_W(16)
|
||||
) s_apb_ctrl();
|
||||
|
||||
logic xcvr_gtpowergood_out;
|
||||
logic xcvr_gtrefclk00_in;
|
||||
logic xcvr_qpll0pd_in;
|
||||
logic xcvr_qpll0reset_in;
|
||||
logic [2:0] xcvr_qpll0pcierate_in;
|
||||
logic xcvr_qpll0lock_out;
|
||||
logic xcvr_qpll0clk_out;
|
||||
logic xcvr_qpll0refclk_out;
|
||||
logic xcvr_gtrefclk01_in;
|
||||
logic xcvr_qpll1pd_in;
|
||||
logic xcvr_qpll1reset_in;
|
||||
logic [2:0] xcvr_qpll1pcierate_in;
|
||||
logic xcvr_qpll1lock_out;
|
||||
logic xcvr_qpll1clk_out;
|
||||
logic xcvr_qpll1refclk_out;
|
||||
|
||||
logic xcvr_txp[CNT];
|
||||
logic xcvr_txn[CNT];
|
||||
logic xcvr_rxp[CNT];
|
||||
logic xcvr_rxn[CNT];
|
||||
|
||||
logic rx_clk[CNT];
|
||||
logic rx_rst_in[CNT];
|
||||
logic rx_rst_out[CNT];
|
||||
logic tx_clk[CNT];
|
||||
logic tx_rst_in[CNT];
|
||||
logic tx_rst_out[CNT];
|
||||
|
||||
taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(TX_USER_W), .ID_EN(1), .ID_W(TX_TAG_W)) s_axis_tx[CNT]();
|
||||
taxi_axis_if #(.DATA_W(PTP_TS_W), .KEEP_W(1), .ID_EN(1), .ID_W(TX_TAG_W)) m_axis_tx_cpl[CNT]();
|
||||
taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(RX_USER_W)) m_axis_rx[CNT]();
|
||||
|
||||
logic ptp_clk;
|
||||
logic ptp_rst;
|
||||
logic ptp_sample_clk;
|
||||
logic ptp_td_sdi;
|
||||
logic [PTP_TS_W-1:0] tx_ptp_ts_in[CNT];
|
||||
logic [PTP_TS_W-1:0] tx_ptp_ts_out[CNT];
|
||||
logic tx_ptp_ts_step_out[CNT];
|
||||
logic tx_ptp_locked[CNT];
|
||||
logic [PTP_TS_W-1:0] rx_ptp_ts_in[CNT];
|
||||
logic [PTP_TS_W-1:0] rx_ptp_ts_out[CNT];
|
||||
logic rx_ptp_ts_step_out[CNT];
|
||||
logic rx_ptp_locked[CNT];
|
||||
|
||||
logic tx_lfc_req[CNT];
|
||||
logic tx_lfc_resend[CNT];
|
||||
logic rx_lfc_en[CNT];
|
||||
logic rx_lfc_req[CNT];
|
||||
logic rx_lfc_ack[CNT];
|
||||
|
||||
logic [7:0] tx_pfc_req[CNT];
|
||||
logic tx_pfc_resend[CNT];
|
||||
logic [7:0] rx_pfc_en[CNT];
|
||||
logic [7:0] rx_pfc_req[CNT];
|
||||
logic [7:0] rx_pfc_ack[CNT];
|
||||
|
||||
logic tx_lfc_pause_en[CNT];
|
||||
logic tx_pause_req[CNT];
|
||||
logic tx_pause_ack[CNT];
|
||||
|
||||
logic stat_clk;
|
||||
logic stat_rst;
|
||||
taxi_axis_if #(.DATA_W(24), .KEEP_W(1), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) m_axis_stat();
|
||||
|
||||
logic [1:0] tx_start_packet[CNT];
|
||||
logic [1:0] stat_tx_byte[CNT];
|
||||
logic [15:0] stat_tx_pkt_len[CNT];
|
||||
logic stat_tx_pkt_ucast[CNT];
|
||||
logic stat_tx_pkt_mcast[CNT];
|
||||
logic stat_tx_pkt_bcast[CNT];
|
||||
logic stat_tx_pkt_vlan[CNT];
|
||||
logic stat_tx_pkt_good[CNT];
|
||||
logic stat_tx_pkt_bad[CNT];
|
||||
logic stat_tx_pad_frame[CNT];
|
||||
logic stat_tx_err_oversize[CNT];
|
||||
logic stat_tx_err_user[CNT];
|
||||
logic stat_tx_err_underflow[CNT];
|
||||
logic [1:0] rx_start_packet[CNT];
|
||||
logic [4:0] rx_error_count[CNT];
|
||||
logic rx_block_lock[CNT];
|
||||
logic rx_high_ber[CNT];
|
||||
logic rx_status[CNT];
|
||||
logic [1:0] stat_rx_byte[CNT];
|
||||
logic [15:0] stat_rx_pkt_len[CNT];
|
||||
logic stat_rx_pkt_fragment[CNT];
|
||||
logic stat_rx_pkt_jabber[CNT];
|
||||
logic stat_rx_pkt_ucast[CNT];
|
||||
logic stat_rx_pkt_mcast[CNT];
|
||||
logic stat_rx_pkt_bcast[CNT];
|
||||
logic stat_rx_pkt_vlan[CNT];
|
||||
logic stat_rx_pkt_good[CNT];
|
||||
logic stat_rx_pkt_bad[CNT];
|
||||
logic stat_rx_err_oversize[CNT];
|
||||
logic stat_rx_err_bad_fcs[CNT];
|
||||
logic stat_rx_err_bad_block[CNT];
|
||||
logic stat_rx_err_framing[CNT];
|
||||
logic stat_rx_err_preamble[CNT];
|
||||
logic stat_rx_fifo_drop[CNT];
|
||||
logic stat_tx_mcf[CNT];
|
||||
logic stat_rx_mcf[CNT];
|
||||
logic stat_tx_lfc_pkt[CNT];
|
||||
logic stat_tx_lfc_xon[CNT];
|
||||
logic stat_tx_lfc_xoff[CNT];
|
||||
logic stat_tx_lfc_paused[CNT];
|
||||
logic stat_tx_pfc_pkt[CNT];
|
||||
logic [7:0] stat_tx_pfc_xon[CNT];
|
||||
logic [7:0] stat_tx_pfc_xoff[CNT];
|
||||
logic [7:0] stat_tx_pfc_paused[CNT];
|
||||
logic stat_rx_lfc_pkt[CNT];
|
||||
logic stat_rx_lfc_xon[CNT];
|
||||
logic stat_rx_lfc_xoff[CNT];
|
||||
logic stat_rx_lfc_paused[CNT];
|
||||
logic stat_rx_pfc_pkt[CNT];
|
||||
logic [7:0] stat_rx_pfc_xon[CNT];
|
||||
logic [7:0] stat_rx_pfc_xoff[CNT];
|
||||
logic [7:0] stat_rx_pfc_paused[CNT];
|
||||
|
||||
logic cfg_tx_pad_en[CNT];
|
||||
logic [7:0] cfg_tx_min_pkt_len[CNT];
|
||||
logic [15:0] cfg_tx_max_pkt_len[CNT];
|
||||
logic [7:0] cfg_tx_ifg[CNT];
|
||||
logic cfg_tx_enable[CNT];
|
||||
logic [15:0] cfg_rx_max_pkt_len[CNT];
|
||||
logic cfg_rx_enable[CNT];
|
||||
logic cfg_tx_prbs31_enable[CNT];
|
||||
logic cfg_rx_prbs31_enable[CNT];
|
||||
logic [47:0] cfg_mcf_rx_eth_dst_mcast[CNT];
|
||||
logic cfg_mcf_rx_check_eth_dst_mcast[CNT];
|
||||
logic [47:0] cfg_mcf_rx_eth_dst_ucast[CNT];
|
||||
logic cfg_mcf_rx_check_eth_dst_ucast[CNT];
|
||||
logic [47:0] cfg_mcf_rx_eth_src[CNT];
|
||||
logic cfg_mcf_rx_check_eth_src[CNT];
|
||||
logic [15:0] cfg_mcf_rx_eth_type[CNT];
|
||||
logic [15:0] cfg_mcf_rx_opcode_lfc[CNT];
|
||||
logic cfg_mcf_rx_check_opcode_lfc[CNT];
|
||||
logic [15:0] cfg_mcf_rx_opcode_pfc[CNT];
|
||||
logic cfg_mcf_rx_check_opcode_pfc[CNT];
|
||||
logic cfg_mcf_rx_forward[CNT];
|
||||
logic cfg_mcf_rx_enable[CNT];
|
||||
logic [47:0] cfg_tx_lfc_eth_dst[CNT];
|
||||
logic [47:0] cfg_tx_lfc_eth_src[CNT];
|
||||
logic [15:0] cfg_tx_lfc_eth_type[CNT];
|
||||
logic [15:0] cfg_tx_lfc_opcode[CNT];
|
||||
logic cfg_tx_lfc_en[CNT];
|
||||
logic [15:0] cfg_tx_lfc_quanta[CNT];
|
||||
logic [15:0] cfg_tx_lfc_refresh[CNT];
|
||||
logic [47:0] cfg_tx_pfc_eth_dst[CNT];
|
||||
logic [47:0] cfg_tx_pfc_eth_src[CNT];
|
||||
logic [15:0] cfg_tx_pfc_eth_type[CNT];
|
||||
logic [15:0] cfg_tx_pfc_opcode[CNT];
|
||||
logic cfg_tx_pfc_en[CNT];
|
||||
logic [15:0] cfg_tx_pfc_quanta[CNT][8];
|
||||
logic [15:0] cfg_tx_pfc_refresh[CNT][8];
|
||||
logic [15:0] cfg_rx_lfc_opcode[CNT];
|
||||
logic cfg_rx_lfc_en[CNT];
|
||||
logic [15:0] cfg_rx_pfc_opcode[CNT];
|
||||
logic cfg_rx_pfc_en[CNT];
|
||||
|
||||
taxi_eth_mac_1g_basex_us #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
.CNT(CNT),
|
||||
.CFG_LOW_LATENCY(CFG_LOW_LATENCY),
|
||||
.GT_TYPE(GT_TYPE),
|
||||
.QPLL0_PD(QPLL0_PD),
|
||||
.QPLL1_PD(QPLL1_PD),
|
||||
.QPLL0_EXT_CTRL(QPLL0_EXT_CTRL),
|
||||
.QPLL1_EXT_CTRL(QPLL1_EXT_CTRL),
|
||||
.GT_TX_PD(GT_TX_PD),
|
||||
.GT_TX_QPLL_SEL(GT_TX_QPLL_SEL),
|
||||
.GT_TX_POLARITY(GT_TX_POLARITY),
|
||||
.GT_TX_ELECIDLE(GT_TX_ELECIDLE),
|
||||
.GT_TX_INHIBIT(GT_TX_INHIBIT),
|
||||
.GT_TX_DIFFCTRL(GT_TX_DIFFCTRL),
|
||||
.GT_TX_MAINCURSOR(GT_TX_MAINCURSOR),
|
||||
.GT_TX_POSTCURSOR(GT_TX_POSTCURSOR),
|
||||
.GT_TX_PRECURSOR(GT_TX_PRECURSOR),
|
||||
.GT_RX_PD(GT_RX_PD),
|
||||
.GT_RX_QPLL_SEL(GT_RX_QPLL_SEL),
|
||||
.GT_RX_LPM_EN(GT_RX_LPM_EN),
|
||||
.GT_RX_POLARITY(GT_RX_POLARITY),
|
||||
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
|
||||
.DIC_EN(DIC_EN),
|
||||
.PTP_TS_EN(PTP_TS_EN),
|
||||
.PTP_TD_EN(PTP_TD_EN),
|
||||
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
|
||||
.PTP_TS_W(PTP_TS_W),
|
||||
.PTP_TD_SDI_PIPELINE(PTP_TD_SDI_PIPELINE),
|
||||
.PRBS31_EN(PRBS31_EN),
|
||||
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
|
||||
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
|
||||
.COUNT_125US(COUNT_125US),
|
||||
.PFC_EN(PFC_EN),
|
||||
.PAUSE_EN(PAUSE_EN),
|
||||
.STAT_EN(STAT_EN),
|
||||
.STAT_TX_LEVEL(STAT_TX_LEVEL),
|
||||
.STAT_RX_LEVEL(STAT_RX_LEVEL),
|
||||
.STAT_ID_BASE(STAT_ID_BASE),
|
||||
.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD),
|
||||
.STAT_STR_EN(STAT_STR_EN),
|
||||
.STAT_PREFIX_STR(STAT_PREFIX_STR)
|
||||
)
|
||||
uut (
|
||||
.xcvr_ctrl_clk(xcvr_ctrl_clk),
|
||||
.xcvr_ctrl_rst(xcvr_ctrl_rst),
|
||||
|
||||
/*
|
||||
* Transceiver control
|
||||
*/
|
||||
.s_apb_ctrl(s_apb_ctrl),
|
||||
|
||||
/*
|
||||
* Common
|
||||
*/
|
||||
.xcvr_gtpowergood_out(xcvr_gtpowergood_out),
|
||||
.xcvr_gtrefclk00_in(xcvr_gtrefclk00_in),
|
||||
.xcvr_qpll0pd_in(xcvr_qpll0pd_in),
|
||||
.xcvr_qpll0reset_in(xcvr_qpll0reset_in),
|
||||
.xcvr_qpll0pcierate_in(xcvr_qpll0pcierate_in),
|
||||
.xcvr_qpll0lock_out(xcvr_qpll0lock_out),
|
||||
.xcvr_qpll0clk_out(xcvr_qpll0clk_out),
|
||||
.xcvr_qpll0refclk_out(xcvr_qpll0refclk_out),
|
||||
.xcvr_gtrefclk01_in(xcvr_gtrefclk01_in),
|
||||
.xcvr_qpll1pd_in(xcvr_qpll1pd_in),
|
||||
.xcvr_qpll1reset_in(xcvr_qpll1reset_in),
|
||||
.xcvr_qpll1pcierate_in(xcvr_qpll1pcierate_in),
|
||||
.xcvr_qpll1lock_out(xcvr_qpll1lock_out),
|
||||
.xcvr_qpll1clk_out(xcvr_qpll1clk_out),
|
||||
.xcvr_qpll1refclk_out(xcvr_qpll1refclk_out),
|
||||
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp(xcvr_txp),
|
||||
.xcvr_txn(xcvr_txn),
|
||||
.xcvr_rxp(xcvr_rxp),
|
||||
.xcvr_rxn(xcvr_rxn),
|
||||
|
||||
/*
|
||||
* MAC clocks
|
||||
*/
|
||||
.rx_clk(rx_clk),
|
||||
.rx_rst_in(rx_rst_in),
|
||||
.rx_rst_out(rx_rst_out),
|
||||
.tx_clk(tx_clk),
|
||||
.tx_rst_in(tx_rst_in),
|
||||
.tx_rst_out(tx_rst_out),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(s_axis_tx),
|
||||
.m_axis_tx_cpl(m_axis_tx_cpl),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(m_axis_rx),
|
||||
|
||||
/*
|
||||
* PTP
|
||||
*/
|
||||
.ptp_clk(ptp_clk),
|
||||
.ptp_rst(ptp_rst),
|
||||
.ptp_sample_clk(ptp_sample_clk),
|
||||
.ptp_td_sdi(ptp_td_sdi),
|
||||
.tx_ptp_ts_in(tx_ptp_ts_in),
|
||||
.tx_ptp_ts_out(tx_ptp_ts_out),
|
||||
.tx_ptp_ts_step_out(tx_ptp_ts_step_out),
|
||||
.tx_ptp_locked(tx_ptp_locked),
|
||||
.rx_ptp_ts_in(rx_ptp_ts_in),
|
||||
.rx_ptp_ts_out(rx_ptp_ts_out),
|
||||
.rx_ptp_ts_step_out(rx_ptp_ts_step_out),
|
||||
.rx_ptp_locked(rx_ptp_locked),
|
||||
|
||||
/*
|
||||
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
|
||||
*/
|
||||
.tx_lfc_req(tx_lfc_req),
|
||||
.tx_lfc_resend(tx_lfc_resend),
|
||||
.rx_lfc_en(rx_lfc_en),
|
||||
.rx_lfc_req(rx_lfc_req),
|
||||
.rx_lfc_ack(rx_lfc_ack),
|
||||
|
||||
/*
|
||||
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
|
||||
*/
|
||||
.tx_pfc_req(tx_pfc_req),
|
||||
.tx_pfc_resend(tx_pfc_resend),
|
||||
.rx_pfc_en(rx_pfc_en),
|
||||
.rx_pfc_req(rx_pfc_req),
|
||||
.rx_pfc_ack(rx_pfc_ack),
|
||||
|
||||
/*
|
||||
* Pause interface
|
||||
*/
|
||||
.tx_lfc_pause_en(tx_lfc_pause_en),
|
||||
.tx_pause_req(tx_pause_req),
|
||||
.tx_pause_ack(tx_pause_ack),
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
.stat_clk(stat_clk),
|
||||
.stat_rst(stat_rst),
|
||||
.m_axis_stat(m_axis_stat),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_start_packet(tx_start_packet),
|
||||
.stat_tx_byte(stat_tx_byte),
|
||||
.stat_tx_pkt_len(stat_tx_pkt_len),
|
||||
.stat_tx_pkt_ucast(stat_tx_pkt_ucast),
|
||||
.stat_tx_pkt_mcast(stat_tx_pkt_mcast),
|
||||
.stat_tx_pkt_bcast(stat_tx_pkt_bcast),
|
||||
.stat_tx_pkt_vlan(stat_tx_pkt_vlan),
|
||||
.stat_tx_pkt_good(stat_tx_pkt_good),
|
||||
.stat_tx_pkt_bad(stat_tx_pkt_bad),
|
||||
.stat_tx_pad_frame(stat_tx_pad_frame),
|
||||
.stat_tx_err_oversize(stat_tx_err_oversize),
|
||||
.stat_tx_err_user(stat_tx_err_user),
|
||||
.stat_tx_err_underflow(stat_tx_err_underflow),
|
||||
.rx_start_packet(rx_start_packet),
|
||||
.rx_error_count(rx_error_count),
|
||||
.rx_block_lock(rx_block_lock),
|
||||
.rx_high_ber(rx_high_ber),
|
||||
.rx_status(rx_status),
|
||||
.stat_rx_byte(stat_rx_byte),
|
||||
.stat_rx_pkt_len(stat_rx_pkt_len),
|
||||
.stat_rx_pkt_fragment(stat_rx_pkt_fragment),
|
||||
.stat_rx_pkt_jabber(stat_rx_pkt_jabber),
|
||||
.stat_rx_pkt_ucast(stat_rx_pkt_ucast),
|
||||
.stat_rx_pkt_mcast(stat_rx_pkt_mcast),
|
||||
.stat_rx_pkt_bcast(stat_rx_pkt_bcast),
|
||||
.stat_rx_pkt_vlan(stat_rx_pkt_vlan),
|
||||
.stat_rx_pkt_good(stat_rx_pkt_good),
|
||||
.stat_rx_pkt_bad(stat_rx_pkt_bad),
|
||||
.stat_rx_err_oversize(stat_rx_err_oversize),
|
||||
.stat_rx_err_bad_fcs(stat_rx_err_bad_fcs),
|
||||
.stat_rx_err_bad_block(stat_rx_err_bad_block),
|
||||
.stat_rx_err_framing(stat_rx_err_framing),
|
||||
.stat_rx_err_preamble(stat_rx_err_preamble),
|
||||
.stat_rx_fifo_drop(stat_rx_fifo_drop),
|
||||
.stat_tx_mcf(stat_tx_mcf),
|
||||
.stat_rx_mcf(stat_rx_mcf),
|
||||
.stat_tx_lfc_pkt(stat_tx_lfc_pkt),
|
||||
.stat_tx_lfc_xon(stat_tx_lfc_xon),
|
||||
.stat_tx_lfc_xoff(stat_tx_lfc_xoff),
|
||||
.stat_tx_lfc_paused(stat_tx_lfc_paused),
|
||||
.stat_tx_pfc_pkt(stat_tx_pfc_pkt),
|
||||
.stat_tx_pfc_xon(stat_tx_pfc_xon),
|
||||
.stat_tx_pfc_xoff(stat_tx_pfc_xoff),
|
||||
.stat_tx_pfc_paused(stat_tx_pfc_paused),
|
||||
.stat_rx_lfc_pkt(stat_rx_lfc_pkt),
|
||||
.stat_rx_lfc_xon(stat_rx_lfc_xon),
|
||||
.stat_rx_lfc_xoff(stat_rx_lfc_xoff),
|
||||
.stat_rx_lfc_paused(stat_rx_lfc_paused),
|
||||
.stat_rx_pfc_pkt(stat_rx_pfc_pkt),
|
||||
.stat_rx_pfc_xon(stat_rx_pfc_xon),
|
||||
.stat_rx_pfc_xoff(stat_rx_pfc_xoff),
|
||||
.stat_rx_pfc_paused(stat_rx_pfc_paused),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_tx_pad_en(cfg_tx_pad_en),
|
||||
.cfg_tx_min_pkt_len(cfg_tx_min_pkt_len),
|
||||
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
|
||||
.cfg_tx_ifg(cfg_tx_ifg),
|
||||
.cfg_tx_enable(cfg_tx_enable),
|
||||
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
|
||||
.cfg_rx_enable(cfg_rx_enable),
|
||||
.cfg_tx_prbs31_enable(cfg_tx_prbs31_enable),
|
||||
.cfg_rx_prbs31_enable(cfg_rx_prbs31_enable),
|
||||
.cfg_mcf_rx_eth_dst_mcast(cfg_mcf_rx_eth_dst_mcast),
|
||||
.cfg_mcf_rx_check_eth_dst_mcast(cfg_mcf_rx_check_eth_dst_mcast),
|
||||
.cfg_mcf_rx_eth_dst_ucast(cfg_mcf_rx_eth_dst_ucast),
|
||||
.cfg_mcf_rx_check_eth_dst_ucast(cfg_mcf_rx_check_eth_dst_ucast),
|
||||
.cfg_mcf_rx_eth_src(cfg_mcf_rx_eth_src),
|
||||
.cfg_mcf_rx_check_eth_src(cfg_mcf_rx_check_eth_src),
|
||||
.cfg_mcf_rx_eth_type(cfg_mcf_rx_eth_type),
|
||||
.cfg_mcf_rx_opcode_lfc(cfg_mcf_rx_opcode_lfc),
|
||||
.cfg_mcf_rx_check_opcode_lfc(cfg_mcf_rx_check_opcode_lfc),
|
||||
.cfg_mcf_rx_opcode_pfc(cfg_mcf_rx_opcode_pfc),
|
||||
.cfg_mcf_rx_check_opcode_pfc(cfg_mcf_rx_check_opcode_pfc),
|
||||
.cfg_mcf_rx_forward(cfg_mcf_rx_forward),
|
||||
.cfg_mcf_rx_enable(cfg_mcf_rx_enable),
|
||||
.cfg_tx_lfc_eth_dst(cfg_tx_lfc_eth_dst),
|
||||
.cfg_tx_lfc_eth_src(cfg_tx_lfc_eth_src),
|
||||
.cfg_tx_lfc_eth_type(cfg_tx_lfc_eth_type),
|
||||
.cfg_tx_lfc_opcode(cfg_tx_lfc_opcode),
|
||||
.cfg_tx_lfc_en(cfg_tx_lfc_en),
|
||||
.cfg_tx_lfc_quanta(cfg_tx_lfc_quanta),
|
||||
.cfg_tx_lfc_refresh(cfg_tx_lfc_refresh),
|
||||
.cfg_tx_pfc_eth_dst(cfg_tx_pfc_eth_dst),
|
||||
.cfg_tx_pfc_eth_src(cfg_tx_pfc_eth_src),
|
||||
.cfg_tx_pfc_eth_type(cfg_tx_pfc_eth_type),
|
||||
.cfg_tx_pfc_opcode(cfg_tx_pfc_opcode),
|
||||
.cfg_tx_pfc_en(cfg_tx_pfc_en),
|
||||
.cfg_tx_pfc_quanta(cfg_tx_pfc_quanta),
|
||||
.cfg_tx_pfc_refresh(cfg_tx_pfc_refresh),
|
||||
.cfg_rx_lfc_opcode(cfg_rx_lfc_opcode),
|
||||
.cfg_rx_lfc_en(cfg_rx_lfc_en),
|
||||
.cfg_rx_pfc_opcode(cfg_rx_pfc_opcode),
|
||||
.cfg_rx_pfc_en(cfg_rx_pfc_en)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user