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eth: Add 10G Ethernet MAC module with FIFOs and testbench

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-02-13 13:47:54 -08:00
parent d76e810033
commit 90650aee69
5 changed files with 1109 additions and 0 deletions
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rtl/eth/taxi_eth_mac_10g_fifo.f Normal file
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taxi_eth_mac_10g_fifo.sv
taxi_eth_mac_10g.f
../ptp/taxi_ptp_clock_cdc.sv
../axis/taxi_axis_async_fifo_adapter.f

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rtl/eth/taxi_eth_mac_10g_fifo.sv Normal file
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// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2015-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet MAC with TX and RX FIFOs
*/
module taxi_eth_mac_10g_fifo #
(
parameter DATA_W = 64,
parameter CTRL_W = (DATA_W/8),
parameter logic PADDING_EN = 1'b1,
parameter logic DIC_EN = 1'b1,
parameter MIN_FRAME_LEN = 64,
parameter logic PTP_TS_EN = 1'b0,
parameter logic PTP_TS_FMT_TOD = 1'b1,
parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64,
parameter TX_FIFO_DEPTH = 4096,
parameter TX_FIFO_RAM_PIPELINE = 1,
parameter logic TX_FRAME_FIFO = 1'b1,
parameter logic TX_DROP_OVERSIZE_FRAME = TX_FRAME_FIFO,
parameter logic TX_DROP_BAD_FRAME = TX_DROP_OVERSIZE_FRAME,
parameter logic TX_DROP_WHEN_FULL = 1'b0,
parameter TX_CPL_FIFO_DEPTH = 64,
parameter RX_FIFO_DEPTH = 4096,
parameter RX_FIFO_RAM_PIPELINE = 1,
parameter logic RX_FRAME_FIFO = 1'b1,
parameter logic RX_DROP_OVERSIZE_FRAME = RX_FRAME_FIFO,
parameter logic RX_DROP_BAD_FRAME = RX_DROP_OVERSIZE_FRAME,
parameter logic RX_DROP_WHEN_FULL = RX_DROP_OVERSIZE_FRAME
)
(
input wire logic rx_clk,
input wire logic rx_rst,
input wire logic tx_clk,
input wire logic tx_rst,
input wire logic logic_clk,
input wire logic logic_rst,
input wire logic ptp_sample_clk,
/*
* AXI4-Stream input (sink)
*/
taxi_axis_if.snk s_axis_tx,
taxi_axis_if.src m_axis_tx_cpl,
/*
* AXI4-Stream output (source)
*/
taxi_axis_if.src m_axis_rx,
/*
* XGMII interface
*/
input wire logic [DATA_W-1:0] xgmii_rxd,
input wire logic [CTRL_W-1:0] xgmii_rxc,
output wire logic [DATA_W-1:0] xgmii_txd,
output wire logic [CTRL_W-1:0] xgmii_txc,
/*
* Status
*/
output wire logic tx_error_underflow,
output wire logic tx_fifo_overflow,
output wire logic tx_fifo_bad_frame,
output wire logic tx_fifo_good_frame,
output wire logic rx_error_bad_frame,
output wire logic rx_error_bad_fcs,
output wire logic rx_fifo_overflow,
output wire logic rx_fifo_bad_frame,
output wire logic rx_fifo_good_frame,
/*
* PTP clock
*/
input wire logic [PTP_TS_W-1:0] ptp_ts = '0,
input wire logic ptp_ts_step = 1'b0,
/*
* Configuration
*/
input wire logic [7:0] cfg_ifg = 8'd12,
input wire logic cfg_tx_enable = 1'b1,
input wire logic cfg_rx_enable = 1'b1
);
localparam KEEP_W = DATA_W/8;
localparam TX_USER_W = 1;
localparam RX_USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1;
localparam TX_TAG_W = s_axis_tx.ID_W;
taxi_axis_if #(.DATA_W(DATA_W), .KEEP_W(KEEP_W), .USER_EN(1), .USER_W(TX_USER_W), .ID_EN(1), .ID_W(TX_TAG_W)) axis_tx_int();
taxi_axis_if #(.DATA_W(PTP_TS_W), .KEEP_W(1), .ID_EN(1), .ID_W(TX_TAG_W)) axis_tx_cpl_int();
taxi_axis_if #(.DATA_W(DATA_W), .KEEP_W(KEEP_W), .USER_EN(1), .USER_W(RX_USER_W)) axis_rx_int();
wire [PTP_TS_W-1:0] tx_ptp_ts;
wire [PTP_TS_W-1:0] rx_ptp_ts;
wire tx_ptp_locked;
wire rx_ptp_locked;
// synchronize MAC status signals into logic clock domain
wire tx_error_underflow_int;
logic [0:0] tx_sync_reg_1 = '0;
logic [0:0] tx_sync_reg_2 = '0;
logic [0:0] tx_sync_reg_3 = '0;
logic [0:0] tx_sync_reg_4 = '0;
assign tx_error_underflow = tx_sync_reg_3[0] ^ tx_sync_reg_4[0];
always_ff @(posedge tx_clk or posedge tx_rst) begin
if (tx_rst) begin
tx_sync_reg_1 <= '0;
end else begin
tx_sync_reg_1 <= tx_sync_reg_1 ^ {tx_error_underflow_int};
end
end
always_ff @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
tx_sync_reg_2 <= '0;
tx_sync_reg_3 <= '0;
tx_sync_reg_4 <= '0;
end else begin
tx_sync_reg_2 <= tx_sync_reg_1;
tx_sync_reg_3 <= tx_sync_reg_2;
tx_sync_reg_4 <= tx_sync_reg_3;
end
end
wire rx_error_bad_frame_int;
wire rx_error_bad_fcs_int;
logic [1:0] rx_sync_reg_1 = '0;
logic [1:0] rx_sync_reg_2 = '0;
logic [1:0] rx_sync_reg_3 = '0;
logic [1:0] rx_sync_reg_4 = '0;
assign rx_error_bad_frame = rx_sync_reg_3[0] ^ rx_sync_reg_4[0];
assign rx_error_bad_fcs = rx_sync_reg_3[1] ^ rx_sync_reg_4[1];
always_ff @(posedge rx_clk or posedge rx_rst) begin
if (rx_rst) begin
rx_sync_reg_1 <= '0;
end else begin
rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_error_bad_fcs_int, rx_error_bad_frame_int};
end
end
always_ff @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
rx_sync_reg_2 <= '0;
rx_sync_reg_3 <= '0;
rx_sync_reg_4 <= '0;
end else begin
rx_sync_reg_2 <= rx_sync_reg_1;
rx_sync_reg_3 <= rx_sync_reg_2;
rx_sync_reg_4 <= rx_sync_reg_3;
end
end
// PTP timestamping
generate
if (PTP_TS_EN) begin : ptp
taxi_ptp_clock_cdc #(
.TS_W(PTP_TS_W),
.NS_W(6)
)
tx_ptp_cdc (
.input_clk(logic_clk),
.input_rst(logic_rst),
.output_clk(tx_clk),
.output_rst(tx_rst),
.sample_clk(ptp_sample_clk),
.input_ts(ptp_ts),
.input_ts_step(ptp_ts_step),
.output_ts(tx_ptp_ts),
.output_ts_step(),
.output_pps(),
.output_pps_str(),
.locked(tx_ptp_locked)
);
taxi_ptp_clock_cdc #(
.TS_W(PTP_TS_W),
.NS_W(6)
)
rx_ptp_cdc (
.input_clk(logic_clk),
.input_rst(logic_rst),
.output_clk(rx_clk),
.output_rst(rx_rst),
.sample_clk(ptp_sample_clk),
.input_ts(ptp_ts),
.input_ts_step(ptp_ts_step),
.output_ts(rx_ptp_ts),
.output_ts_step(),
.output_pps(),
.output_pps_str(),
.locked(rx_ptp_locked)
);
end else begin
assign tx_ptp_ts = '0;
assign rx_ptp_ts = '0;
assign tx_ptp_locked = 1'b0;
assign rx_ptp_locked = 1'b0;
end
endgenerate
taxi_eth_mac_10g #(
.DATA_W(DATA_W),
.CTRL_W(CTRL_W),
.PADDING_EN(PADDING_EN),
.DIC_EN(DIC_EN),
.MIN_FRAME_LEN(MIN_FRAME_LEN),
.PTP_TS_EN(PTP_TS_EN),
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
.PTP_TS_W(PTP_TS_W),
.PFC_EN(1'b0),
.PAUSE_EN(1'b0)
)
eth_mac_10g_inst (
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
/*
* Transmit interface (AXI stream)
*/
.s_axis_tx(axis_tx_int),
.m_axis_tx_cpl(axis_tx_cpl_int),
/*
* Receive interface (AXI stream)
*/
.m_axis_rx(axis_rx_int),
/*
* XGMII interface
*/
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
/*
* PTP
*/
.tx_ptp_ts(tx_ptp_ts),
.rx_ptp_ts(rx_ptp_ts),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
.tx_lfc_req(0),
.tx_lfc_resend(0),
.rx_lfc_en(0),
.rx_lfc_req(),
.rx_lfc_ack(0),
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req(0),
.tx_pfc_resend(0),
.rx_pfc_en(0),
.rx_pfc_req(),
.rx_pfc_ack(0),
/*
* Pause interface
*/
.tx_lfc_pause_en(0),
.tx_pause_req(0),
.tx_pause_ack(),
/*
* Status
*/
.tx_start_packet(),
.tx_error_underflow(tx_error_underflow_int),
.rx_start_packet(),
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.stat_tx_mcf(),
.stat_rx_mcf(),
.stat_tx_lfc_pkt(),
.stat_tx_lfc_xon(),
.stat_tx_lfc_xoff(),
.stat_tx_lfc_paused(),
.stat_tx_pfc_pkt(),
.stat_tx_pfc_xon(),
.stat_tx_pfc_xoff(),
.stat_tx_pfc_paused(),
.stat_rx_lfc_pkt(),
.stat_rx_lfc_xon(),
.stat_rx_lfc_xoff(),
.stat_rx_lfc_paused(),
.stat_rx_pfc_pkt(),
.stat_rx_pfc_xon(),
.stat_rx_pfc_xoff(),
.stat_rx_pfc_paused(),
/*
* Configuration
*/
.cfg_ifg(cfg_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_enable(cfg_rx_enable),
.cfg_mcf_rx_eth_dst_mcast(0),
.cfg_mcf_rx_check_eth_dst_mcast(0),
.cfg_mcf_rx_eth_dst_ucast(0),
.cfg_mcf_rx_check_eth_dst_ucast(0),
.cfg_mcf_rx_eth_src(0),
.cfg_mcf_rx_check_eth_src(0),
.cfg_mcf_rx_eth_type(0),
.cfg_mcf_rx_opcode_lfc(0),
.cfg_mcf_rx_check_opcode_lfc(0),
.cfg_mcf_rx_opcode_pfc(0),
.cfg_mcf_rx_check_opcode_pfc(0),
.cfg_mcf_rx_forward(0),
.cfg_mcf_rx_enable(0),
.cfg_tx_lfc_eth_dst(0),
.cfg_tx_lfc_eth_src(0),
.cfg_tx_lfc_eth_type(0),
.cfg_tx_lfc_opcode(0),
.cfg_tx_lfc_en(0),
.cfg_tx_lfc_quanta(0),
.cfg_tx_lfc_refresh(0),
.cfg_tx_pfc_eth_dst(0),
.cfg_tx_pfc_eth_src(0),
.cfg_tx_pfc_eth_type(0),
.cfg_tx_pfc_opcode(0),
.cfg_tx_pfc_en(0),
.cfg_tx_pfc_quanta(0),
.cfg_tx_pfc_refresh(0),
.cfg_rx_lfc_opcode(0),
.cfg_rx_lfc_en(0),
.cfg_rx_pfc_opcode(0),
.cfg_rx_pfc_en(0)
);
taxi_axis_async_fifo_adapter #(
.DEPTH(TX_FIFO_DEPTH),
.RAM_PIPELINE(TX_FIFO_RAM_PIPELINE),
.FRAME_FIFO(TX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_OVERSIZE_FRAME(TX_DROP_OVERSIZE_FRAME),
.DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(TX_DROP_WHEN_FULL)
)
tx_fifo (
/*
* AXI4-Stream input (sink)
*/
.s_clk(logic_clk),
.s_rst(logic_rst),
.s_axis(s_axis_tx),
/*
* AXI4-Stream output (source)
*/
.m_clk(tx_clk),
.m_rst(tx_rst),
.m_axis(axis_tx_int),
/*
* Pause
*/
.s_pause_req(1'b0),
.s_pause_ack(),
.m_pause_req(1'b0),
.m_pause_ack(),
/*
* Status
*/
.s_status_depth(),
.s_status_depth_commit(),
.s_status_overflow(tx_fifo_overflow),
.s_status_bad_frame(tx_fifo_bad_frame),
.s_status_good_frame(tx_fifo_good_frame),
.m_status_depth(),
.m_status_depth_commit(),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
taxi_axis_async_fifo #(
.DEPTH(TX_CPL_FIFO_DEPTH),
.FRAME_FIFO(1'b0)
)
tx_cpl_fifo (
/*
* AXI4-Stream input (sink)
*/
.s_clk(tx_clk),
.s_rst(tx_rst),
.s_axis(axis_tx_cpl_int),
/*
* AXI4-Stream output (source)
*/
.m_clk(logic_clk),
.m_rst(logic_rst),
.m_axis(m_axis_tx_cpl),
/*
* Pause
*/
.s_pause_req(1'b0),
.s_pause_ack(),
.m_pause_req(1'b0),
.m_pause_ack(),
/*
* Status
*/
.s_status_depth(),
.s_status_depth_commit(),
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_depth(),
.m_status_depth_commit(),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
taxi_axis_async_fifo_adapter #(
.DEPTH(RX_FIFO_DEPTH),
.RAM_PIPELINE(RX_FIFO_RAM_PIPELINE),
.FRAME_FIFO(RX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_OVERSIZE_FRAME(RX_DROP_OVERSIZE_FRAME),
.DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
)
rx_fifo (
/*
* AXI4-Stream input (sink)
*/
.s_clk(rx_clk),
.s_rst(rx_rst),
.s_axis(axis_rx_int),
/*
* AXI4-Stream output (source)
*/
.m_clk(logic_clk),
.m_rst(logic_rst),
.m_axis(m_axis_rx),
/*
* Pause
*/
.s_pause_req(1'b0),
.s_pause_ack(),
.m_pause_req(1'b0),
.m_pause_ack(),
/*
* Status
*/
.s_status_depth(),
.s_status_depth_commit(),
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_depth(),
.m_status_depth_commit(),
.m_status_overflow(rx_fifo_overflow),
.m_status_bad_frame(rx_fifo_bad_frame),
.m_status_good_frame(rx_fifo_good_frame)
);
endmodule
`resetall

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tb/eth/taxi_eth_mac_10g_fifo/Makefile Normal file
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# SPDX-License-Identifier: CERN-OHL-S-2.0
#
# Copyright (c) 2020-2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
TOPLEVEL_LANG = verilog
SIM ?= verilator
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
DUT = taxi_eth_mac_10g_fifo
COCOTB_TEST_MODULES = test_$(DUT)
COCOTB_TOPLEVEL = test_$(DUT)
MODULE = $(COCOTB_TEST_MODULES)
TOPLEVEL = $(COCOTB_TOPLEVEL)
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
VERILOG_SOURCES += ../../../rtl/eth/$(DUT).f
# handle file list files
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_DATA_W := 64
export PARAM_AXIS_DATA_W := $(PARAM_DATA_W)
export PARAM_PADDING_EN := 1
export PARAM_DIC_EN := 1
export PARAM_MIN_FRAME_LEN := 64
export PARAM_PTP_TS_EN := 1
export PARAM_PTP_TS_FMT_TOD := 1
export PARAM_PTP_TS_W := $(if $(filter-out 1,$(PARAM_PTP_TS_FMT_TOD)),64,96)
export PARAM_TX_TAG_W := 16
export PARAM_TX_FIFO_DEPTH := 16384
export PARAM_TX_FIFO_RAM_PIPELINE := 1
export PARAM_TX_FRAME_FIFO := 1
export PARAM_TX_DROP_OVERSIZE_FRAME := $(PARAM_TX_FRAME_FIFO)
export PARAM_TX_DROP_BAD_FRAME := $(PARAM_TX_DROP_OVERSIZE_FRAME)
export PARAM_TX_DROP_WHEN_FULL := 0
export PARAM_TX_CPL_FIFO_DEPTH := 64
export PARAM_RX_FIFO_DEPTH := 16384
export PARAM_RX_FIFO_RAM_PIPELINE := 1
export PARAM_RX_FRAME_FIFO := 1
export PARAM_RX_DROP_OVERSIZE_FRAME := $(PARAM_RX_FRAME_FIFO)
export PARAM_RX_DROP_BAD_FRAME := $(PARAM_RX_DROP_OVERSIZE_FRAME)
export PARAM_RX_DROP_WHEN_FULL := $(PARAM_RX_DROP_OVERSIZE_FRAME)
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
else ifeq ($(SIM), verilator)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst
VERILATOR_TRACE = 1
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim

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tb/eth/taxi_eth_mac_10g_fifo/test_taxi_eth_mac_10g_fifo.py Normal file
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#!/usr/bin/env python
# SPDX-License-Identifier: CERN-OHL-S-2.0
"""
Copyright (c) 2020-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
"""
import itertools
import logging
import os
import pytest
import cocotb_test.simulator
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.utils import get_time_from_sim_steps
from cocotb.regression import TestFactory
from cocotbext.eth import XgmiiFrame, XgmiiSource, XgmiiSink, PtpClockSimTime
from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame
class TB:
def __init__(self, dut):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
if len(dut.xgmii_txd) == 64:
self.clk_period = 6.4
else:
self.clk_period = 3.2
cocotb.start_soon(Clock(dut.logic_clk, self.clk_period, units="ns").start())
cocotb.start_soon(Clock(dut.rx_clk, self.clk_period, units="ns").start())
cocotb.start_soon(Clock(dut.tx_clk, self.clk_period, units="ns").start())
cocotb.start_soon(Clock(dut.ptp_sample_clk, 9.9, units="ns").start())
self.xgmii_source = XgmiiSource(dut.xgmii_rxd, dut.xgmii_rxc, dut.rx_clk, dut.rx_rst)
self.xgmii_sink = XgmiiSink(dut.xgmii_txd, dut.xgmii_txc, dut.tx_clk, dut.tx_rst)
self.axis_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_tx), dut.logic_clk, dut.logic_rst)
self.tx_cpl_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_tx_cpl), dut.tx_clk, dut.tx_rst)
self.axis_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.logic_clk, dut.logic_rst)
self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts, clock=dut.logic_clk)
dut.ptp_ts_step.setimmediatevalue(0)
dut.cfg_ifg.setimmediatevalue(0)
dut.cfg_tx_enable.setimmediatevalue(0)
dut.cfg_rx_enable.setimmediatevalue(0)
async def reset(self):
self.dut.logic_rst.setimmediatevalue(0)
self.dut.rx_rst.setimmediatevalue(0)
self.dut.tx_rst.setimmediatevalue(0)
await RisingEdge(self.dut.logic_clk)
await RisingEdge(self.dut.logic_clk)
self.dut.logic_rst.value = 1
self.dut.rx_rst.value = 1
self.dut.tx_rst.value = 1
await RisingEdge(self.dut.logic_clk)
await RisingEdge(self.dut.logic_clk)
self.dut.logic_rst.value = 0
self.dut.rx_rst.value = 0
self.dut.tx_rst.value = 0
await RisingEdge(self.dut.logic_clk)
await RisingEdge(self.dut.logic_clk)
async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.xgmii_source.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_rx_enable.value = 1
await tb.reset()
tb.log.info("Wait for PTP CDC lock")
while not dut.uut.rx_ptp_locked.value.integer:
await RisingEdge(dut.rx_clk)
for k in range(1000):
await RisingEdge(dut.rx_clk)
test_frames = [payload_data(x) for x in payload_lengths()]
tx_frames = []
for test_data in test_frames:
test_frame = XgmiiFrame.from_payload(test_data, tx_complete=tx_frames.append)
await tb.xgmii_source.send(test_frame)
for test_data in test_frames:
rx_frame = await tb.axis_sink.recv()
tx_frame = tx_frames.pop(0)
frame_error = rx_frame.tuser & 1
ptp_ts = rx_frame.tuser >> 1
ptp_ts_ns = ptp_ts / 2**16
tx_frame_sfd_ns = get_time_from_sim_steps(tx_frame.sim_time_sfd, "ns")
if tx_frame.start_lane == 4:
# start in lane 4 reports 1 full cycle delay, so subtract half clock period
tx_frame_sfd_ns -= tb.clk_period/2
tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns)
tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns)
tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns))
assert rx_frame.tdata == test_data
assert frame_error == 0
assert abs(ptp_ts_ns - tx_frame_sfd_ns - tb.clk_period) < tb.clk_period*2
assert tb.axis_sink.empty()
await RisingEdge(dut.logic_clk)
await RisingEdge(dut.logic_clk)
async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.xgmii_source.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()
tb.log.info("Wait for PTP CDC lock")
while not dut.uut.tx_ptp_locked.value.integer:
await RisingEdge(dut.tx_clk)
for k in range(1000):
await RisingEdge(dut.tx_clk)
test_frames = [payload_data(x) for x in payload_lengths()]
for test_data in test_frames:
await tb.axis_source.send(AxiStreamFrame(test_data, tid=0, tuser=0))
for test_data in test_frames:
rx_frame = await tb.xgmii_sink.recv()
tx_cpl = await tb.tx_cpl_sink.recv()
ptp_ts_ns = int(tx_cpl.tdata[0]) / 2**16
rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
if rx_frame.start_lane == 4:
# start in lane 4 reports 1 full cycle delay, so subtract half clock period
rx_frame_sfd_ns -= tb.clk_period/2
tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))
assert rx_frame.get_payload() == test_data
assert rx_frame.check_fcs()
assert rx_frame.ctrl is None
assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period) < tb.clk_period*2
assert tb.xgmii_sink.empty()
await RisingEdge(dut.logic_clk)
await RisingEdge(dut.logic_clk)
async def run_test_tx_alignment(dut, payload_data=None, ifg=12):
dic_en = int(cocotb.top.DIC_EN.value)
tb = TB(dut)
byte_width = tb.axis_source.width // 8
tb.xgmii_source.ifg = ifg
tb.dut.cfg_ifg.value = ifg
tb.dut.cfg_tx_enable.value = 1
await tb.reset()
tb.log.info("Wait for PTP CDC lock")
while not dut.uut.tx_ptp_locked.value.integer:
await RisingEdge(dut.tx_clk)
for k in range(1000):
await RisingEdge(dut.tx_clk)
for length in range(60, 92):
for k in range(10):
await RisingEdge(dut.tx_clk)
test_frames = [payload_data(length) for k in range(10)]
start_lane = []
for test_data in test_frames:
await tb.axis_source.send(AxiStreamFrame(test_data, tid=0, tuser=0))
for test_data in test_frames:
rx_frame = await tb.xgmii_sink.recv()
tx_cpl = await tb.tx_cpl_sink.recv()
ptp_ts_ns = int(tx_cpl.tdata[0]) / 2**16
rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
if rx_frame.start_lane == 4:
# start in lane 4 reports 1 full cycle delay, so subtract half clock period
rx_frame_sfd_ns -= 3.2
tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))
assert rx_frame.get_payload() == test_data
assert rx_frame.check_fcs()
assert rx_frame.ctrl is None
assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period) < tb.clk_period*2
start_lane.append(rx_frame.start_lane)
tb.log.info("length: %d", length)
tb.log.info("start_lane: %s", start_lane)
start_lane_ref = []
# compute expected starting lanes
lane = 0
deficit_idle_count = 0
for test_data in test_frames:
if ifg == 0:
lane = 0
start_lane_ref.append(lane)
lane = (lane + len(test_data)+4+ifg) % byte_width
if dic_en:
offset = lane % 4
if deficit_idle_count+offset >= 4:
offset += 4
lane = (lane - offset) % byte_width
deficit_idle_count = (deficit_idle_count + offset) % 4
else:
offset = lane % 4
if offset > 0:
offset += 4
lane = (lane - offset) % byte_width
tb.log.info("start_lane_ref: %s", start_lane_ref)
assert start_lane_ref == start_lane
await RisingEdge(dut.logic_clk)
assert tb.xgmii_sink.empty()
await RisingEdge(dut.logic_clk)
await RisingEdge(dut.logic_clk)
def size_list():
return list(range(60, 128)) + [512, 1514, 9214] + [60]*10
def incrementing_payload(length):
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
def cycle_en():
return itertools.cycle([0, 0, 0, 1])
if cocotb.SIM_NAME:
for test in [run_test_rx, run_test_tx]:
factory = TestFactory(test)
factory.add_option("payload_lengths", [size_list])
factory.add_option("payload_data", [incrementing_payload])
factory.add_option("ifg", [12, 0])
factory.generate_tests()
factory = TestFactory(run_test_tx_alignment)
factory.add_option("payload_data", [incrementing_payload])
factory.add_option("ifg", [12])
factory.generate_tests()
# cocotb-test
tests_dir = os.path.abspath(os.path.dirname(__file__))
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
def process_f_files(files):
lst = []
for f in files:
if f[-2:].lower() == '.f':
with open(f, 'r') as fp:
l = fp.read().split()
lst.extend(process_f_files([os.path.join(os.path.dirname(f), x) for x in l]))
else:
lst.append(f)
return list(dict.fromkeys(lst))
@pytest.mark.parametrize("dic_en", [1, 0])
@pytest.mark.parametrize("data_w", [32, 64])
def test_taxi_eth_mac_10g_fifo(request, data_w, dic_en):
dut = "taxi_eth_mac_10g_fifo"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = module
verilog_sources = [
os.path.join(tests_dir, f"{toplevel}.sv"),
os.path.join(rtl_dir, "eth", f"{dut}.f"),
]
verilog_sources = process_f_files(verilog_sources)
parameters = {}
parameters['DATA_W'] = data_w
parameters['AXIS_DATA_W'] = parameters['DATA_W']
parameters['PADDING_EN'] = 1
parameters['DIC_EN'] = dic_en
parameters['MIN_FRAME_LEN'] = 64
parameters['PTP_TS_EN'] = 1
parameters['PTP_TS_FMT_TOD'] = 1
parameters['PTP_TS_W'] = 96 if parameters['PTP_TS_FMT_TOD'] else 64
parameters['TX_TAG_W'] = 16
parameters['TX_FIFO_DEPTH'] = 16384
parameters['TX_FIFO_RAM_PIPELINE'] = 1
parameters['TX_FRAME_FIFO'] = 1
parameters['TX_DROP_OVERSIZE_FRAME'] = parameters['TX_FRAME_FIFO']
parameters['TX_DROP_BAD_FRAME'] = parameters['TX_DROP_OVERSIZE_FRAME']
parameters['TX_DROP_WHEN_FULL'] = 0
parameters['TX_CPL_FIFO_DEPTH'] = 64
parameters['RX_FIFO_DEPTH'] = 16384
parameters['RX_FIFO_RAM_PIPELINE'] = 1
parameters['RX_FRAME_FIFO'] = 1
parameters['RX_DROP_OVERSIZE_FRAME'] = parameters['RX_FRAME_FIFO']
parameters['RX_DROP_BAD_FRAME'] = parameters['RX_DROP_OVERSIZE_FRAME']
parameters['RX_DROP_WHEN_FULL'] = parameters['RX_DROP_OVERSIZE_FRAME']
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
simulator="verilator",
python_search=[tests_dir],
verilog_sources=verilog_sources,
toplevel=toplevel,
module=module,
parameters=parameters,
sim_build=sim_build,
extra_env=extra_env,
)

165
tb/eth/taxi_eth_mac_10g_fifo/test_taxi_eth_mac_10g_fifo.sv Normal file
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// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet MAC with TX and RX FIFOs testbench
*/
module test_taxi_eth_mac_10g_fifo #
(
/* verilator lint_off WIDTHTRUNC */
parameter DATA_W = 8,
parameter AXIS_DATA_W = 8,
parameter logic PADDING_EN = 1'b1,
parameter logic DIC_EN = 1'b1,
parameter MIN_FRAME_LEN = 64,
parameter logic PTP_TS_EN = 1'b0,
parameter logic PTP_TS_FMT_TOD = 1'b1,
parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64,
parameter TX_TAG_W = 16,
parameter TX_FIFO_DEPTH = 4096,
parameter TX_FIFO_RAM_PIPELINE = 1,
parameter logic TX_FRAME_FIFO = 1'b1,
parameter logic TX_DROP_OVERSIZE_FRAME = TX_FRAME_FIFO,
parameter logic TX_DROP_BAD_FRAME = TX_DROP_OVERSIZE_FRAME,
parameter logic TX_DROP_WHEN_FULL = 1'b0,
parameter TX_CPL_FIFO_DEPTH = 64,
parameter RX_FIFO_DEPTH = 4096,
parameter RX_FIFO_RAM_PIPELINE = 1,
parameter logic RX_FRAME_FIFO = 1'b1,
parameter logic RX_DROP_OVERSIZE_FRAME = RX_FRAME_FIFO,
parameter logic RX_DROP_BAD_FRAME = RX_DROP_OVERSIZE_FRAME,
parameter logic RX_DROP_WHEN_FULL = RX_DROP_OVERSIZE_FRAME
/* verilator lint_on WIDTHTRUNC */
)
();
localparam CTRL_W = DATA_W/8;
localparam TX_USER_W = 1;
localparam RX_USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1;
logic rx_clk;
logic rx_rst;
logic tx_clk;
logic tx_rst;
logic logic_clk;
logic logic_rst;
logic ptp_sample_clk;
taxi_axis_if #(.DATA_W(AXIS_DATA_W), .USER_EN(1), .USER_W(TX_USER_W), .ID_EN(1), .ID_W(TX_TAG_W)) s_axis_tx();
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_EN(1), .ID_W(TX_TAG_W)) m_axis_tx_cpl();
taxi_axis_if #(.DATA_W(AXIS_DATA_W), .USER_EN(1), .USER_W(RX_USER_W)) m_axis_rx();
logic [DATA_W-1:0] xgmii_rxd;
logic [CTRL_W-1:0] xgmii_rxc;
logic [DATA_W-1:0] xgmii_txd;
logic [CTRL_W-1:0] xgmii_txc;
logic tx_error_underflow;
logic tx_fifo_overflow;
logic tx_fifo_bad_frame;
logic tx_fifo_good_frame;
logic rx_error_bad_frame;
logic rx_error_bad_fcs;
logic rx_fifo_overflow;
logic rx_fifo_bad_frame;
logic rx_fifo_good_frame;
logic [PTP_TS_W-1:0] ptp_ts;
logic ptp_ts_step;
logic [7:0] cfg_ifg;
logic cfg_tx_enable;
logic cfg_rx_enable;
taxi_eth_mac_10g_fifo #(
.DATA_W(DATA_W),
.CTRL_W(CTRL_W),
.PADDING_EN(PADDING_EN),
.DIC_EN(DIC_EN),
.MIN_FRAME_LEN(MIN_FRAME_LEN),
.PTP_TS_EN(PTP_TS_EN),
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
.PTP_TS_W(PTP_TS_W),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.TX_FIFO_RAM_PIPELINE(TX_FIFO_RAM_PIPELINE),
.TX_FRAME_FIFO(TX_FRAME_FIFO),
.TX_DROP_OVERSIZE_FRAME(TX_DROP_OVERSIZE_FRAME),
.TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL),
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.RX_FIFO_RAM_PIPELINE(RX_FIFO_RAM_PIPELINE),
.RX_FRAME_FIFO(RX_FRAME_FIFO),
.RX_DROP_OVERSIZE_FRAME(RX_DROP_OVERSIZE_FRAME),
.RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
.RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
)
uut (
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.logic_clk(logic_clk),
.logic_rst(logic_rst),
.ptp_sample_clk(ptp_sample_clk),
/*
* Transmit interface (AXI stream)
*/
.s_axis_tx(s_axis_tx),
.m_axis_tx_cpl(m_axis_tx_cpl),
/*
* Receive interface (AXI stream)
*/
.m_axis_rx(m_axis_rx),
/*
* XGMII interface
*/
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
/*
* Status
*/
.tx_error_underflow(tx_error_underflow),
.tx_fifo_overflow(tx_fifo_overflow),
.tx_fifo_bad_frame(tx_fifo_bad_frame),
.tx_fifo_good_frame(tx_fifo_good_frame),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.rx_fifo_overflow(rx_fifo_overflow),
.rx_fifo_bad_frame(rx_fifo_bad_frame),
.rx_fifo_good_frame(rx_fifo_good_frame),
/*
* PTP clock
*/
.ptp_ts(ptp_ts),
.ptp_ts_step(ptp_ts_step),
/*
* Configuration
*/
.cfg_ifg(cfg_ifg),
.cfg_tx_enable(cfg_tx_enable),
.cfg_rx_enable(cfg_rx_enable)
);
endmodule
`resetall