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eth: Fix BASE-R model timestamping

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-06-04 17:39:19 -07:00
parent 251921bfce
commit 90bbb8a780
8 changed files with 62 additions and 139 deletions
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50
src/eth/tb/baser.py
View File

@@ -198,6 +198,7 @@ class BaseRSerdesSource():
async def _run(self):
frame = None
frame_offset = 0
in_pre = False
ifg_cnt = 0
deficit_idle_cnt = 0
scrambler_state = 0
@@ -214,11 +215,10 @@ class BaseRSerdesSource():
while True:
await RisingEdge(self.clock)
if not clk_period:
if last_clk:
clk_period = get_sim_time() - last_clk
else:
last_clk = get_sim_time()
sim_time = get_sim_time()
if last_clk:
clk_period = sim_time - last_clk
last_clk = sim_time
# clock enable
if self.enable is not None and not self.enable.value:
@@ -288,7 +288,7 @@ class BaseRSerdesSource():
self.queue_occupancy_bytes -= len(frame)
self.queue_occupancy_frames -= 1
self.current_frame = frame
frame.sim_time_start = get_sim_time() - gbx_delay
frame.sim_time_start = sim_time - gbx_delay
frame.sim_time_sfd = None
frame.sim_time_end = None
self.log.info("TX frame: %s", frame)
@@ -318,6 +318,7 @@ class BaseRSerdesSource():
ifg_cnt = 0
self.active = True
frame_offset = 0
in_pre = True
else:
# clear counters
deficit_idle_cnt = 0
@@ -330,15 +331,17 @@ class BaseRSerdesSource():
for k in range(8):
if frame is not None:
d = frame.data[frame_offset]
if frame.sim_time_sfd is None and d == EthPre.SFD:
frame.sim_time_sfd = get_sim_time() - gbx_delay
if frame.sim_time_sfd is None and not in_pre:
frame.sim_time_sfd = sim_time + (clk_period // self.byte_lanes * k) - gbx_delay
if d == EthPre.SFD:
in_pre = False
dl.append(d)
cl.append(frame.ctrl[frame_offset])
frame_offset += 1
if frame_offset >= len(frame.data):
ifg_cnt = max(self.ifg - (8-k), 0)
frame.sim_time_end = get_sim_time() - gbx_delay
frame.sim_time_end = sim_time - gbx_delay
frame.handle_tx_complete()
frame = None
self.current_frame = None
@@ -642,6 +645,7 @@ class BaseRSerdesSink:
async def _run(self):
frame = None
scrambler_state = 0
in_pre = False
self.active = False
clk_period = 0
@@ -655,11 +659,10 @@ class BaseRSerdesSink:
while True:
await RisingEdge(self.clock)
if not clk_period:
if last_clk:
clk_period = get_sim_time() - last_clk
else:
last_clk = get_sim_time()
sim_time = get_sim_time()
if last_clk:
clk_period = sim_time - last_clk
last_clk = sim_time
# clock enable
if self.enable is not None and not self.enable.value:
@@ -869,16 +872,17 @@ class BaseRSerdesSink:
dl = [XgmiiCtrl.ERROR]*8
cl = [1]*8
for offset in range(8):
d_val = dl[offset]
c_val = cl[offset]
for k in range(8):
d_val = dl[k]
c_val = cl[k]
if frame is None:
if c_val and d_val == XgmiiCtrl.START:
# start
frame = XgmiiFrame(bytearray([EthPre.PRE]), [0])
frame.sim_time_start = get_sim_time() + gbx_delay
frame.start_lane = offset
frame.sim_time_start = sim_time + gbx_delay
frame.start_lane = k
in_pre = True
else:
if c_val:
# got a control character; terminate frame reception
@@ -888,7 +892,7 @@ class BaseRSerdesSink:
frame.ctrl.append(c_val)
frame.compact()
frame.sim_time_end = get_sim_time() + gbx_delay
frame.sim_time_end = sim_time + gbx_delay
self.log.info("RX frame: %s", frame)
self.queue_occupancy_bytes += len(frame)
@@ -899,8 +903,10 @@ class BaseRSerdesSink:
frame = None
else:
if frame.sim_time_sfd is None and d_val == EthPre.SFD:
frame.sim_time_sfd = get_sim_time() + gbx_delay
if frame.sim_time_sfd is None and not in_pre:
frame.sim_time_sfd = sim_time + (clk_period // self.byte_lanes * k) + gbx_delay
if d_val == EthPre.SFD:
in_pre = False
frame.data.append(d_val)
frame.ctrl.append(c_val)

6
src/eth/tb/taxi_axis_baser_rx_32/test_taxi_axis_baser_rx_32.py
View File

@@ -142,10 +142,6 @@ async def run_test(dut, gbx_cfg=None, payload_lengths=None, payload_data=None, i
tx_frame_sfd_ns = get_time_from_sim_steps(tx_frame.sim_time_sfd, "ns")
if tx_frame.start_lane == 4:
# start in lane 4 reports 1 full cycle delay, so subtract half clock period
tx_frame_sfd_ns -= tb.clk_period
tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns)
tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns)
tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns))
@@ -153,7 +149,7 @@ async def run_test(dut, gbx_cfg=None, payload_lengths=None, payload_data=None, i
assert rx_frame.tdata == test_data
assert frame_error == 0
if gbx_cfg is None:
assert abs(ptp_ts_ns - tx_frame_sfd_ns - tb.clk_period*3) < 0.01
assert abs(ptp_ts_ns - tx_frame_sfd_ns - tb.clk_period*1) < 0.01
assert tb.sink.empty()

6
src/eth/tb/taxi_axis_baser_rx_64/test_taxi_axis_baser_rx_64.py
View File

@@ -142,10 +142,6 @@ async def run_test(dut, gbx_cfg=None, payload_lengths=None, payload_data=None, i
tx_frame_sfd_ns = get_time_from_sim_steps(tx_frame.sim_time_sfd, "ns")
if tx_frame.start_lane == 4:
# start in lane 4 reports 1 full cycle delay, so subtract half clock period
tx_frame_sfd_ns -= tb.clk_period/2
tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns)
tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns)
tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns))
@@ -153,7 +149,7 @@ async def run_test(dut, gbx_cfg=None, payload_lengths=None, payload_data=None, i
assert rx_frame.tdata == test_data
assert frame_error == 0
if gbx_cfg is None:
assert abs(ptp_ts_ns - tx_frame_sfd_ns - tb.clk_period) < 0.01
assert abs(ptp_ts_ns - tx_frame_sfd_ns - tb.clk_period*0) < 0.01
assert tb.sink.empty()

6
src/eth/tb/taxi_axis_baser_tx_32/test_taxi_axis_baser_tx_32.py
View File

@@ -143,10 +143,6 @@ async def run_test(dut, gbx_cfg=None, payload_lengths=None, payload_data=None, i
rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
if rx_frame.start_lane == 4:
# start in lane 4 reports 1 full cycle delay, so subtract half clock period
rx_frame_sfd_ns -= tb.clk_period/2*2
tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))
@@ -155,7 +151,7 @@ async def run_test(dut, gbx_cfg=None, payload_lengths=None, payload_data=None, i
assert rx_frame.check_fcs()
assert rx_frame.ctrl is None
if gbx_cfg is None:
assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period*2) < 0.01
assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period*4) < 0.01
assert tb.sink.empty()

12
src/eth/tb/taxi_axis_baser_tx_64/test_taxi_axis_baser_tx_64.py
View File

@@ -143,10 +143,6 @@ async def run_test(dut, gbx_cfg=None, payload_lengths=None, payload_data=None, i
rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
if rx_frame.start_lane == 4:
# start in lane 4 reports 1 full cycle delay, so subtract half clock period
rx_frame_sfd_ns -= tb.clk_period/2
tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))
@@ -155,7 +151,7 @@ async def run_test(dut, gbx_cfg=None, payload_lengths=None, payload_data=None, i
assert rx_frame.check_fcs()
assert rx_frame.ctrl is None
if gbx_cfg is None:
assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period*2) < 0.01
assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period*3) < 0.01
assert tb.sink.empty()
@@ -220,10 +216,6 @@ async def run_test_alignment(dut, gbx_cfg=None, payload_data=None, ifg=12):
rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
if rx_frame.start_lane == 4:
# start in lane 4 reports 1 full cycle delay, so subtract half clock period
rx_frame_sfd_ns -= tb.clk_period/2
tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))
@@ -232,7 +224,7 @@ async def run_test_alignment(dut, gbx_cfg=None, payload_data=None, ifg=12):
assert rx_frame.check_fcs()
assert rx_frame.ctrl is None
if gbx_cfg is None:
assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period*2) < 0.01
assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period*3) < 0.01
start_lane.append(rx_frame.start_lane)

55
src/eth/tb/taxi_eth_mac_25g_us/test_taxi_eth_mac_25g_us.py
View File

@@ -225,15 +225,15 @@ async def run_test_regs(dut):
async def run_test_rx(dut, port=0, payload_lengths=None, payload_data=None, ifg=12):
if dut.DATA_W.value == 64:
if dut.COMBINED_MAC_PCS.value:
pipe_delay = 3
else:
pipe_delay = 4
else:
if dut.COMBINED_MAC_PCS.value:
pipe_delay = 4
else:
pipe_delay = 5
else:
if dut.COMBINED_MAC_PCS.value:
pipe_delay = 6
else:
pipe_delay = 7
tb = TB(dut)
@@ -280,13 +280,6 @@ async def run_test_rx(dut, port=0, payload_lengths=None, payload_data=None, ifg=
tx_frame_sfd_ns = get_time_from_sim_steps(tx_frame.sim_time_sfd, "ns")
if tx_frame.start_lane == 4:
# start in lane 4 reports 1 full cycle delay, so subtract half clock period
if dut.DATA_W.value == 64:
tx_frame_sfd_ns -= tb.clk_period[port]/2
else:
tx_frame_sfd_ns -= tb.clk_period[port]
tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns)
tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns)
tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns))
@@ -310,14 +303,14 @@ async def run_test_tx(dut, port=0, payload_lengths=None, payload_data=None, ifg=
if dut.DATA_W.value == 64:
if dut.COMBINED_MAC_PCS.value:
pipe_delay = 5
else:
pipe_delay = 5
else:
if dut.COMBINED_MAC_PCS.value:
pipe_delay = 5
pipe_delay = 6
else:
pipe_delay = 6
else:
if dut.COMBINED_MAC_PCS.value:
pipe_delay = 7
else:
pipe_delay = 8
tb = TB(dut)
@@ -357,13 +350,6 @@ async def run_test_tx(dut, port=0, payload_lengths=None, payload_data=None, ifg=
rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
if rx_frame.start_lane == 4:
# start in lane 4 reports 1 full cycle delay, so subtract half clock period
if dut.DATA_W.value == 64:
rx_frame_sfd_ns -= tb.clk_period[port]/2
else:
rx_frame_sfd_ns -= tb.clk_period[port]
tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))
@@ -390,14 +376,14 @@ async def run_test_tx_alignment(dut, port=0, payload_data=None, ifg=12):
if dut.DATA_W.value == 64:
if dut.COMBINED_MAC_PCS.value:
pipe_delay = 5
else:
pipe_delay = 5
else:
if dut.COMBINED_MAC_PCS.value:
pipe_delay = 5
pipe_delay = 6
else:
pipe_delay = 6
else:
if dut.COMBINED_MAC_PCS.value:
pipe_delay = 7
else:
pipe_delay = 8
tb = TB(dut)
@@ -445,13 +431,6 @@ async def run_test_tx_alignment(dut, port=0, payload_data=None, ifg=12):
rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
if rx_frame.start_lane == 4:
# start in lane 4 reports 1 full cycle delay, so subtract half clock period
if dut.DATA_W.value == 64:
rx_frame_sfd_ns -= tb.clk_period[port]/2
else:
rx_frame_sfd_ns -= tb.clk_period[port]
tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))

33
src/eth/tb/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.py
View File

@@ -176,9 +176,9 @@ class TB:
async def run_test_rx(dut, gbx_cfg=None, payload_lengths=None, payload_data=None, ifg=12):
if len(dut.serdes_tx_data) == 64:
pipe_delay = 4
pipe_delay = 3
else:
pipe_delay = 6
pipe_delay = 4
tb = TB(dut, gbx_cfg)
@@ -222,13 +222,6 @@ async def run_test_rx(dut, gbx_cfg=None, payload_lengths=None, payload_data=None
tx_frame_sfd_ns = get_time_from_sim_steps(tx_frame.sim_time_sfd, "ns")
if tx_frame.start_lane == 4:
# start in lane 4 reports 1 full cycle delay, so subtract half clock period
if len(dut.serdes_tx_data) == 64:
tx_frame_sfd_ns -= tb.clk_period/2
else:
tx_frame_sfd_ns -= tb.clk_period
tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns)
tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns)
tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns))
@@ -251,9 +244,9 @@ async def run_test_rx(dut, gbx_cfg=None, payload_lengths=None, payload_data=None
async def run_test_tx(dut, gbx_cfg=None, payload_lengths=None, payload_data=None, ifg=12):
if len(dut.serdes_tx_data) == 64:
pipe_delay = 5
pipe_delay = 6
else:
pipe_delay = 5
pipe_delay = 7
tb = TB(dut, gbx_cfg)
@@ -291,13 +284,6 @@ async def run_test_tx(dut, gbx_cfg=None, payload_lengths=None, payload_data=None
rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
if rx_frame.start_lane == 4:
# start in lane 4 reports 1 full cycle delay, so subtract half clock period
if len(dut.serdes_tx_data) == 64:
rx_frame_sfd_ns -= tb.clk_period/2
else:
rx_frame_sfd_ns -= tb.clk_period
tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))
@@ -321,9 +307,9 @@ async def run_test_tx(dut, gbx_cfg=None, payload_lengths=None, payload_data=None
async def run_test_tx_alignment(dut, gbx_cfg=None, payload_data=None, ifg=12):
if len(dut.serdes_tx_data) == 64:
pipe_delay = 5
pipe_delay = 6
else:
pipe_delay = 5
pipe_delay = 7
dic_en = int(cocotb.top.DIC_EN.value)
@@ -371,13 +357,6 @@ async def run_test_tx_alignment(dut, gbx_cfg=None, payload_data=None, ifg=12):
rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
if rx_frame.start_lane == 4:
# start in lane 4 reports 1 full cycle delay, so subtract half clock period
if len(dut.serdes_tx_data) == 64:
rx_frame_sfd_ns -= tb.clk_period/2
else:
rx_frame_sfd_ns -= tb.clk_period
tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))

33
src/eth/tb/taxi_eth_mac_phy_10g_fifo/test_taxi_eth_mac_phy_10g_fifo.py
View File

@@ -144,9 +144,9 @@ class TB:
async def run_test_rx(dut, gbx_cfg=None, payload_lengths=None, payload_data=None, ifg=12):
if len(dut.serdes_tx_data) == 64:
pipe_delay = 4
pipe_delay = 3
else:
pipe_delay = 6
pipe_delay = 4
tb = TB(dut, gbx_cfg)
@@ -187,13 +187,6 @@ async def run_test_rx(dut, gbx_cfg=None, payload_lengths=None, payload_data=None
tx_frame_sfd_ns = get_time_from_sim_steps(tx_frame.sim_time_sfd, "ns")
if tx_frame.start_lane == 4:
# start in lane 4 reports 1 full cycle delay, so subtract half clock period
if len(dut.serdes_tx_data) == 64:
tx_frame_sfd_ns -= tb.clk_period/2
else:
tx_frame_sfd_ns -= tb.clk_period
tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns)
tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns)
tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns))
@@ -215,9 +208,9 @@ async def run_test_rx(dut, gbx_cfg=None, payload_lengths=None, payload_data=None
async def run_test_tx(dut, gbx_cfg=None, payload_lengths=None, payload_data=None, ifg=12):
if len(dut.serdes_tx_data) == 64:
pipe_delay = 5
pipe_delay = 6
else:
pipe_delay = 5
pipe_delay = 7
tb = TB(dut, gbx_cfg)
@@ -251,13 +244,6 @@ async def run_test_tx(dut, gbx_cfg=None, payload_lengths=None, payload_data=None
rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
if rx_frame.start_lane == 4:
# start in lane 4 reports 1 full cycle delay, so subtract half clock period
if len(dut.serdes_tx_data) == 64:
rx_frame_sfd_ns -= tb.clk_period/2
else:
rx_frame_sfd_ns -= tb.clk_period
tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))
@@ -280,9 +266,9 @@ async def run_test_tx(dut, gbx_cfg=None, payload_lengths=None, payload_data=None
async def run_test_tx_alignment(dut, gbx_cfg=None, payload_data=None, ifg=12):
if len(dut.serdes_tx_data) == 64:
pipe_delay = 5
pipe_delay = 6
else:
pipe_delay = 5
pipe_delay = 7
dic_en = int(cocotb.top.DIC_EN.value)
@@ -326,13 +312,6 @@ async def run_test_tx_alignment(dut, gbx_cfg=None, payload_data=None, ifg=12):
rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
if rx_frame.start_lane == 4:
# start in lane 4 reports 1 full cycle delay, so subtract half clock period
if len(dut.serdes_tx_data) == 64:
rx_frame_sfd_ns -= tb.clk_period/2
else:
rx_frame_sfd_ns -= tb.clk_period
tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
tb.log.info("Difference: %f ns", abs(rx_frame_sfd_ns - ptp_ts_ns))