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axis: Add AXI stream switch module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
@@ -45,6 +45,7 @@ To facilitate the dual-license model, contributions to the project can only be a
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* Demultiplexer
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* Broadcaster
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* Concatenator
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* Switch
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* COBS encoder
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* COBS decoder
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* Pipeline register
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5
src/axis/rtl/taxi_axis_switch.f
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5
src/axis/rtl/taxi_axis_switch.f
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@@ -0,0 +1,5 @@
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taxi_axis_switch.sv
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taxi_axis_register.sv
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taxi_axis_if.sv
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../lib/taxi/src/prim/rtl/taxi_arbiter.sv
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../lib/taxi/src/prim/rtl/taxi_penc.sv
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371
src/axis/rtl/taxi_axis_switch.sv
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371
src/axis/rtl/taxi_axis_switch.sv
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@@ -0,0 +1,371 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2016-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4-Stream switch
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*/
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module taxi_axis_switch #
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(
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// Number of AXI stream inputs
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parameter S_COUNT = 4,
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// Number of AXI stream outputs
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parameter M_COUNT = 4,
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// Output interface routing base tdest selection
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// Port selected if M_BASE <= tdest <= M_TOP
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parameter M_BASE[M_COUNT] = '{M_COUNT{'0}},
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// Output interface routing top tdest selection
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// Port selected if M_BASE <= tdest <= M_TOP
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parameter M_TOP[M_COUNT] = '{M_COUNT{'0}},
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// Set for default routing with tdest MSBs as port index
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parameter logic AUTO_ADDR = 1'b0,
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// Interface connection control
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parameter logic M_CONNECT[M_COUNT][S_COUNT] = '{M_COUNT{'{S_COUNT{1'b1}}}},
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// Update tid with routing information
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parameter logic UPDATE_TID = 1'b0,
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// Input interface register type
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S_REG_TYPE = 0,
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// Output interface register type
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M_REG_TYPE = 2,
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// select round robin arbitration
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parameter logic ARB_ROUND_ROBIN = 1'b1,
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// LSB priority selection
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parameter logic ARB_LSB_HIGH_PRIO = 1'b1
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* AXI4-Stream inputs (sink)
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*/
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taxi_axis_if.snk s_axis[S_COUNT],
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/*
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* AXI4-Stream outputs (source)
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*/
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taxi_axis_if.src m_axis[M_COUNT]
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);
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// extract parameters
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localparam DATA_W = s_axis[0].DATA_W;
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localparam logic KEEP_EN = s_axis[0].KEEP_EN && m_axis[0].KEEP_EN;
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localparam KEEP_W = s_axis[0].KEEP_W;
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localparam logic STRB_EN = s_axis[0].STRB_EN && m_axis[0].STRB_EN;
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localparam logic LAST_EN = s_axis[0].LAST_EN && m_axis[0].LAST_EN;
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localparam logic ID_EN = s_axis[0].ID_EN && m_axis[0].ID_EN;
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localparam S_ID_W = s_axis[0].ID_W;
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localparam logic DEST_EN = s_axis[0].DEST_EN && m_axis[0].DEST_EN;
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localparam S_DEST_W = s_axis[0].DEST_W;
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localparam logic USER_EN = s_axis[0].USER_EN && m_axis[0].USER_EN;
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localparam USER_W = s_axis[0].USER_W;
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localparam M_ID_W = m_axis[0].ID_W;
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localparam M_DEST_W = m_axis[0].DEST_W;
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localparam CL_S_COUNT = $clog2(S_COUNT);
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localparam CL_M_COUNT = $clog2(M_COUNT);
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localparam S_ID_W_INT = S_ID_W > 0 ? S_ID_W : 1;
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localparam M_ID_W_INT = M_ID_W > 0 ? M_ID_W : 1;
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localparam S_DEST_W_INT = S_DEST_W > 0 ? S_DEST_W : 1;
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localparam M_DEST_W_INT = M_DEST_W > 0 ? M_DEST_W : 1;
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// check configuration
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if (m_axis.DATA_W != DATA_W)
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$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
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if (KEEP_EN && m_axis.KEEP_W != KEEP_W)
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$fatal(0, "Error: Interface KEEP_W parameter mismatch (instance %m)");
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if (M_COUNT > 1) begin
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if (!DEST_EN)
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$fatal(0, "Error: DEST_EN required for M_COUNT > 1 (instance %m)");
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if (S_DEST_W < CL_M_COUNT)
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$fatal(0, "Error: S_DEST_W too small for port count (instance %m)");
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end
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if (UPDATE_TID) begin
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if (!ID_EN)
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$fatal(0, "Error: UPDATE_TID set requires ID_EN set (instance %m)");
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if (M_ID_W < CL_S_COUNT)
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$fatal(0, "Error: M_ID_W too small for port count (instance %m)");
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end
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if (AUTO_ADDR) begin
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initial begin
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// route with tdest as port index
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$display("Addressing configuration for axis_switch instance %m");
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for (integer i = 0; i < M_COUNT; i = i + 1) begin
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$display("%d: %08x-%08x", i, i << (S_DEST_W-CL_M_COUNT), ((i+1) << (S_DEST_W-CL_M_COUNT))-1);
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end
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end
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end else begin
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for (genvar i = 0; i < M_COUNT; i = i + 1) begin
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if (M_BASE[i] > M_TOP[i]) begin
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$fatal(0, "Error: range index %d is invalid (%08x > %08x) (instance %m)", i, M_BASE[i], M_TOP[i]);
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end
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for (genvar j = i+1; j < M_COUNT; j = j + 1) begin
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if (M_BASE[i] <= M_TOP[j] && M_BASE[j] <= M_TOP[i]) begin
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$fatal(0, "Error: ranges %d (%08x-%08x) and %d (%08x-%08x) overlap (instance %m)", i, M_BASE[i], M_TOP[i], j, M_BASE[j], M_TOP[j]);
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end
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end
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end
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initial begin
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$display("Addressing configuration for axis_switch instance %m");
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for (integer i = 0; i < M_COUNT; i = i + 1) begin
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$display("%d: %08x-%08x", i, M_BASE[i], M_TOP[i]);
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end
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end
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end
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wire [DATA_W-1:0] int_s_axis_tdata[S_COUNT];
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wire [KEEP_W-1:0] int_s_axis_tkeep[S_COUNT];
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wire int_s_axis_tvalid[S_COUNT];
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wire int_s_axis_tready[S_COUNT];
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wire int_s_axis_tlast[S_COUNT];
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wire [S_ID_W-1:0] int_s_axis_tid[S_COUNT];
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wire [S_DEST_W-1:0] int_s_axis_tdest[S_COUNT];
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wire [USER_W-1:0] int_s_axis_tuser[S_COUNT];
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logic [M_COUNT-1:0] int_axis_tvalid[S_COUNT];
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logic [S_COUNT-1:0] int_axis_tready[M_COUNT];
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for (genvar m = 0; m < S_COUNT; m = m + 1) begin : s_if
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taxi_axis_if #(
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.DATA_W(s_axis.DATA_W),
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.KEEP_EN(s_axis.KEEP_EN),
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.KEEP_W(s_axis.KEEP_W),
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.STRB_EN(s_axis.STRB_EN),
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.LAST_EN(s_axis.LAST_EN),
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.ID_EN(s_axis.ID_EN),
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.ID_W(s_axis.ID_W),
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.DEST_EN(s_axis.DEST_EN),
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.DEST_W(s_axis.DEST_W),
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.USER_EN(s_axis.USER_EN),
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.USER_W(s_axis.USER_W)
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) int_axis();
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// S side register
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taxi_axis_register #(
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.REG_TYPE(S_REG_TYPE)
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)
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reg_inst (
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.clk(clk),
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.rst(rst),
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/*
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* AXI4-Stream input (sink)
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*/
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.s_axis(s_axis[m]),
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/*
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* AXI4-Stream output (source)
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*/
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.m_axis(int_axis)
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);
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if (M_COUNT == 1) begin
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// degenerate case
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// forwarding
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assign int_s_axis_tdata[m] = int_axis.tdata;
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assign int_s_axis_tkeep[m] = int_axis.tkeep;
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assign int_s_axis_tvalid[m] = int_axis.tvalid;
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assign int_s_axis_tlast[m] = int_axis.tlast;
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assign int_s_axis_tid[m] = int_axis.tid;
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assign int_s_axis_tdest[m] = int_axis.tdest;
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assign int_s_axis_tuser[m] = int_axis.tuser;
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assign int_axis_tvalid[m] = int_axis.tvalid;
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assign int_axis.tready = int_axis_tready[0][m];
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end else begin
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// decoding
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logic frame_reg = 1'b0, frame_next;
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logic [CL_M_COUNT-1:0] select_reg = '0, select_next;
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logic drop_reg = 1'b0, drop_next;
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logic select_valid_reg = 1'b0, select_valid_next;
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always_comb begin
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select_next = select_reg;
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drop_next = drop_reg && !(int_axis.tvalid && int_axis.tready && int_axis.tlast);
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select_valid_next = select_valid_reg && !(int_axis.tvalid && int_axis.tready && int_axis.tlast);
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if (int_axis.tvalid && !select_valid_reg && !drop_reg) begin
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select_next = '0;
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select_valid_next = 1'b0;
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drop_next = 1'b1;
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for (integer k = 0; k < M_COUNT; k = k + 1) begin
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if (AUTO_ADDR) begin
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// route with $clog2(M_COUNT) MSBs of tdest as port index
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if (int_axis.tdest[(S_DEST_W-CL_M_COUNT) +: CL_M_COUNT] == CL_M_COUNT'(k) && M_CONNECT[k][m]) begin
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select_next = CL_M_COUNT'(k);
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select_valid_next = 1'b1;
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drop_next = 1'b0;
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end
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end else begin
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if (int_axis.tdest >= S_DEST_W'(M_BASE[k]) && int_axis.tdest <= S_DEST_W'(M_TOP[k]) && M_CONNECT[k][m]) begin
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select_next = CL_M_COUNT'(k);
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select_valid_next = 1'b1;
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drop_next = 1'b0;
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end
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end
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end
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end
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end
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always_ff @(posedge clk) begin
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select_reg <= select_next;
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drop_reg <= drop_next;
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select_valid_reg <= select_valid_next;
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if (rst) begin
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select_valid_reg <= 1'b0;
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end
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end
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// forwarding
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assign int_s_axis_tdata[m] = int_axis.tdata;
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assign int_s_axis_tkeep[m] = int_axis.tkeep;
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assign int_s_axis_tvalid[m] = int_axis.tvalid;
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assign int_s_axis_tlast[m] = int_axis.tlast;
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assign int_s_axis_tid[m] = int_axis.tid;
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assign int_s_axis_tdest[m] = int_axis.tdest;
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assign int_s_axis_tuser[m] = int_axis.tuser;
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always_comb begin
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int_axis_tvalid[m] = '0;
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int_axis_tvalid[m][select_reg] = int_axis.tvalid && select_valid_reg && !drop_reg;
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end
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assign int_axis.tready = (int_axis_tready[select_reg][m] || drop_reg) && select_valid_reg;
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end
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end // s_if
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for (genvar n = 0; n < M_COUNT; n = n + 1) begin : m_if
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taxi_axis_if #(
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.DATA_W(m_axis.DATA_W),
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.KEEP_EN(m_axis.KEEP_EN),
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.KEEP_W(m_axis.KEEP_W),
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.STRB_EN(m_axis.STRB_EN),
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.LAST_EN(m_axis.LAST_EN),
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.ID_EN(m_axis.ID_EN),
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.ID_W(m_axis.ID_W),
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.DEST_EN(m_axis.DEST_EN),
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.DEST_W(m_axis.DEST_W),
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.USER_EN(m_axis.USER_EN),
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.USER_W(m_axis.USER_W)
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) int_axis();
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if (S_COUNT == 1) begin
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// degenerate case
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always_comb begin
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int_axis.tdata = int_s_axis_tdata[0];
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int_axis.tkeep = int_s_axis_tkeep[0];
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int_axis.tvalid = int_axis_tvalid[0][n];
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int_axis.tlast = int_s_axis_tlast[0];
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int_axis.tid = M_ID_W'(int_s_axis_tid[0]);
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int_axis.tdest = M_DEST_W'(int_s_axis_tdest[0]);
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int_axis.tuser = int_s_axis_tuser[0];
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end
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assign int_axis_tready[n] = int_axis.tready;
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end else begin
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// arbitration
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wire [S_COUNT-1:0] req;
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wire [S_COUNT-1:0] ack;
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wire [S_COUNT-1:0] grant;
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wire grant_valid;
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wire [CL_S_COUNT-1:0] grant_index;
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taxi_arbiter #(
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.PORTS(S_COUNT),
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.ARB_ROUND_ROBIN(ARB_ROUND_ROBIN),
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.ARB_BLOCK(1),
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.ARB_BLOCK_ACK(1),
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.LSB_HIGH_PRIO(ARB_LSB_HIGH_PRIO)
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)
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arb_inst (
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.clk(clk),
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.rst(rst),
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.req(req),
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.ack(ack),
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.grant(grant),
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.grant_valid(grant_valid),
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.grant_index(grant_index)
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);
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always_comb begin
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int_axis.tdata = int_s_axis_tdata[grant_index];
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int_axis.tkeep = int_s_axis_tkeep[grant_index];
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int_axis.tvalid = int_axis_tvalid[grant_index][n] && grant_valid;
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int_axis.tlast = int_s_axis_tlast[grant_index];
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int_axis.tid = M_ID_W'(int_s_axis_tid[grant_index]);
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if (UPDATE_TID) begin
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int_axis.tid[M_ID_W-1:M_ID_W-CL_S_COUNT] = grant_index;
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end
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int_axis.tdest = M_DEST_W'(int_s_axis_tdest[grant_index]);
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int_axis.tuser = int_s_axis_tuser[grant_index];
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end
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always_comb begin
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int_axis_tready[n] = '0;
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int_axis_tready[n][grant_index] = grant_valid && int_axis.tready;
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end
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for (genvar m = 0; m < S_COUNT; m = m + 1) begin
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assign req[m] = int_axis_tvalid[m][n] && !grant[m];
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assign ack[m] = grant[m] && int_axis_tvalid[m][n] && int_axis.tlast && int_axis.tready;
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end
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end
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// M side register
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taxi_axis_register #(
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.REG_TYPE(S_REG_TYPE)
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)
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reg_inst (
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.clk(clk),
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.rst(rst),
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/*
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* AXI4-Stream input (sink)
|
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*/
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.s_axis(int_axis),
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/*
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* AXI4-Stream output (source)
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*/
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.m_axis(m_axis[n])
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);
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end // m_if
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endmodule
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`resetall
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70
src/axis/tb/taxi_axis_switch/Makefile
Normal file
70
src/axis/tb/taxi_axis_switch/Makefile
Normal file
@@ -0,0 +1,70 @@
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# SPDX-License-Identifier: CERN-OHL-S-2.0
|
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#
|
||||
# Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
#
|
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# Authors:
|
||||
# - Alex Forencich
|
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|
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TOPLEVEL_LANG = verilog
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SIM ?= verilator
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WAVES ?= 0
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COCOTB_HDL_TIMEUNIT = 1ns
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COCOTB_HDL_TIMEPRECISION = 1ps
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RTL_DIR = ../../rtl
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LIB_DIR = ../../lib
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TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
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DUT = taxi_axis_switch
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COCOTB_TEST_MODULES = test_$(DUT)
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COCOTB_TOPLEVEL = test_$(DUT)
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MODULE = $(COCOTB_TEST_MODULES)
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TOPLEVEL = $(COCOTB_TOPLEVEL)
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VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
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VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
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# handle file list files
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process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
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||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_S_COUNT := 4
|
||||
export PARAM_M_COUNT := 4
|
||||
export PARAM_DATA_W := 8
|
||||
export PARAM_KEEP_EN := $(shell expr $(PARAM_DATA_W) \> 8 )
|
||||
export PARAM_KEEP_W := $(shell expr \( $(PARAM_DATA_W) + 7 \) / 8 )
|
||||
export PARAM_STRB_EN := 0
|
||||
export PARAM_LAST_EN := 1
|
||||
export PARAM_ID_EN := 1
|
||||
export PARAM_S_ID_W := 16
|
||||
export PARAM_M_ID_W := $(shell python -c "print($(PARAM_S_ID_W) + ($(PARAM_S_COUNT)-1).bit_length())")
|
||||
export PARAM_DEST_EN := 1
|
||||
export PARAM_M_DEST_W := 8
|
||||
export PARAM_S_DEST_W := $(shell python -c "print($(PARAM_M_DEST_W) + ($(PARAM_M_COUNT)-1).bit_length())")
|
||||
export PARAM_USER_EN := 1
|
||||
export PARAM_USER_W := 1
|
||||
export PARAM_AUTO_ADDR := 1
|
||||
export PARAM_UPDATE_TID := 1
|
||||
export PARAM_S_REG_TYPE := 0
|
||||
export PARAM_M_REG_TYPE := 2
|
||||
export PARAM_ARB_ROUND_ROBIN := 0
|
||||
export PARAM_ARB_LSB_HIGH_PRIO := 1
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
383
src/axis/tb/taxi_axis_switch/test_taxi_axis_switch.py
Normal file
383
src/axis/tb/taxi_axis_switch/test_taxi_axis_switch.py
Normal file
@@ -0,0 +1,383 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import random
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge, Event
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
|
||||
|
||||
self.source = [AxiStreamSource(AxiStreamBus.from_entity(bus), dut.clk, dut.rst) for bus in dut.s_axis]
|
||||
self.sink = [AxiStreamSink(AxiStreamBus.from_entity(bus), dut.clk, dut.rst) for bus in dut.m_axis]
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
for source in self.source:
|
||||
source.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
for sink in self.sink:
|
||||
sink.set_pause_generator(generator())
|
||||
|
||||
async def reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None, s=0, m=0):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
id_width = len(tb.source[0].bus.tid)
|
||||
id_count = 2**id_width
|
||||
id_mask = id_count-1
|
||||
|
||||
dest_width = len(tb.source[0].bus.tdest)
|
||||
dest_shift = dest_width-(len(tb.sink)-1).bit_length()
|
||||
|
||||
src_width = (len(tb.source)-1).bit_length()
|
||||
src_mask = 2**src_width-1 if src_width else 0
|
||||
src_shift = id_width-src_width
|
||||
max_count = 2**src_shift
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for test_data in [payload_data(x) for x in payload_lengths()]:
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id | (s << src_shift)
|
||||
test_frame.tdest = m << dest_shift
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source[s].send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % max_count
|
||||
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink[m].recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert (rx_frame.tid & id_mask) == test_frame.tid
|
||||
assert ((rx_frame.tid >> src_shift) & src_mask) == s
|
||||
assert (rx_frame.tid >> id_width) == s
|
||||
# assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert all(s.empty() for s in tb.sink)
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_tuser_assert(dut, s=0, m=0):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
dest_width = len(tb.sink[0].bus.tdest)
|
||||
dest_shift = dest_width
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data, tuser=1, tdest=m << dest_shift)
|
||||
await tb.source[s].send(test_frame)
|
||||
|
||||
rx_frame = await tb.sink[m].recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert rx_frame.tuser
|
||||
|
||||
assert all(s.empty() for s in tb.sink)
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_arb_test(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.source[0].byte_lanes
|
||||
id_width = len(tb.source[0].bus.tid)
|
||||
id_count = 2**id_width
|
||||
id_mask = id_count-1
|
||||
|
||||
dest_width = len(tb.source[0].bus.tdest)
|
||||
dest_shift = dest_width-(len(tb.sink)-1).bit_length()
|
||||
|
||||
src_width = (len(tb.source)-1).bit_length()
|
||||
src_mask = 2**src_width-1 if src_width else 0
|
||||
src_shift = id_width-src_width
|
||||
max_count = 2**src_shift
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_frames = []
|
||||
|
||||
length = byte_lanes*16
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
for k in range(5):
|
||||
test_frame = AxiStreamFrame(test_data, tx_complete=Event())
|
||||
|
||||
src_ind = 0
|
||||
|
||||
if k == 0:
|
||||
src_ind = 0
|
||||
elif k == 4:
|
||||
await test_frames[1].tx_complete.wait()
|
||||
for j in range(8):
|
||||
await RisingEdge(dut.clk)
|
||||
src_ind = 0
|
||||
else:
|
||||
src_ind = 1
|
||||
|
||||
test_frame.tid = cur_id | (src_ind << src_shift)
|
||||
test_frame.tdest = 0
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source[src_ind].send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % max_count
|
||||
|
||||
for k in [0, 1, 2, 4, 3]:
|
||||
test_frame = test_frames[k]
|
||||
rx_frame = await tb.sink[0].recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert (rx_frame.tid & id_mask) == test_frame.tid
|
||||
assert ((rx_frame.tid >> src_shift) & src_mask) == (rx_frame.tid >> id_width)
|
||||
assert rx_frame.tdest == 0
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert all(s.empty() for s in tb.sink)
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.source[0].byte_lanes
|
||||
id_width = len(tb.source[0].bus.tid)
|
||||
id_count = 2**id_width
|
||||
id_mask = id_count-1
|
||||
|
||||
dest_width = len(tb.source[0].bus.tdest)
|
||||
dest_shift = dest_width-(len(tb.sink)-1).bit_length()
|
||||
|
||||
src_width = (len(tb.source)-1).bit_length()
|
||||
src_mask = 2**src_width-1 if src_width else 0
|
||||
src_shift = id_width-src_width
|
||||
max_count = 2**src_shift
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = [[list() for y in tb.sink] for x in tb.source]
|
||||
|
||||
for p in range(len(tb.source)):
|
||||
for k in range(128):
|
||||
length = random.randint(1, byte_lanes*16)
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id | (p << src_shift)
|
||||
dest = random.randrange(len(tb.sink))
|
||||
test_frame.tdest = dest << dest_shift
|
||||
|
||||
test_frames[p][dest].append(test_frame)
|
||||
await tb.source[p].send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % max_count
|
||||
|
||||
for lst in test_frames:
|
||||
while any(lst):
|
||||
rx_frame = await tb.sink[[dest for dest, x in enumerate(lst) if x][0]].recv()
|
||||
|
||||
test_frame = None
|
||||
|
||||
for lst_a in test_frames:
|
||||
for lst_b in lst_a:
|
||||
if lst_b and lst_b[0].tid == (rx_frame.tid & id_mask):
|
||||
test_frame = lst_b.pop(0)
|
||||
break
|
||||
|
||||
assert test_frame is not None
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert (rx_frame.tid & id_mask) == test_frame.tid
|
||||
assert ((rx_frame.tid >> src_shift) & src_mask) == (rx_frame.tid >> id_width)
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert all(s.empty() for s in tb.sink)
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
def size_list():
|
||||
data_width = len(cocotb.top.s_axis[0].tdata)
|
||||
byte_width = data_width // 8
|
||||
return list(range(1, byte_width*4+1))+[512]+[1]*64
|
||||
|
||||
|
||||
def incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
s_count = len(cocotb.top.s_axis)
|
||||
m_count = len(cocotb.top.m_axis)
|
||||
|
||||
factory = TestFactory(run_test)
|
||||
factory.add_option("payload_lengths", [size_list])
|
||||
factory.add_option("payload_data", [incrementing_payload])
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.add_option("s", range(min(s_count, 2)))
|
||||
factory.add_option("m", range(min(m_count, 2)))
|
||||
factory.generate_tests()
|
||||
|
||||
for test in [run_test_tuser_assert]:
|
||||
factory = TestFactory(test)
|
||||
factory.add_option("s", range(min(s_count, 2)))
|
||||
factory.add_option("m", range(min(m_count, 2)))
|
||||
factory.generate_tests()
|
||||
|
||||
if s_count > 1:
|
||||
factory = TestFactory(run_arb_test)
|
||||
factory.generate_tests()
|
||||
|
||||
factory = TestFactory(run_stress_test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("data_w", [8, 16, 32])
|
||||
@pytest.mark.parametrize("m_count", [1, 4])
|
||||
@pytest.mark.parametrize("s_count", [1, 4])
|
||||
def test_axis_switch(request, s_count, m_count, data_w):
|
||||
dut = "taxi_axis_switch"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.f"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['M_COUNT'] = m_count
|
||||
parameters['S_COUNT'] = s_count
|
||||
parameters['DATA_W'] = data_w
|
||||
parameters['KEEP_EN'] = int(parameters['DATA_W'] > 8)
|
||||
parameters['KEEP_W'] = (parameters['DATA_W'] + 7) // 8
|
||||
parameters['ID_EN'] = 1
|
||||
parameters['S_ID_W'] = 16
|
||||
parameters['M_ID_W'] = parameters['S_ID_W'] + (s_count-1).bit_length()
|
||||
parameters['DEST_EN'] = 1
|
||||
parameters['M_DEST_W'] = 8
|
||||
parameters['S_DEST_W'] = parameters['M_DEST_W'] + (m_count-1).bit_length()
|
||||
parameters['USER_EN'] = 1
|
||||
parameters['USER_W'] = 1
|
||||
parameters['AUTO_ADDR'] = 1
|
||||
parameters['UPDATE_TID'] = 1
|
||||
parameters['S_REG_TYPE'] = 0
|
||||
parameters['M_REG_TYPE'] = 2
|
||||
parameters['ARB_ROUND_ROBIN'] = 1
|
||||
parameters['ARB_LSB_HIGH_PRIO'] = 1
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
110
src/axis/tb/taxi_axis_switch/test_taxi_axis_switch.sv
Normal file
110
src/axis/tb/taxi_axis_switch/test_taxi_axis_switch.sv
Normal file
@@ -0,0 +1,110 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream switch testbench
|
||||
*/
|
||||
module test_taxi_axis_switch #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter S_COUNT = 4,
|
||||
parameter M_COUNT = 4,
|
||||
parameter DATA_W = 8,
|
||||
parameter logic KEEP_EN = (DATA_W>8),
|
||||
parameter KEEP_W = ((DATA_W+7)/8),
|
||||
parameter logic STRB_EN = 1'b0,
|
||||
parameter logic LAST_EN = 1'b1,
|
||||
parameter logic ID_EN = 1'b0,
|
||||
parameter S_ID_W = 8,
|
||||
parameter M_ID_W = S_ID_W+$clog2(S_COUNT),
|
||||
parameter logic DEST_EN = 1'b0,
|
||||
parameter M_DEST_W = 1,
|
||||
parameter S_DEST_W = M_DEST_W+$clog2(M_COUNT),
|
||||
parameter logic USER_EN = 1'b1,
|
||||
parameter USER_W = 1,
|
||||
parameter M_BASE[M_COUNT] = '{M_COUNT{'0}},
|
||||
parameter M_TOP[M_COUNT] = '{M_COUNT{'0}},
|
||||
parameter logic AUTO_ADDR = 1'b1,
|
||||
parameter logic M_CONNECT[M_COUNT][S_COUNT] = '{M_COUNT{'{S_COUNT{1'b1}}}},
|
||||
parameter logic UPDATE_TID = 1'b0,
|
||||
parameter S_REG_TYPE = 0,
|
||||
parameter M_REG_TYPE = 2,
|
||||
parameter logic ARB_ROUND_ROBIN = 1'b1,
|
||||
parameter logic ARB_LSB_HIGH_PRIO = 1'b1
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.KEEP_EN(KEEP_EN),
|
||||
.KEEP_W(KEEP_W),
|
||||
.STRB_EN(STRB_EN),
|
||||
.LAST_EN(LAST_EN),
|
||||
.ID_EN(ID_EN),
|
||||
.ID_W(S_ID_W),
|
||||
.DEST_EN(DEST_EN),
|
||||
.DEST_W(S_DEST_W),
|
||||
.USER_EN(USER_EN),
|
||||
.USER_W(USER_W)
|
||||
) s_axis[S_COUNT]();
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.KEEP_EN(KEEP_EN),
|
||||
.KEEP_W(KEEP_W),
|
||||
.STRB_EN(STRB_EN),
|
||||
.LAST_EN(LAST_EN),
|
||||
.ID_EN(ID_EN),
|
||||
.ID_W(M_ID_W),
|
||||
.DEST_EN(DEST_EN),
|
||||
.DEST_W(M_DEST_W),
|
||||
.USER_EN(USER_EN),
|
||||
.USER_W(USER_W)
|
||||
) m_axis[M_COUNT]();
|
||||
|
||||
taxi_axis_switch #(
|
||||
.S_COUNT(S_COUNT),
|
||||
.M_COUNT(M_COUNT),
|
||||
.M_BASE(M_BASE),
|
||||
.M_TOP(M_TOP),
|
||||
.AUTO_ADDR(AUTO_ADDR),
|
||||
.M_CONNECT(M_CONNECT),
|
||||
.UPDATE_TID(UPDATE_TID),
|
||||
.S_REG_TYPE(S_REG_TYPE),
|
||||
.M_REG_TYPE(M_REG_TYPE),
|
||||
.ARB_ROUND_ROBIN(ARB_ROUND_ROBIN),
|
||||
.ARB_LSB_HIGH_PRIO(ARB_LSB_HIGH_PRIO)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream inputs (sink)
|
||||
*/
|
||||
.s_axis(s_axis),
|
||||
|
||||
/*
|
||||
* AXI4-Stream outputs (source)
|
||||
*/
|
||||
.m_axis(m_axis)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user