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eth: Re-nest if statements for termination character handling in 10G RX logic

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-10-04 19:01:47 -07:00
parent e395398666
commit 93ef0f970b
4 changed files with 126 additions and 134 deletions
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8
src/eth/rtl/taxi_axis_baser_rx_32.sv
View File

@@ -437,9 +437,7 @@ always_comb begin
stat_rx_pkt_jabber_next = frame_oversize_next; stat_rx_pkt_jabber_next = frame_oversize_next;
reset_crc = 1'b1; reset_crc = 1'b1;
state_next = STATE_IDLE; state_next = STATE_IDLE;
end else if (term_present_reg) begin end else if (term_first_cycle_reg) begin
reset_crc = 1'b1;
if (term_first_cycle_reg) begin
// end this cycle // end this cycle
m_axis_rx_tkeep_next = 4'b1111; m_axis_rx_tkeep_next = 4'b1111;
m_axis_rx_tlast_next = 1'b1; m_axis_rx_tlast_next = 1'b1;
@@ -468,11 +466,11 @@ always_comb begin
stat_rx_pkt_vlan_next = is_8021q_reg; stat_rx_pkt_vlan_next = is_8021q_reg;
stat_rx_err_oversize_next = frame_oversize_next; stat_rx_err_oversize_next = frame_oversize_next;
stat_rx_err_preamble_next = !pre_ok_reg; stat_rx_err_preamble_next = !pre_ok_reg;
reset_crc = 1'b1;
state_next = STATE_IDLE; state_next = STATE_IDLE;
end else begin end else if (term_present_reg) begin
// need extra cycle // need extra cycle
state_next = STATE_LAST; state_next = STATE_LAST;
end
end else begin end else begin
state_next = STATE_PAYLOAD; state_next = STATE_PAYLOAD;
end end

6
src/eth/rtl/taxi_axis_baser_rx_64.sv
View File

@@ -446,8 +446,7 @@ always_comb begin
reset_crc = 1'b1; reset_crc = 1'b1;
state_next = STATE_IDLE; state_next = STATE_IDLE;
end if (term_present_reg) begin end else if (term_first_cycle_reg) begin
if (term_first_cycle_reg) begin
// end this cycle // end this cycle
m_axis_rx_tkeep_next = {KEEP_W{1'b1}} >> 3'(KEEP_W-4-term_lane_reg); m_axis_rx_tkeep_next = {KEEP_W{1'b1}} >> 3'(KEEP_W-4-term_lane_reg);
m_axis_rx_tlast_next = 1'b1; m_axis_rx_tlast_next = 1'b1;
@@ -484,10 +483,9 @@ always_comb begin
reset_crc = 1'b1; reset_crc = 1'b1;
state_next = STATE_IDLE; state_next = STATE_IDLE;
end else begin end else if (term_present_reg) begin
// need extra cycle // need extra cycle
state_next = STATE_LAST; state_next = STATE_LAST;
end
end else begin end else begin
state_next = STATE_PAYLOAD; state_next = STATE_PAYLOAD;
end end

8
src/eth/rtl/taxi_axis_xgmii_rx_32.sv
View File

@@ -395,9 +395,7 @@ always_comb begin
stat_rx_pkt_jabber_next = frame_oversize_next; stat_rx_pkt_jabber_next = frame_oversize_next;
reset_crc = 1'b1; reset_crc = 1'b1;
state_next = STATE_IDLE; state_next = STATE_IDLE;
end else if (term_present_reg) begin end else if (term_first_cycle_reg) begin
reset_crc = 1'b1;
if (term_first_cycle_reg) begin
// end this cycle // end this cycle
m_axis_rx_tkeep_next = 4'b1111; m_axis_rx_tkeep_next = 4'b1111;
m_axis_rx_tlast_next = 1'b1; m_axis_rx_tlast_next = 1'b1;
@@ -426,11 +424,11 @@ always_comb begin
stat_rx_pkt_vlan_next = is_8021q_reg; stat_rx_pkt_vlan_next = is_8021q_reg;
stat_rx_err_oversize_next = frame_oversize_next; stat_rx_err_oversize_next = frame_oversize_next;
stat_rx_err_preamble_next = !pre_ok_reg; stat_rx_err_preamble_next = !pre_ok_reg;
reset_crc = 1'b1;
state_next = STATE_IDLE; state_next = STATE_IDLE;
end else begin end else if (term_present_reg) begin
// need extra cycle // need extra cycle
state_next = STATE_LAST; state_next = STATE_LAST;
end
end else begin end else begin
state_next = STATE_PAYLOAD; state_next = STATE_PAYLOAD;
end end

8
src/eth/rtl/taxi_axis_xgmii_rx_64.sv
View File

@@ -392,9 +392,7 @@ always_comb begin
stat_rx_pkt_jabber_next = frame_oversize_next; stat_rx_pkt_jabber_next = frame_oversize_next;
reset_crc = 1'b1; reset_crc = 1'b1;
state_next = STATE_IDLE; state_next = STATE_IDLE;
end else if (term_present_reg) begin end else if (term_first_cycle_reg) begin
reset_crc = 1'b1;
if (term_first_cycle_reg) begin
// end this cycle // end this cycle
m_axis_rx_tkeep_next = {KEEP_W{1'b1}} >> 3'(CTRL_W-4-term_lane_reg); m_axis_rx_tkeep_next = {KEEP_W{1'b1}} >> 3'(CTRL_W-4-term_lane_reg);
m_axis_rx_tlast_next = 1'b1; m_axis_rx_tlast_next = 1'b1;
@@ -427,11 +425,11 @@ always_comb begin
stat_rx_pkt_vlan_next = is_8021q_reg; stat_rx_pkt_vlan_next = is_8021q_reg;
stat_rx_err_oversize_next = frame_oversize_next; stat_rx_err_oversize_next = frame_oversize_next;
stat_rx_err_preamble_next = !pre_ok_reg; stat_rx_err_preamble_next = !pre_ok_reg;
reset_crc = 1'b1;
state_next = STATE_IDLE; state_next = STATE_IDLE;
end else begin end else if (term_present_reg) begin
// need extra cycle // need extra cycle
state_next = STATE_LAST; state_next = STATE_LAST;
end
end else begin end else begin
state_next = STATE_PAYLOAD; state_next = STATE_PAYLOAD;
end end