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eth: Re-nest if statements for termination character handling in 10G RX logic

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-10-04 19:01:47 -07:00
parent e395398666
commit 93ef0f970b
4 changed files with 126 additions and 134 deletions
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60
src/eth/rtl/taxi_axis_baser_rx_32.sv
View File

@@ -437,42 +437,40 @@ always_comb begin
stat_rx_pkt_jabber_next = frame_oversize_next; stat_rx_pkt_jabber_next = frame_oversize_next;
reset_crc = 1'b1; reset_crc = 1'b1;
state_next = STATE_IDLE; state_next = STATE_IDLE;
end else if (term_present_reg) begin end else if (term_first_cycle_reg) begin
reset_crc = 1'b1; // end this cycle
if (term_first_cycle_reg) begin m_axis_rx_tkeep_next = 4'b1111;
// end this cycle m_axis_rx_tlast_next = 1'b1;
m_axis_rx_tkeep_next = 4'b1111; if (crc_valid_save[3]) begin
m_axis_rx_tlast_next = 1'b1; // CRC valid
if (crc_valid_save[3]) begin if (frame_oversize_next) begin
// CRC valid // too long
if (frame_oversize_next) begin
// too long
m_axis_rx_tuser_next = 1'b1;
stat_rx_pkt_bad_next = 1'b1;
end else begin
// length OK
m_axis_rx_tuser_next = 1'b0;
stat_rx_pkt_good_next = 1'b1;
end
end else begin
m_axis_rx_tuser_next = 1'b1; m_axis_rx_tuser_next = 1'b1;
stat_rx_pkt_fragment_next = frame_len_next[15:6] == 0;
stat_rx_pkt_jabber_next = frame_oversize_next;
stat_rx_pkt_bad_next = 1'b1; stat_rx_pkt_bad_next = 1'b1;
stat_rx_err_bad_fcs_next = 1'b1; end else begin
// length OK
m_axis_rx_tuser_next = 1'b0;
stat_rx_pkt_good_next = 1'b1;
end end
stat_rx_pkt_len_next = frame_len_next;
stat_rx_pkt_ucast_next = !is_mcast_reg;
stat_rx_pkt_mcast_next = is_mcast_reg && !is_bcast_reg;
stat_rx_pkt_bcast_next = is_bcast_reg;
stat_rx_pkt_vlan_next = is_8021q_reg;
stat_rx_err_oversize_next = frame_oversize_next;
stat_rx_err_preamble_next = !pre_ok_reg;
state_next = STATE_IDLE;
end else begin end else begin
// need extra cycle m_axis_rx_tuser_next = 1'b1;
state_next = STATE_LAST; stat_rx_pkt_fragment_next = frame_len_next[15:6] == 0;
stat_rx_pkt_jabber_next = frame_oversize_next;
stat_rx_pkt_bad_next = 1'b1;
stat_rx_err_bad_fcs_next = 1'b1;
end end
stat_rx_pkt_len_next = frame_len_next;
stat_rx_pkt_ucast_next = !is_mcast_reg;
stat_rx_pkt_mcast_next = is_mcast_reg && !is_bcast_reg;
stat_rx_pkt_bcast_next = is_bcast_reg;
stat_rx_pkt_vlan_next = is_8021q_reg;
stat_rx_err_oversize_next = frame_oversize_next;
stat_rx_err_preamble_next = !pre_ok_reg;
reset_crc = 1'b1;
state_next = STATE_IDLE;
end else if (term_present_reg) begin
// need extra cycle
state_next = STATE_LAST;
end else begin end else begin
state_next = STATE_PAYLOAD; state_next = STATE_PAYLOAD;
end end

72
src/eth/rtl/taxi_axis_baser_rx_64.sv
View File

@@ -446,48 +446,46 @@ always_comb begin
reset_crc = 1'b1; reset_crc = 1'b1;
state_next = STATE_IDLE; state_next = STATE_IDLE;
end if (term_present_reg) begin end else if (term_first_cycle_reg) begin
if (term_first_cycle_reg) begin // end this cycle
// end this cycle m_axis_rx_tkeep_next = {KEEP_W{1'b1}} >> 3'(KEEP_W-4-term_lane_reg);
m_axis_rx_tkeep_next = {KEEP_W{1'b1}} >> 3'(KEEP_W-4-term_lane_reg); m_axis_rx_tlast_next = 1'b1;
m_axis_rx_tlast_next = 1'b1; if ((term_lane_reg == 0 && crc_valid_save[7]) ||
if ((term_lane_reg == 0 && crc_valid_save[7]) || (term_lane_reg == 1 && crc_valid[0]) ||
(term_lane_reg == 1 && crc_valid[0]) || (term_lane_reg == 2 && crc_valid[1]) ||
(term_lane_reg == 2 && crc_valid[1]) || (term_lane_reg == 3 && crc_valid[2]) ||
(term_lane_reg == 3 && crc_valid[2]) || (term_lane_reg == 4 && crc_valid[3])) begin
(term_lane_reg == 4 && crc_valid[3])) begin // CRC valid
// CRC valid if (frame_oversize_next) begin
if (frame_oversize_next) begin // too long
// too long
m_axis_rx_tuser_next = 1'b1;
stat_rx_pkt_bad_next = 1'b1;
end else begin
// length OK
m_axis_rx_tuser_next = 1'b0;
stat_rx_pkt_good_next = 1'b1;
end
end else begin
m_axis_rx_tuser_next = 1'b1; m_axis_rx_tuser_next = 1'b1;
stat_rx_pkt_fragment_next = frame_len_next[15:6] == 0;
stat_rx_pkt_jabber_next = frame_oversize_next;
stat_rx_pkt_bad_next = 1'b1; stat_rx_pkt_bad_next = 1'b1;
stat_rx_err_bad_fcs_next = 1'b1; end else begin
// length OK
m_axis_rx_tuser_next = 1'b0;
stat_rx_pkt_good_next = 1'b1;
end end
stat_rx_pkt_len_next = frame_len_next;
stat_rx_pkt_ucast_next = !is_mcast_reg;
stat_rx_pkt_mcast_next = is_mcast_reg && !is_bcast_reg;
stat_rx_pkt_bcast_next = is_bcast_reg;
stat_rx_pkt_vlan_next = is_8021q_reg;
stat_rx_err_oversize_next = frame_oversize_next;
stat_rx_err_preamble_next = !pre_ok_reg;
reset_crc = 1'b1;
state_next = STATE_IDLE;
end else begin end else begin
// need extra cycle m_axis_rx_tuser_next = 1'b1;
state_next = STATE_LAST; stat_rx_pkt_fragment_next = frame_len_next[15:6] == 0;
stat_rx_pkt_jabber_next = frame_oversize_next;
stat_rx_pkt_bad_next = 1'b1;
stat_rx_err_bad_fcs_next = 1'b1;
end end
stat_rx_pkt_len_next = frame_len_next;
stat_rx_pkt_ucast_next = !is_mcast_reg;
stat_rx_pkt_mcast_next = is_mcast_reg && !is_bcast_reg;
stat_rx_pkt_bcast_next = is_bcast_reg;
stat_rx_pkt_vlan_next = is_8021q_reg;
stat_rx_err_oversize_next = frame_oversize_next;
stat_rx_err_preamble_next = !pre_ok_reg;
reset_crc = 1'b1;
state_next = STATE_IDLE;
end else if (term_present_reg) begin
// need extra cycle
state_next = STATE_LAST;
end else begin end else begin
state_next = STATE_PAYLOAD; state_next = STATE_PAYLOAD;
end end

60
src/eth/rtl/taxi_axis_xgmii_rx_32.sv
View File

@@ -395,42 +395,40 @@ always_comb begin
stat_rx_pkt_jabber_next = frame_oversize_next; stat_rx_pkt_jabber_next = frame_oversize_next;
reset_crc = 1'b1; reset_crc = 1'b1;
state_next = STATE_IDLE; state_next = STATE_IDLE;
end else if (term_present_reg) begin end else if (term_first_cycle_reg) begin
reset_crc = 1'b1; // end this cycle
if (term_first_cycle_reg) begin m_axis_rx_tkeep_next = 4'b1111;
// end this cycle m_axis_rx_tlast_next = 1'b1;
m_axis_rx_tkeep_next = 4'b1111; if (crc_valid_save[3]) begin
m_axis_rx_tlast_next = 1'b1; // CRC valid
if (crc_valid_save[3]) begin if (frame_oversize_next) begin
// CRC valid // too long
if (frame_oversize_next) begin
// too long
m_axis_rx_tuser_next = 1'b1;
stat_rx_pkt_bad_next = 1'b1;
end else begin
// length OK
m_axis_rx_tuser_next = 1'b0;
stat_rx_pkt_good_next = 1'b1;
end
end else begin
m_axis_rx_tuser_next = 1'b1; m_axis_rx_tuser_next = 1'b1;
stat_rx_pkt_fragment_next = frame_len_next[15:6] == 0;
stat_rx_pkt_jabber_next = frame_oversize_next;
stat_rx_pkt_bad_next = 1'b1; stat_rx_pkt_bad_next = 1'b1;
stat_rx_err_bad_fcs_next = 1'b1; end else begin
// length OK
m_axis_rx_tuser_next = 1'b0;
stat_rx_pkt_good_next = 1'b1;
end end
stat_rx_pkt_len_next = frame_len_next;
stat_rx_pkt_ucast_next = !is_mcast_reg;
stat_rx_pkt_mcast_next = is_mcast_reg && !is_bcast_reg;
stat_rx_pkt_bcast_next = is_bcast_reg;
stat_rx_pkt_vlan_next = is_8021q_reg;
stat_rx_err_oversize_next = frame_oversize_next;
stat_rx_err_preamble_next = !pre_ok_reg;
state_next = STATE_IDLE;
end else begin end else begin
// need extra cycle m_axis_rx_tuser_next = 1'b1;
state_next = STATE_LAST; stat_rx_pkt_fragment_next = frame_len_next[15:6] == 0;
stat_rx_pkt_jabber_next = frame_oversize_next;
stat_rx_pkt_bad_next = 1'b1;
stat_rx_err_bad_fcs_next = 1'b1;
end end
stat_rx_pkt_len_next = frame_len_next;
stat_rx_pkt_ucast_next = !is_mcast_reg;
stat_rx_pkt_mcast_next = is_mcast_reg && !is_bcast_reg;
stat_rx_pkt_bcast_next = is_bcast_reg;
stat_rx_pkt_vlan_next = is_8021q_reg;
stat_rx_err_oversize_next = frame_oversize_next;
stat_rx_err_preamble_next = !pre_ok_reg;
reset_crc = 1'b1;
state_next = STATE_IDLE;
end else if (term_present_reg) begin
// need extra cycle
state_next = STATE_LAST;
end else begin end else begin
state_next = STATE_PAYLOAD; state_next = STATE_PAYLOAD;
end end

68
src/eth/rtl/taxi_axis_xgmii_rx_64.sv
View File

@@ -392,46 +392,44 @@ always_comb begin
stat_rx_pkt_jabber_next = frame_oversize_next; stat_rx_pkt_jabber_next = frame_oversize_next;
reset_crc = 1'b1; reset_crc = 1'b1;
state_next = STATE_IDLE; state_next = STATE_IDLE;
end else if (term_present_reg) begin end else if (term_first_cycle_reg) begin
reset_crc = 1'b1; // end this cycle
if (term_first_cycle_reg) begin m_axis_rx_tkeep_next = {KEEP_W{1'b1}} >> 3'(CTRL_W-4-term_lane_reg);
// end this cycle m_axis_rx_tlast_next = 1'b1;
m_axis_rx_tkeep_next = {KEEP_W{1'b1}} >> 3'(CTRL_W-4-term_lane_reg); if ((term_lane_reg == 0 && crc_valid_save[7]) ||
m_axis_rx_tlast_next = 1'b1; (term_lane_reg == 1 && crc_valid[0]) ||
if ((term_lane_reg == 0 && crc_valid_save[7]) || (term_lane_reg == 2 && crc_valid[1]) ||
(term_lane_reg == 1 && crc_valid[0]) || (term_lane_reg == 3 && crc_valid[2]) ||
(term_lane_reg == 2 && crc_valid[1]) || (term_lane_reg == 4 && crc_valid[3])) begin
(term_lane_reg == 3 && crc_valid[2]) || // CRC valid
(term_lane_reg == 4 && crc_valid[3])) begin if (frame_oversize_next) begin
// CRC valid // too long
if (frame_oversize_next) begin
// too long
m_axis_rx_tuser_next = 1'b1;
stat_rx_pkt_bad_next = 1'b1;
end else begin
// length OK
m_axis_rx_tuser_next = 1'b0;
stat_rx_pkt_good_next = 1'b1;
end
end else begin
m_axis_rx_tuser_next = 1'b1; m_axis_rx_tuser_next = 1'b1;
stat_rx_pkt_fragment_next = frame_len_next[15:6] == 0;
stat_rx_pkt_jabber_next = frame_oversize_next;
stat_rx_pkt_bad_next = 1'b1; stat_rx_pkt_bad_next = 1'b1;
stat_rx_err_bad_fcs_next = 1'b1; end else begin
// length OK
m_axis_rx_tuser_next = 1'b0;
stat_rx_pkt_good_next = 1'b1;
end end
stat_rx_pkt_len_next = frame_len_next;
stat_rx_pkt_ucast_next = !is_mcast_reg;
stat_rx_pkt_mcast_next = is_mcast_reg && !is_bcast_reg;
stat_rx_pkt_bcast_next = is_bcast_reg;
stat_rx_pkt_vlan_next = is_8021q_reg;
stat_rx_err_oversize_next = frame_oversize_next;
stat_rx_err_preamble_next = !pre_ok_reg;
state_next = STATE_IDLE;
end else begin end else begin
// need extra cycle m_axis_rx_tuser_next = 1'b1;
state_next = STATE_LAST; stat_rx_pkt_fragment_next = frame_len_next[15:6] == 0;
stat_rx_pkt_jabber_next = frame_oversize_next;
stat_rx_pkt_bad_next = 1'b1;
stat_rx_err_bad_fcs_next = 1'b1;
end end
stat_rx_pkt_len_next = frame_len_next;
stat_rx_pkt_ucast_next = !is_mcast_reg;
stat_rx_pkt_mcast_next = is_mcast_reg && !is_bcast_reg;
stat_rx_pkt_bcast_next = is_bcast_reg;
stat_rx_pkt_vlan_next = is_8021q_reg;
stat_rx_err_oversize_next = frame_oversize_next;
stat_rx_err_preamble_next = !pre_ok_reg;
reset_crc = 1'b1;
state_next = STATE_IDLE;
end else if (term_present_reg) begin
// need extra cycle
state_next = STATE_LAST;
end else begin end else begin
state_next = STATE_PAYLOAD; state_next = STATE_PAYLOAD;
end end