example/ADM_PCIE_9V3: Add example design for ADM-PCIE-9V3

Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-12-07 16:28:40 -08:00 · 2025-02-23 00:49:41 -08:00
parent 9a8f311f2c
commit 951f81680a
12 changed files with 1862 additions and 0 deletions
--- a/README.md
+++ b/README.md
@@ -92,6 +92,7 @@ To facilitate the dual-license model, contributions to the project can only be a

 Example designs are provided for several different FPGA boards, showcasing many of the capabilities of this library.  Building the example designs will require the appropriate vendor toolchain and may also require tool and IP licenses.

+*  Alpha Data ADM-PCIE-9V3 (Xilinx Virtex UltraScale+ XCVU3P)
 *  Digilent Arty A7 (Xilinx Artix 7 XC7A35T)
 *  HiTech Global HTG-940 (Xilinx Virtex UltraScale+ XCVU9P/XCVU13P)
 *  Xilinx KC705 (Xilinx Kintex 7 XC7K325T)
--- a/example/ADM_PCIE_9V3/fpga/README.md
+++ b/example/ADM_PCIE_9V3/fpga/README.md
@@ -0,0 +1,32 @@
+# Taxi Example Design for ADM-PCIE-9V3
+
+## Introduction
+
+This example design targets the Alpha Data ADM-PCIE-9V3 FPGA board.
+
+The design places looped-back MACs on the QSFP28 ports.
+
+*  QSFP28
+    *  Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers
+
+## Board details
+
+*  FPGA: xcvu3p-ffvc1517-2-i
+*  25GBASE-R PHY: Soft PCS with GTY transceivers
+
+## Licensing
+
+*  Toolchain
+    *  Vivado Enterprise (requires license)
+*  IP
+    *  No licensed vendor IP or 3rd party IP
+
+## How to build
+
+Run `make` in the appropriate `fpga*` subdirectory to build the bitstream.  Ensure that the Xilinx Vivado toolchain components are in PATH.
+
+## How to test
+
+Run `make program` to program the board with Vivado.
+
+To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback.  Do not connect the looped-back MAC to a network as the reflected packets may cause problems.
--- a/example/ADM_PCIE_9V3/fpga/common/vivado.mk
+++ b/example/ADM_PCIE_9V3/fpga/common/vivado.mk
@@ -0,0 +1,153 @@
+# SPDX-License-Identifier: MIT
+###################################################################
+#
+# Xilinx Vivado FPGA Makefile
+#
+# Copyright (c) 2016-2025 Alex Forencich
+#
+###################################################################
+#
+# Parameters:
+# FPGA_TOP - Top module name
+# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
+# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
+# SYN_FILES - list of source files
+# INC_FILES - list of include files
+# XDC_FILES - list of timing constraint files
+# XCI_FILES - list of IP XCI files
+# IP_TCL_FILES - list of IP TCL files (sourced during project creation)
+# CONFIG_TCL_FILES - list of config TCL files (sourced before each build)
+#
+# Note: both SYN_FILES and INC_FILES support file list files.  File list
+# files are files with a .f extension that contain a list of additional
+# files to include, one path relative to the .f file location per line.
+# The .f files are processed recursively, and then the complete file list
+# is de-duplicated, with later files in the list taking precedence.
+#
+# Example:
+#
+# FPGA_TOP = fpga
+# FPGA_FAMILY = VirtexUltrascale
+# FPGA_DEVICE = xcvu095-ffva2104-2-e
+# SYN_FILES = rtl/fpga.v
+# XDC_FILES = fpga.xdc
+# XCI_FILES = ip/pcspma.xci
+# include ../common/vivado.mk
+#
+###################################################################
+
+# phony targets
+.PHONY: fpga vivado tmpclean clean distclean
+
+# prevent make from deleting intermediate files and reports
+.PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm
+.SECONDARY:
+
+CONFIG ?= config.mk
+-include $(CONFIG)
+
+FPGA_TOP ?= fpga
+PROJECT ?= $(FPGA_TOP)
+XDC_FILES ?= $(PROJECT).xdc
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES)))
+INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES)))
+
+###################################################################
+# Main Targets
+#
+# all: build everything (fpga)
+# fpga: build FPGA config
+# vivado: open project in Vivado
+# tmpclean: remove intermediate files
+# clean: remove output files and project files
+# distclean: remove archived output files
+###################################################################
+
+all: fpga
+
+fpga: $(PROJECT).bit
+
+vivado: $(PROJECT).xpr
+	vivado $(PROJECT).xpr
+
+tmpclean::
+	-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
+	-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
+
+clean:: tmpclean
+	-rm -rf *.bit *.bin *.ltx *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
+	-rm -rf *_utilization.rpt *_utilization_hierarchical.rpt
+
+distclean:: clean
+	-rm -rf rev
+
+###################################################################
+# Target implementations
+###################################################################
+
+# Vivado project file
+
+# create fresh project if Makefile or IP files have changed
+create_project.tcl: Makefile $(XCI_FILES) $(IP_TCL_FILES)
+	rm -rf defines.v
+	touch defines.v
+	for x in $(DEFS); do echo '`define' $$x >> defines.v; done
+	echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@
+	echo "add_files -fileset sources_1 defines.v $(SYN_FILES)" >> $@
+	echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@
+	echo "add_files -fileset constrs_1 $(XDC_FILES)" >> $@
+	for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done
+	for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done
+	for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
+
+# source config TCL scripts if any source file has changed
+update_config.tcl: $(CONFIG_TCL_FILES) $(SYN_FILES) $(INC_FILES) $(XDC_FILES)
+	echo "open_project -quiet $(PROJECT).xpr" > $@
+	for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
+
+$(PROJECT).xpr: create_project.tcl update_config.tcl
+	vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
+
+# synthesis run
+$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES) $(INC_FILES) $(XDC_FILES) | $(PROJECT).xpr
+	echo "open_project $(PROJECT).xpr" > run_synth.tcl
+	echo "reset_run synth_1" >> run_synth.tcl
+	echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
+	echo "wait_on_run synth_1" >> run_synth.tcl
+	vivado -nojournal -nolog -mode batch -source run_synth.tcl
+
+# implementation run
+$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp
+	echo "open_project $(PROJECT).xpr" > run_impl.tcl
+	echo "reset_run impl_1" >> run_impl.tcl
+	echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
+	echo "wait_on_run impl_1" >> run_impl.tcl
+	echo "open_run impl_1" >> run_impl.tcl
+	echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl
+	echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl
+	vivado -nojournal -nolog -mode batch -source run_impl.tcl
+
+# output files (including potentially bit, bin, ltx, and xsa)
+$(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp
+	echo "open_project $(PROJECT).xpr" > generate_bit.tcl
+	echo "open_run impl_1" >> generate_bit.tcl
+	echo "write_bitstream -force -bin_file $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl
+	echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl
+	echo "write_hw_platform -fixed -force -include_bit $(PROJECT).xsa" >> generate_bit.tcl
+	vivado -nojournal -nolog -mode batch -source generate_bit.tcl
+	ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit .
+	ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bin .
+	if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \
+	cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \
+	if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \
+	if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi
--- a/example/ADM_PCIE_9V3/fpga/fpga.xdc
+++ b/example/ADM_PCIE_9V3/fpga/fpga.xdc
@@ -0,0 +1,490 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2014-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# XDC constraints for the ADM-PCIE-9V3
+# part: xcvu3p-ffvc1517-2-i
+
+# General configuration
+set_property CFGBVS GND                                [current_design]
+set_property CONFIG_VOLTAGE 1.8                        [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
+set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
+set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES       [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8           [current_design]
+set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
+set_property BITSTREAM.CONFIG.UNUSEDPIN {Pullnone}     [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
+
+# 300 MHz system clock
+set_property -dict {LOC AP26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_300mhz_p]
+set_property -dict {LOC AP27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_300mhz_n]
+create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p]
+
+# LEDs
+set_property -dict {LOC AT27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {user_led_g[0]}]
+set_property -dict {LOC AU27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {user_led_g[1]}]
+set_property -dict {LOC AU23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {user_led_r}]
+set_property -dict {LOC AH24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {front_led[0]}]
+set_property -dict {LOC AJ23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {front_led[1]}]
+
+set_false_path -to [get_ports {user_led_g[*] user_led_r front_led[*]}]
+set_output_delay 0 [get_ports {user_led_g[*] user_led_r front_led[*]}]
+
+# Switches
+set_property -dict {LOC AV27 IOSTANDARD LVCMOS18} [get_ports {user_sw[0]}]
+set_property -dict {LOC AW27 IOSTANDARD LVCMOS18} [get_ports {user_sw[1]}]
+
+set_false_path -from [get_ports {user_sw[*]}]
+set_input_delay 0 [get_ports {user_sw[*]}]
+
+# GPIO
+#set_property -dict {LOC G30  IOSTANDARD LVCMOS18} [get_ports gpio_p[0]]
+#set_property -dict {LOC F30  IOSTANDARD LVCMOS18} [get_ports gpio_n[0]]
+#set_property -dict {LOC J31  IOSTANDARD LVCMOS18} [get_ports gpio_p[1]]
+#set_property -dict {LOC H31  IOSTANDARD LVCMOS18} [get_ports gpio_n[1]]
+
+# QSFP28 Interfaces
+set_property -dict {LOC G38  } [get_ports {qsfp_0_rx_p[0]}] ;# MGTYRXP0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
+set_property -dict {LOC G39  } [get_ports {qsfp_0_rx_n[0]}] ;# MGTYRXN0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
+set_property -dict {LOC F35  } [get_ports {qsfp_0_tx_p[0]}] ;# MGTYTXP0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
+set_property -dict {LOC F36  } [get_ports {qsfp_0_tx_n[0]}] ;# MGTYTXN0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
+set_property -dict {LOC E38  } [get_ports {qsfp_0_rx_p[1]}] ;# MGTYRXP1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
+set_property -dict {LOC E39  } [get_ports {qsfp_0_rx_n[1]}] ;# MGTYRXN1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
+set_property -dict {LOC D35  } [get_ports {qsfp_0_tx_p[1]}] ;# MGTYTXP1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
+set_property -dict {LOC D36  } [get_ports {qsfp_0_tx_n[1]}] ;# MGTYTXN1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
+set_property -dict {LOC C38  } [get_ports {qsfp_0_rx_p[2]}] ;# MGTYRXP2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
+set_property -dict {LOC C39  } [get_ports {qsfp_0_rx_n[2]}] ;# MGTYRXN2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
+set_property -dict {LOC C33  } [get_ports {qsfp_0_tx_p[2]}] ;# MGTYTXP2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
+set_property -dict {LOC C34  } [get_ports {qsfp_0_tx_n[2]}] ;# MGTYTXN2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
+set_property -dict {LOC B36  } [get_ports {qsfp_0_rx_p[3]}] ;# MGTYRXP3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
+set_property -dict {LOC B37  } [get_ports {qsfp_0_rx_n[3]}] ;# MGTYRXN3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
+set_property -dict {LOC A33  } [get_ports {qsfp_0_tx_p[3]}] ;# MGTYTXP3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
+set_property -dict {LOC A34  } [get_ports {qsfp_0_tx_n[3]}] ;# MGTYTXN3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
+set_property -dict {LOC N33  } [get_ports qsfp_0_mgt_refclk_p] ;# MGTREFCLK0P_128 from ?
+set_property -dict {LOC N34  } [get_ports qsfp_0_mgt_refclk_n] ;# MGTREFCLK0N_128 from ?
+set_property -dict {LOC F29  IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_0_modprs_l]
+set_property -dict {LOC D31  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports qsfp_0_sel_l]
+
+# 161.1328125 MHz MGT reference clock
+create_clock -period 6.206 -name qsfp_0_mgt_refclk [get_ports qsfp_0_mgt_refclk_p]
+
+set_property -dict {LOC R38  } [get_ports {qsfp_1_rx_p[0]}] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
+set_property -dict {LOC R39  } [get_ports {qsfp_1_rx_n[0]}] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
+set_property -dict {LOC P35  } [get_ports {qsfp_1_tx_p[0]}] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
+set_property -dict {LOC P36  } [get_ports {qsfp_1_tx_n[0]}] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
+set_property -dict {LOC N38  } [get_ports {qsfp_1_rx_p[1]}] ;# MGTYRXP1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
+set_property -dict {LOC N39  } [get_ports {qsfp_1_rx_n[1]}] ;# MGTYRXN1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
+set_property -dict {LOC M35  } [get_ports {qsfp_1_tx_p[1]}] ;# MGTYTXP1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
+set_property -dict {LOC M36  } [get_ports {qsfp_1_tx_n[1]}] ;# MGTYTXN1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
+set_property -dict {LOC L38  } [get_ports {qsfp_1_rx_p[2]}] ;# MGTYRXP2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
+set_property -dict {LOC L39  } [get_ports {qsfp_1_rx_n[2]}] ;# MGTYRXN2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
+set_property -dict {LOC K35  } [get_ports {qsfp_1_tx_p[2]}] ;# MGTYTXP2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
+set_property -dict {LOC K36  } [get_ports {qsfp_1_tx_n[2]}] ;# MGTYTXN2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
+set_property -dict {LOC J38  } [get_ports {qsfp_1_rx_p[3]}] ;# MGTYRXP3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
+set_property -dict {LOC J39  } [get_ports {qsfp_1_rx_n[3]}] ;# MGTYRXN3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
+set_property -dict {LOC H35  } [get_ports {qsfp_1_tx_p[3]}] ;# MGTYTXP3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
+set_property -dict {LOC H36  } [get_ports {qsfp_1_tx_n[3]}] ;# MGTYTXN3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
+#set_property -dict {LOC U33  } [get_ports qsfp_1_mgt_refclk_p] ;# MGTREFCLK0P_127 from ?
+#set_property -dict {LOC U34  } [get_ports qsfp_1_mgt_refclk_n] ;# MGTREFCLK0N_127 from ?
+set_property -dict {LOC F33  IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_1_modprs_l]
+set_property -dict {LOC D30  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports qsfp_1_sel_l]
+
+# 161.1328125 MHz MGT reference clock
+#create_clock -period 6.206 -name qsfp_1_mgt_refclk [get_ports qsfp_1_mgt_refclk_p]
+
+set_property -dict {LOC B29  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports qsfp_reset_l]
+set_property -dict {LOC C29  IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_int_l]
+#set_property -dict {LOC A28  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports qsfp_i2c_scl]
+#set_property -dict {LOC A29  IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports qsfp_i2c_sda]
+
+set_false_path -to [get_ports {qsfp_0_sel_l qsfp_1_sel_l qsfp_reset_l}]
+set_output_delay 0 [get_ports {qsfp_0_sel_l qsfp_1_sel_l qsfp_reset_l}]
+set_false_path -from [get_ports {qsfp_0_modprs_l qsfp_1_modprs_l qsfp_int_l}]
+set_input_delay 0 [get_ports {qsfp_0_modprs_l qsfp_1_modprs_l qsfp_int_l}]
+
+#set_false_path -to [get_ports {qsfp_i2c_sda qsfp_i2c_scl}]
+#set_output_delay 0 [get_ports {qsfp_i2c_sda qsfp_i2c_scl}]
+#set_false_path -from [get_ports {qsfp_i2c_sda qsfp_i2c_scl}]
+#set_input_delay 0 [get_ports {qsfp_i2c_sda qsfp_i2c_scl}]
+
+# I2C interface
+#set_property -dict {LOC AT25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports eeprom_i2c_scl]
+#set_property -dict {LOC AT26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports eeprom_i2c_sda]
+#set_property -dict {LOC AP23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports eeprom_wp]
+
+#set_false_path -to [get_ports {eeprom_i2c_sda eeprom_i2c_scl eeprom_wp}]
+#set_output_delay 0 [get_ports {eeprom_i2c_sda eeprom_i2c_scl eeprom_wp}]
+#set_false_path -from [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
+#set_input_delay 0 [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
+
+# PCIe Interface
+#set_property -dict {LOC J2   } [get_ports {pcie_rx_p[0]}]  ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
+#set_property -dict {LOC J1   } [get_ports {pcie_rx_n[0]}]  ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
+#set_property -dict {LOC H5   } [get_ports {pcie_tx_p[0]}]  ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
+#set_property -dict {LOC H4   } [get_ports {pcie_tx_n[0]}]  ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
+#set_property -dict {LOC L2   } [get_ports {pcie_rx_p[1]}]  ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
+#set_property -dict {LOC L1   } [get_ports {pcie_rx_n[1]}]  ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
+#set_property -dict {LOC K5   } [get_ports {pcie_tx_p[1]}]  ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
+#set_property -dict {LOC K4   } [get_ports {pcie_tx_n[1]}]  ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
+#set_property -dict {LOC N2   } [get_ports {pcie_rx_p[2]}]  ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
+#set_property -dict {LOC N1   } [get_ports {pcie_rx_n[2]}]  ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
+#set_property -dict {LOC M5   } [get_ports {pcie_tx_p[2]}]  ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
+#set_property -dict {LOC M4   } [get_ports {pcie_tx_n[2]}]  ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
+#set_property -dict {LOC R2   } [get_ports {pcie_rx_p[3]}]  ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
+#set_property -dict {LOC R1   } [get_ports {pcie_rx_n[3]}]  ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
+#set_property -dict {LOC P5   } [get_ports {pcie_tx_p[3]}]  ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
+#set_property -dict {LOC P4   } [get_ports {pcie_tx_n[3]}]  ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
+#set_property -dict {LOC U2   } [get_ports {pcie_rx_p[4]}]  ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
+#set_property -dict {LOC U1   } [get_ports {pcie_rx_n[4]}]  ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
+#set_property -dict {LOC T5   } [get_ports {pcie_tx_p[4]}]  ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
+#set_property -dict {LOC T4   } [get_ports {pcie_tx_n[4]}]  ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
+#set_property -dict {LOC W2   } [get_ports {pcie_rx_p[5]}]  ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
+#set_property -dict {LOC W1   } [get_ports {pcie_rx_n[5]}]  ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
+#set_property -dict {LOC V5   } [get_ports {pcie_tx_p[5]}]  ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
+#set_property -dict {LOC V4   } [get_ports {pcie_tx_n[5]}]  ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
+#set_property -dict {LOC AA2  } [get_ports {pcie_rx_p[6]}]  ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
+#set_property -dict {LOC AA1  } [get_ports {pcie_rx_n[6]}]  ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
+#set_property -dict {LOC AB5  } [get_ports {pcie_tx_p[6]}]  ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
+#set_property -dict {LOC AB4  } [get_ports {pcie_tx_n[6]}]  ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
+#set_property -dict {LOC AC2  } [get_ports {pcie_rx_p[7]}]  ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
+#set_property -dict {LOC AC1  } [get_ports {pcie_rx_n[7]}]  ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
+#set_property -dict {LOC AD5  } [get_ports {pcie_tx_p[7]}]  ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
+#set_property -dict {LOC AD4  } [get_ports {pcie_tx_n[7]}]  ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
+#set_property -dict {LOC AE2  } [get_ports {pcie_rx_p[8]}]  ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
+#set_property -dict {LOC AE1  } [get_ports {pcie_rx_n[8]}]  ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
+#set_property -dict {LOC AF5  } [get_ports {pcie_tx_p[8]}]  ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
+#set_property -dict {LOC AF4  } [get_ports {pcie_tx_n[8]}]  ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
+#set_property -dict {LOC AG2  } [get_ports {pcie_rx_p[9]}]  ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
+#set_property -dict {LOC AG1  } [get_ports {pcie_rx_n[9]}]  ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
+#set_property -dict {LOC AH5  } [get_ports {pcie_tx_p[9]}]  ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
+#set_property -dict {LOC AH4  } [get_ports {pcie_tx_n[9]}]  ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
+#set_property -dict {LOC AJ2  } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
+#set_property -dict {LOC AJ1  } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
+#set_property -dict {LOC AK5  } [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
+#set_property -dict {LOC AK4  } [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
+#set_property -dict {LOC AL2  } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
+#set_property -dict {LOC AL1  } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
+#set_property -dict {LOC AM5  } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
+#set_property -dict {LOC AM4  } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
+#set_property -dict {LOC AN2  } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
+#set_property -dict {LOC AN1  } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
+#set_property -dict {LOC AP5  } [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
+#set_property -dict {LOC AP4  } [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
+#set_property -dict {LOC AR2  } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
+#set_property -dict {LOC AR1  } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
+#set_property -dict {LOC AT5  } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
+#set_property -dict {LOC AT4  } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
+#set_property -dict {LOC AU2  } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
+#set_property -dict {LOC AU1  } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
+#set_property -dict {LOC AU7  } [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
+#set_property -dict {LOC AU6  } [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
+#set_property -dict {LOC AV4  } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
+#set_property -dict {LOC AV3  } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
+#set_property -dict {LOC AW7  } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
+#set_property -dict {LOC AW6  } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
+#set_property -dict {LOC AA7  } [get_ports pcie_refclk_1_p] ;# MGTREFCLK0P_226
+#set_property -dict {LOC AA6  } [get_ports pcie_refclk_1_n] ;# MGTREFCLK0N_226
+#set_property -dict {LOC AJ7  } [get_ports pcie_refclk_2_p] ;# MGTREFCLK0P_224
+#set_property -dict {LOC AJ6  } [get_ports pcie_refclk_2_n] ;# MGTREFCLK0N_224
+#set_property -dict {LOC AJ31 IOSTANDARD LVCMOS18 PULLUP true} [get_ports perst_0]
+#set_property -dict {LOC AH29 IOSTANDARD LVCMOS18 PULLUP true} [get_ports perst_1]
+
+# 100 MHz MGT reference clock
+#create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_1_p]
+#create_clock -period 10 -name pcie_mgt_refclk_2 [get_ports pcie_refclk_2_p]
+
+#set_false_path -from [get_ports {perst_0}]
+#set_input_delay 0 [get_ports {perst_0}]
+
+# DDR4 C0
+# 5x K4A8G085WB-RC
+#set_property -dict {LOC F9   IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c0_adr[0]}]
+#set_property -dict {LOC G9   IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c0_adr[1]}]
+#set_property -dict {LOC G11  IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c0_adr[2]}]
+#set_property -dict {LOC D11  IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c0_adr[3]}]
+#set_property -dict {LOC E12  IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c0_adr[4]}]
+#set_property -dict {LOC G10  IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c0_adr[5]}]
+#set_property -dict {LOC F10  IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c0_adr[6]}]
+#set_property -dict {LOC J9   IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c0_adr[7]}]
+#set_property -dict {LOC J8   IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c0_adr[8]}]
+#set_property -dict {LOC F12  IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c0_adr[9]}]
+#set_property -dict {LOC D9   IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c0_adr[10]}]
+#set_property -dict {LOC H11  IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c0_adr[11]}]
+#set_property -dict {LOC E8   IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c0_adr[12]}]
+#set_property -dict {LOC J11  IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c0_adr[13]}]
+#set_property -dict {LOC C9   IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c0_adr[14]}]
+#set_property -dict {LOC B11  IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c0_adr[15]}]
+#set_property -dict {LOC K12  IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c0_adr[16]}]
+#set_property -dict {LOC H9   IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c0_adr[17]}]
+#set_property -dict {LOC F8   IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c0_ba[0]}]
+#set_property -dict {LOC H8   IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c0_ba[1]}]
+#set_property -dict {LOC D10  IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c0_bg[0]}]
+#set_property -dict {LOC E11  IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c0_bg[1]}]
+#set_property -dict {LOC B10  IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c0_c[0]}]
+#set_property -dict {LOC C11  IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c0_c[1]}]
+#set_property -dict {LOC A9   IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c0_c[2]}]
+#set_property -dict {LOC H12  IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t}]
+#set_property -dict {LOC G12  IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c}]
+#set_property -dict {LOC B9   IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c0_cke}]
+#set_property -dict {LOC E10  IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c0_cs_n}]
+#set_property -dict {LOC C12  IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c0_act_n}]
+#set_property -dict {LOC A10  IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c0_odt}]
+#set_property -dict {LOC G7   IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c0_par}]
+#set_property -dict {LOC F7   IOSTANDARD LVCMOS12       } [get_ports {ddr4_c0_reset_n}]
+#set_property -dict {LOC H7   IOSTANDARD LVCMOS12       } [get_ports {ddr4_c0_alert_n}]
+#set_property -dict {LOC J10  IOSTANDARD LVCMOS12       } [get_ports {ddr4_c0_ten}]
+
+#set_property -dict {LOC L10  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[0]}]
+#set_property -dict {LOC L9   IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[1]}]
+#set_property -dict {LOC N9   IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[2]}]
+#set_property -dict {LOC M9   IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[3]}]
+#set_property -dict {LOC M10  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[4]}]
+#set_property -dict {LOC K11  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[5]}]
+#set_property -dict {LOC M11  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[6]}]
+#set_property -dict {LOC K10  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[7]}]
+#set_property -dict {LOC L17  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[8]}]
+#set_property -dict {LOC M16  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[9]}]
+#set_property -dict {LOC M15  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[10]}]
+#set_property -dict {LOC M17  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[11]}]
+#set_property -dict {LOC M14  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[12]}]
+#set_property -dict {LOC N18  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[13]}]
+#set_property -dict {LOC N16  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[14]}]
+#set_property -dict {LOC N17  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[15]}]
+#set_property -dict {LOC F15  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[16]}]
+#set_property -dict {LOC E16  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[17]}]
+#set_property -dict {LOC F14  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[18]}]
+#set_property -dict {LOC E17  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[19]}]
+#set_property -dict {LOC G16  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[20]}]
+#set_property -dict {LOC F17  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[21]}]
+#set_property -dict {LOC E15  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[22]}]
+#set_property -dict {LOC G17  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[23]}]
+#set_property -dict {LOC A17  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[24]}]
+#set_property -dict {LOC C16  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[25]}]
+#set_property -dict {LOC B16  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[26]}]
+#set_property -dict {LOC A14  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[27]}]
+#set_property -dict {LOC B17  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[28]}]
+#set_property -dict {LOC B14  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[29]}]
+#set_property -dict {LOC D16  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[30]}]
+#set_property -dict {LOC D15  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[31]}]
+#set_property -dict {LOC F18  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[32]}]
+#set_property -dict {LOC F20  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[33]}]
+#set_property -dict {LOC F19  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[34]}]
+#set_property -dict {LOC D21  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[35]}]
+#set_property -dict {LOC E18  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[36]}]
+#set_property -dict {LOC G19  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[37]}]
+#set_property -dict {LOC E21  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[38]}]
+#set_property -dict {LOC G20  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[39]}]
+#set_property -dict {LOC D18  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[40]}]
+#set_property -dict {LOC B22  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[41]}]
+#set_property -dict {LOC A19  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[42]}]
+#set_property -dict {LOC A18  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[43]}]
+#set_property -dict {LOC C19  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[44]}]
+#set_property -dict {LOC B19  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[45]}]
+#set_property -dict {LOC A22  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[46]}]
+#set_property -dict {LOC C18  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[47]}]
+#set_property -dict {LOC G22  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[48]}]
+#set_property -dict {LOC J20  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[49]}]
+#set_property -dict {LOC H19  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[50]}]
+#set_property -dict {LOC J19  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[51]}]
+#set_property -dict {LOC H18  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[52]}]
+#set_property -dict {LOC J18  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[53]}]
+#set_property -dict {LOC G21  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[54]}]
+#set_property -dict {LOC K18  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[55]}]
+#set_property -dict {LOC L20  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[56]}]
+#set_property -dict {LOC L18  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[57]}]
+#set_property -dict {LOC N19  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[58]}]
+#set_property -dict {LOC M21  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[59]}]
+#set_property -dict {LOC M19  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[60]}]
+#set_property -dict {LOC M22  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[61]}]
+#set_property -dict {LOC L19  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[62]}]
+#set_property -dict {LOC M20  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[63]}]
+#set_property -dict {LOC H16  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[64]}]
+#set_property -dict {LOC K15  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[65]}]
+#set_property -dict {LOC J16  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[66]}]
+#set_property -dict {LOC J14  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[67]}]
+#set_property -dict {LOC K13  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[68]}]
+#set_property -dict {LOC L13  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[69]}]
+#set_property -dict {LOC H14  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[70]}]
+#set_property -dict {LOC J15  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dq[71]}]
+#set_property -dict {LOC M12  IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}]
+#set_property -dict {LOC L12  IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}]
+#set_property -dict {LOC L15  IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}]
+#set_property -dict {LOC L14  IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}]
+#set_property -dict {LOC F13  IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}]
+#set_property -dict {LOC E13  IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}]
+#set_property -dict {LOC B15  IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}]
+#set_property -dict {LOC A15  IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}]
+#set_property -dict {LOC F22  IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}]
+#set_property -dict {LOC E22  IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}]
+#set_property -dict {LOC C21  IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}]
+#set_property -dict {LOC B21  IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}]
+#set_property -dict {LOC K21  IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}]
+#set_property -dict {LOC K20  IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}]
+#set_property -dict {LOC L22  IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}]
+#set_property -dict {LOC K22  IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}]
+#set_property -dict {LOC K17  IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}]
+#set_property -dict {LOC K16  IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}]
+#set_property -dict {LOC N12  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dm_dbi_n[0]}]
+#set_property -dict {LOC P14  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dm_dbi_n[1]}]
+#set_property -dict {LOC G15  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dm_dbi_n[2]}]
+#set_property -dict {LOC D14  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dm_dbi_n[3]}]
+#set_property -dict {LOC E20  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dm_dbi_n[4]}]
+#set_property -dict {LOC B20  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dm_dbi_n[5]}]
+#set_property -dict {LOC H22  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dm_dbi_n[6]}]
+#set_property -dict {LOC N22  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dm_dbi_n[7]}]
+#set_property -dict {LOC J13  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c0_dm_dbi_n[8]}]
+
+# DDR4 C1
+# 5x K4A8G085WB-RC
+#set_property -dict {LOC AN9  IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c1_adr[0]}]
+#set_property -dict {LOC AM9  IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c1_adr[1]}]
+#set_property -dict {LOC AP11 IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c1_adr[2]}]
+#set_property -dict {LOC AU9  IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c1_adr[3]}]
+#set_property -dict {LOC AT10 IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c1_adr[4]}]
+#set_property -dict {LOC AL12 IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c1_adr[5]}]
+#set_property -dict {LOC AM12 IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c1_adr[6]}]
+#set_property -dict {LOC AM10 IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c1_adr[7]}]
+#set_property -dict {LOC AL11 IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c1_adr[8]}]
+#set_property -dict {LOC AP7  IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c1_adr[9]}]
+#set_property -dict {LOC AR8  IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c1_adr[10]}]
+#set_property -dict {LOC AL10 IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c1_adr[11]}]
+#set_property -dict {LOC AP8  IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c1_adr[12]}]
+#set_property -dict {LOC AK11 IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c1_adr[13]}]
+#set_property -dict {LOC AP9  IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c1_adr[14]}]
+#set_property -dict {LOC AV10 IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c1_adr[15]}]
+#set_property -dict {LOC AT11 IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c1_adr[16]}]
+#set_property -dict {LOC AL8  IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c1_adr[17]}]
+#set_property -dict {LOC AN11 IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c1_ba[0]}]
+#set_property -dict {LOC AR9  IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c1_ba[1]}]
+#set_property -dict {LOC AP12 IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c1_bg[0]}]
+#set_property -dict {LOC AN10 IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c1_bg[1]}]
+#set_property -dict {LOC AW13 IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c1_c[0]}]
+#set_property -dict {LOC AU10 IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c1_c[1]}]
+#set_property -dict {LOC AW11 IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c1_c[2]}]
+#set_property -dict {LOC AM7  IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t}]
+#set_property -dict {LOC AN7  IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c}]
+#set_property -dict {LOC AU12 IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c1_cke}]
+#set_property -dict {LOC AT12 IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c1_cs_n}]
+#set_property -dict {LOC AV9  IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c1_act_n}]
+#set_property -dict {LOC AR11 IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c1_odt}]
+#set_property -dict {LOC AM8  IOSTANDARD SSTL12_DCI     } [get_ports {ddr4_c1_par}]
+#set_property -dict {LOC AN12 IOSTANDARD LVCMOS12       } [get_ports {ddr4_c1_reset_n}]
+#set_property -dict {LOC AR10 IOSTANDARD LVCMOS12       } [get_ports {ddr4_c1_alert_n}]
+#set_property -dict {LOC AV11 IOSTANDARD LVCMOS12       } [get_ports {ddr4_c1_ten}]
+
+#set_property -dict {LOC AK9  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[0]}]
+#set_property -dict {LOC AK10 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[1]}]
+#set_property -dict {LOC AH10 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[2]}]
+#set_property -dict {LOC AJ11 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[3]}]
+#set_property -dict {LOC AJ9  IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[4]}]
+#set_property -dict {LOC AH12 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[5]}]
+#set_property -dict {LOC AG10 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[6]}]
+#set_property -dict {LOC AJ12 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[7]}]
+#set_property -dict {LOC AM15 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[8]}]
+#set_property -dict {LOC AN14 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[9]}]
+#set_property -dict {LOC AL13 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[10]}]
+#set_property -dict {LOC AM14 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[11]}]
+#set_property -dict {LOC AL15 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[12]}]
+#set_property -dict {LOC AM17 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[13]}]
+#set_property -dict {LOC AL17 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[14]}]
+#set_property -dict {LOC AM13 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[15]}]
+#set_property -dict {LOC AR15 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[16]}]
+#set_property -dict {LOC AP14 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[17]}]
+#set_property -dict {LOC AT15 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[18]}]
+#set_property -dict {LOC AR14 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[19]}]
+#set_property -dict {LOC AP17 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[20]}]
+#set_property -dict {LOC AN16 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[21]}]
+#set_property -dict {LOC AN17 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[22]}]
+#set_property -dict {LOC AN15 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[23]}]
+#set_property -dict {LOC AU15 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[24]}]
+#set_property -dict {LOC AT17 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[25]}]
+#set_property -dict {LOC AV15 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[26]}]
+#set_property -dict {LOC AT16 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[27]}]
+#set_property -dict {LOC AV14 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[28]}]
+#set_property -dict {LOC AW17 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[29]}]
+#set_property -dict {LOC AW14 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[30]}]
+#set_property -dict {LOC AW18 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[31]}]
+#set_property -dict {LOC AP19 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[32]}]
+#set_property -dict {LOC AT20 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[33]}]
+#set_property -dict {LOC AN21 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[34]}]
+#set_property -dict {LOC AR19 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[35]}]
+#set_property -dict {LOC AN20 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[36]}]
+#set_property -dict {LOC AR18 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[37]}]
+#set_property -dict {LOC AR20 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[38]}]
+#set_property -dict {LOC AP18 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[39]}]
+#set_property -dict {LOC AW19 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[40]}]
+#set_property -dict {LOC AU22 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[41]}]
+#set_property -dict {LOC AV19 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[42]}]
+#set_property -dict {LOC AW22 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[43]}]
+#set_property -dict {LOC AU18 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[44]}]
+#set_property -dict {LOC AT22 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[45]}]
+#set_property -dict {LOC AW21 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[46]}]
+#set_property -dict {LOC AU19 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[47]}]
+#set_property -dict {LOC AH19 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[48]}]
+#set_property -dict {LOC AJ22 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[49]}]
+#set_property -dict {LOC AF21 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[50]}]
+#set_property -dict {LOC AH22 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[51]}]
+#set_property -dict {LOC AF20 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[52]}]
+#set_property -dict {LOC AJ19 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[53]}]
+#set_property -dict {LOC AH21 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[54]}]
+#set_property -dict {LOC AJ21 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[55]}]
+#set_property -dict {LOC AM19 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[56]}]
+#set_property -dict {LOC AK20 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[57]}]
+#set_property -dict {LOC AM22 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[58]}]
+#set_property -dict {LOC AL22 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[59]}]
+#set_property -dict {LOC AM20 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[60]}]
+#set_property -dict {LOC AK19 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[61]}]
+#set_property -dict {LOC AN19 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[62]}]
+#set_property -dict {LOC AL20 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[63]}]
+#set_property -dict {LOC AF15 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[64]}]
+#set_property -dict {LOC AJ17 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[65]}]
+#set_property -dict {LOC AH17 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[66]}]
+#set_property -dict {LOC AJ14 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[67]}]
+#set_property -dict {LOC AG15 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[68]}]
+#set_property -dict {LOC AJ13 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[69]}]
+#set_property -dict {LOC AG17 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[70]}]
+#set_property -dict {LOC AJ16 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dq[71]}]
+#set_property -dict {LOC AG9  IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}]
+#set_property -dict {LOC AH9  IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}]
+#set_property -dict {LOC AK16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}]
+#set_property -dict {LOC AL16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}]
+#set_property -dict {LOC AR13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}]
+#set_property -dict {LOC AT13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}]
+#set_property -dict {LOC AU17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}]
+#set_property -dict {LOC AV17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}]
+#set_property -dict {LOC AN22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}]
+#set_property -dict {LOC AP22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}]
+#set_property -dict {LOC AV22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}]
+#set_property -dict {LOC AV21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}]
+#set_property -dict {LOC AG20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}]
+#set_property -dict {LOC AH20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}]
+#set_property -dict {LOC AK21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}]
+#set_property -dict {LOC AL21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}]
+#set_property -dict {LOC AH16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}]
+#set_property -dict {LOC AH15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}]
+#set_property -dict {LOC AG12 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dm_dbi_n[0]}]
+#set_property -dict {LOC AK15 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dm_dbi_n[1]}]
+#set_property -dict {LOC AP16 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dm_dbi_n[2]}]
+#set_property -dict {LOC AV16 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dm_dbi_n[3]}]
+#set_property -dict {LOC AP21 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dm_dbi_n[4]}]
+#set_property -dict {LOC AU20 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dm_dbi_n[5]}]
+#set_property -dict {LOC AG19 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dm_dbi_n[6]}]
+#set_property -dict {LOC AL18 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dm_dbi_n[7]}]
+#set_property -dict {LOC AG14 IOSTANDARD POD12_DCI      } [get_ports {ddr4_c1_dm_dbi_n[8]}]
+
+# QSPI flash
+#set_property -dict {LOC AF30 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[0]}]
+#set_property -dict {LOC AG30 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[1]}]
+#set_property -dict {LOC AF28 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[2]}]
+#set_property -dict {LOC AG28 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[3]}]
+#set_property -dict {LOC AV30 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_cs}]
+
+#set_false_path -to [get_ports {qspi_1_dq[*] qspi_1_cs}]
+#set_output_delay 0 [get_ports {qspi_1_dq[*] qspi_1_cs}]
+#set_false_path -from [get_ports {qspi_1_dq}]
+#set_input_delay 0 [get_ports {qspi_1_dq}]
--- a/example/ADM_PCIE_9V3/fpga/fpga/Makefile
+++ b/example/ADM_PCIE_9V3/fpga/fpga/Makefile
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# FPGA settings
+FPGA_PART = xcvu3p-ffvc1517-2-i
+FPGA_TOP = fpga
+FPGA_ARCH = virtexuplus
+
+# Files for synthesis
+SYN_FILES = ../rtl/fpga.sv
+SYN_FILES += ../rtl/fpga_core.sv
+SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f
+SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f
+SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv
+SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv
+SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv
+
+# XDC files
+XDC_FILES = ../fpga.xdc
+XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl
+XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl
+XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
+
+# IP
+IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_25g_161.tcl
+
+# Configuration
+# CONFIG_TCL_FILES = ./config.tcl
+
+include ../common/vivado.mk
+
+program: $(FPGA_TOP).bit
+	echo "open_hw" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
+
+%_primary.mcs %_secondary.mcs %_primary.prm %_secondary.prm: %.bit
+	echo "write_cfgmem -force -format mcs -size 64 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
+	echo "exit" >> generate_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \
+	do cp $*$$x rev/$*_rev$$COUNT$$x; \
+	echo "Output: rev/$*_rev$$COUNT$$x"; done;
+
+flash: $(FPGA_TOP)_primary.mcs $(FPGA_TOP)_secondary.mcs $(FPGA_TOP)_primary.prm $(FPGA_TOP)_secondary.prm
+	echo "open_hw" > flash.tcl
+	echo "connect_hw_server" >> flash.tcl
+	echo "open_hw_target" >> flash.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
+	echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu256-spi-x1_x2_x4_x8}] 0]" >> flash.tcl
+	echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
+	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)_primary.mcs\" \"$(FPGA_TOP)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)_primary.prm\" \"$(FPGA_TOP)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
+	echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
+	echo "program_hw_devices [current_hw_device]" >> flash.tcl
+	echo "refresh_hw_device [current_hw_device]" >> flash.tcl
+	echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
+	echo "boot_hw_device [current_hw_device]" >> flash.tcl
+	echo "exit" >> flash.tcl
+	vivado -nojournal -nolog -mode batch -source flash.tcl
+
--- a/example/ADM_PCIE_9V3/fpga/fpga_10g/Makefile
+++ b/example/ADM_PCIE_9V3/fpga/fpga_10g/Makefile
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# FPGA settings
+FPGA_PART = xcvu3p-ffvc1517-2-i
+FPGA_TOP = fpga
+FPGA_ARCH = virtexuplus
+
+# Files for synthesis
+SYN_FILES = ../rtl/fpga.sv
+SYN_FILES += ../rtl/fpga_core.sv
+SYN_FILES += ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f
+SYN_FILES += ../lib/taxi/rtl/axis/taxi_axis_async_fifo.f
+SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv
+SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv
+SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv
+
+# XDC files
+XDC_FILES = ../fpga.xdc
+XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl
+XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl
+XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
+
+# IP
+IP_TCL_FILES = ../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us_gty_10g_161.tcl
+
+# Configuration
+# CONFIG_TCL_FILES = ./config.tcl
+
+include ../common/vivado.mk
+
+program: $(FPGA_TOP).bit
+	echo "open_hw" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
+
+%_primary.mcs %_secondary.mcs %_primary.prm %_secondary.prm: %.bit
+	echo "write_cfgmem -force -format mcs -size 64 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
+	echo "exit" >> generate_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \
+	do cp $*$$x rev/$*_rev$$COUNT$$x; \
+	echo "Output: rev/$*_rev$$COUNT$$x"; done;
+
+flash: $(FPGA_TOP)_primary.mcs $(FPGA_TOP)_secondary.mcs $(FPGA_TOP)_primary.prm $(FPGA_TOP)_secondary.prm
+	echo "open_hw" > flash.tcl
+	echo "connect_hw_server" >> flash.tcl
+	echo "open_hw_target" >> flash.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
+	echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu256-spi-x1_x2_x4_x8}] 0]" >> flash.tcl
+	echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
+	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)_primary.mcs\" \"$(FPGA_TOP)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)_primary.prm\" \"$(FPGA_TOP)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
+	echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
+	echo "program_hw_devices [current_hw_device]" >> flash.tcl
+	echo "refresh_hw_device [current_hw_device]" >> flash.tcl
+	echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
+	echo "boot_hw_device [current_hw_device]" >> flash.tcl
+	echo "exit" >> flash.tcl
+	vivado -nojournal -nolog -mode batch -source flash.tcl
+
--- a/example/ADM_PCIE_9V3/fpga/lib/taxi
+++ b/example/ADM_PCIE_9V3/fpga/lib/taxi
@@ -0,0 +1 @@
+../../../../
--- a/example/ADM_PCIE_9V3/fpga/rtl/fpga.sv
+++ b/example/ADM_PCIE_9V3/fpga/rtl/fpga.sv
@@ -0,0 +1,243 @@
+// SPDX-License-Identifier: MIT
+/*
+
+Copyright (c) 2014-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * FPGA top-level module
+ */
+module fpga #
+(
+    parameter logic SIM = 1'b0,
+    parameter string VENDOR = "XILINX",
+    parameter string FAMILY = "virtexuplus"
+)
+(
+    /*
+     * Clock: 300MHz LVDS
+     */
+    input  wire logic        clk_300mhz_p,
+    input  wire logic        clk_300mhz_n,
+
+    /*
+     * GPIO
+     */
+    output wire logic [1:0]  user_led_g,
+    output wire logic        user_led_r,
+    output wire logic [1:0]  front_led,
+    input  wire logic [1:0]  user_sw,
+
+    /*
+     * Ethernet: QSFP28
+     */
+    output wire logic [3:0]  qsfp_0_tx_p,
+    output wire logic [3:0]  qsfp_0_tx_n,
+    input  wire logic [3:0]  qsfp_0_rx_p,
+    input  wire logic [3:0]  qsfp_0_rx_n,
+    input  wire logic        qsfp_0_mgt_refclk_p,
+    input  wire logic        qsfp_0_mgt_refclk_n,
+    input  wire logic        qsfp_0_modprs_l,
+    output wire logic        qsfp_0_sel_l,
+
+    output wire logic [3:0]  qsfp_1_tx_p,
+    output wire logic [3:0]  qsfp_1_tx_n,
+    input  wire logic [3:0]  qsfp_1_rx_p,
+    input  wire logic [3:0]  qsfp_1_rx_n,
+    // input  wire logic        qsfp_1_mgt_refclk_p,
+    // input  wire logic        qsfp_1_mgt_refclk_n,
+    input  wire logic        qsfp_1_modprs_l,
+    output wire logic        qsfp_1_sel_l,
+
+    output wire logic        qsfp_reset_l,
+    input  wire logic        qsfp_int_l
+);
+
+// Clock and reset
+
+wire clk_300mhz_ibufg;
+
+// Internal 125 MHz clock
+wire clk_125mhz_mmcm_out;
+wire clk_125mhz_int;
+wire rst_125mhz_int;
+
+wire mmcm_rst = 1'b0;
+wire mmcm_locked;
+wire mmcm_clkfb;
+
+IBUFGDS #(
+   .DIFF_TERM("FALSE"),
+   .IBUF_LOW_PWR("FALSE")   
+)
+clk_300mhz_ibufg_inst (
+   .O   (clk_300mhz_ibufg),
+   .I   (clk_300mhz_p),
+   .IB  (clk_300mhz_n) 
+);
+
+// MMCM instance
+MMCME4_BASE #(
+    // 300 MHz input
+    .CLKIN1_PERIOD(3.333),
+    .REF_JITTER1(0.010),
+    // 300 MHz input / 3 = 100 MHz PFD (range 10 MHz to 500 MHz)
+    .DIVCLK_DIVIDE(3),
+    // 100 MHz PFD * 12.5 = 1250 MHz VCO (range 800 MHz to 1600 MHz)
+    .CLKFBOUT_MULT_F(12.5),
+    .CLKFBOUT_PHASE(0),
+    // 1250 MHz / 10 = 125 MHz, 0 degrees
+    .CLKOUT0_DIVIDE_F(10),
+    .CLKOUT0_DUTY_CYCLE(0.5),
+    .CLKOUT0_PHASE(0),
+    // Not used
+    .CLKOUT1_DIVIDE(10),
+    .CLKOUT1_DUTY_CYCLE(0.5),
+    .CLKOUT1_PHASE(90),
+    // Not used
+    .CLKOUT2_DIVIDE(20),
+    .CLKOUT2_DUTY_CYCLE(0.5),
+    .CLKOUT2_PHASE(0),
+    // Not used
+    .CLKOUT3_DIVIDE(4),
+    .CLKOUT3_DUTY_CYCLE(0.5),
+    .CLKOUT3_PHASE(0),
+    // Not used
+    .CLKOUT4_DIVIDE(1),
+    .CLKOUT4_DUTY_CYCLE(0.5),
+    .CLKOUT4_PHASE(0),
+    .CLKOUT4_CASCADE("FALSE"),
+    // Not used
+    .CLKOUT5_DIVIDE(1),
+    .CLKOUT5_DUTY_CYCLE(0.5),
+    .CLKOUT5_PHASE(0),
+    // Not used
+    .CLKOUT6_DIVIDE(1),
+    .CLKOUT6_DUTY_CYCLE(0.5),
+    .CLKOUT6_PHASE(0),
+
+    // optimized bandwidth
+    .BANDWIDTH("OPTIMIZED"),
+    // don't wait for lock during startup
+    .STARTUP_WAIT("FALSE")
+)
+clk_mmcm_inst (
+    // 300 MHz input
+    .CLKIN1(clk_300mhz_ibufg),
+    // direct clkfb feeback
+    .CLKFBIN(mmcm_clkfb),
+    .CLKFBOUT(mmcm_clkfb),
+    .CLKFBOUTB(),
+    // 125 MHz, 0 degrees
+    .CLKOUT0(clk_125mhz_mmcm_out),
+    .CLKOUT0B(),
+    // Not used
+    .CLKOUT1(),
+    .CLKOUT1B(),
+    // Not used
+    .CLKOUT2(),
+    .CLKOUT2B(),
+    // Not used
+    .CLKOUT3(),
+    .CLKOUT3B(),
+    // Not used
+    .CLKOUT4(),
+    // Not used
+    .CLKOUT5(),
+    // Not used
+    .CLKOUT6(),
+    // reset input
+    .RST(mmcm_rst),
+    // don't power down
+    .PWRDWN(1'b0),
+    // locked output
+    .LOCKED(mmcm_locked)
+);
+
+BUFG
+clk_125mhz_bufg_inst (
+    .I(clk_125mhz_mmcm_out),
+    .O(clk_125mhz_int)
+);
+
+taxi_sync_reset #(
+    .N(4)
+)
+sync_reset_125mhz_inst (
+    .clk(clk_125mhz_int),
+    .rst(~mmcm_locked),
+    .out(rst_125mhz_int)
+);
+
+// GPIO
+wire [1:0] user_sw_int;
+
+taxi_debounce_switch #(
+    .WIDTH(2),
+    .N(4),
+    .RATE(125000)
+)
+debounce_switch_inst (
+    .clk(clk_125mhz_int),
+    .rst(rst_125mhz_int),
+    .in({user_sw}),
+    .out({user_sw_int})
+);
+
+fpga_core #(
+    .SIM(SIM),
+    .VENDOR(VENDOR),
+    .FAMILY(FAMILY)
+)
+core_inst (
+    /*
+     * Clock: 125 MHz
+     * Synchronous reset
+     */
+    .clk_125mhz(clk_125mhz_int),
+    .rst_125mhz(rst_125mhz_int),
+
+    /*
+     * GPIO
+     */
+    .user_led_g(user_led_g),
+    .user_led_r(user_led_r),
+    .front_led(front_led),
+    .user_sw(user_sw_int),
+
+    /*
+     * Ethernet: QSFP28
+     */
+    .qsfp_0_tx_p(qsfp_0_tx_p),
+    .qsfp_0_tx_n(qsfp_0_tx_n),
+    .qsfp_0_rx_p(qsfp_0_rx_p),
+    .qsfp_0_rx_n(qsfp_0_rx_n),
+    .qsfp_0_mgt_refclk_p(qsfp_0_mgt_refclk_p),
+    .qsfp_0_mgt_refclk_n(qsfp_0_mgt_refclk_n),
+    .qsfp_0_modprs_l(qsfp_0_modprs_l),
+    .qsfp_0_sel_l(qsfp_0_sel_l),
+
+    .qsfp_1_tx_p(qsfp_1_tx_p),
+    .qsfp_1_tx_n(qsfp_1_tx_n),
+    .qsfp_1_rx_p(qsfp_1_rx_p),
+    .qsfp_1_rx_n(qsfp_1_rx_n),
+    // .qsfp_1_mgt_refclk_p(qsfp_1_mgt_refclk_p),
+    // .qsfp_1_mgt_refclk_n(qsfp_1_mgt_refclk_n),
+    .qsfp_1_modprs_l(qsfp_1_modprs_l),
+    .qsfp_1_sel_l(qsfp_1_sel_l),
+
+    .qsfp_reset_l(qsfp_reset_l),
+    .qsfp_int_l(qsfp_int_l)
+);
+
+endmodule
+
+`resetall
--- a/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv
+++ b/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv
@@ -0,0 +1,529 @@
+// SPDX-License-Identifier: MIT
+/*
+
+Copyright (c) 2014-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * FPGA core logic
+ */
+module fpga_core #
+(
+    parameter logic SIM = 1'b0,
+    parameter string VENDOR = "XILINX",
+    parameter string FAMILY = "virtexuplus"
+)
+(
+    /*
+     * Clock: 125 MHz
+     * Synchronous reset
+     */
+    input  wire       clk_125mhz,
+    input  wire       rst_125mhz,
+
+    /*
+     * GPIO
+     */
+    output wire [1:0] user_led_g,
+    output wire       user_led_r,
+    output wire [1:0] front_led,
+    input  wire [1:0] user_sw,
+
+    /*
+     * Ethernet: QSFP28
+     */
+    output wire logic [3:0]  qsfp_0_tx_p,
+    output wire logic [3:0]  qsfp_0_tx_n,
+    input  wire logic [3:0]  qsfp_0_rx_p,
+    input  wire logic [3:0]  qsfp_0_rx_n,
+    input  wire logic        qsfp_0_mgt_refclk_p,
+    input  wire logic        qsfp_0_mgt_refclk_n,
+    input  wire logic        qsfp_0_modprs_l,
+    output wire logic        qsfp_0_sel_l,
+
+    output wire logic [3:0]  qsfp_1_tx_p,
+    output wire logic [3:0]  qsfp_1_tx_n,
+    input  wire logic [3:0]  qsfp_1_rx_p,
+    input  wire logic [3:0]  qsfp_1_rx_n,
+    // input  wire logic        qsfp_1_mgt_refclk_p,
+    // input  wire logic        qsfp_1_mgt_refclk_n,
+    input  wire logic        qsfp_1_modprs_l,
+    output wire logic        qsfp_1_sel_l,
+
+    output wire logic        qsfp_reset_l,
+    input  wire logic        qsfp_int_l
+);
+
+
+// QSFP28
+assign qsfp_0_sel_l = 1'b1;
+assign qsfp_1_sel_l = 1'b1;
+assign qsfp_reset_l = 1'b1;
+
+wire [7:0] qsfp_tx_clk;
+wire [7:0] qsfp_tx_rst;
+wire [7:0] qsfp_rx_clk;
+wire [7:0] qsfp_rx_rst;
+
+wire [7:0] qsfp_rx_status;
+
+wire [1:0] qsfp_gtpowergood;
+
+wire qsfp_0_mgt_refclk;
+wire qsfp_0_mgt_refclk_int;
+wire qsfp_0_mgt_refclk_bufg;
+
+wire qsfp_rst;
+
+taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_qsfp_tx[7:0]();
+taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_qsfp_tx_cpl[7:0]();
+taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_qsfp_rx[7:0]();
+
+if (SIM) begin
+
+    assign qsfp_gtpowergood = '1;
+
+    assign qsfp_0_mgt_refclk = qsfp_0_mgt_refclk_p;
+    assign qsfp_0_mgt_refclk_int = qsfp_0_mgt_refclk_p;
+    assign qsfp_0_mgt_refclk_bufg = qsfp_0_mgt_refclk_int;
+
+end else begin
+
+    IBUFDS_GTE4 ibufds_gte4_qsfp_0_mgt_refclk_inst (
+        .I     (qsfp_0_mgt_refclk_p),
+        .IB    (qsfp_0_mgt_refclk_n),
+        .CEB   (1'b0),
+        .O     (qsfp_0_mgt_refclk),
+        .ODIV2 (qsfp_0_mgt_refclk_int)
+    );
+
+    BUFG_GT bufg_gt_qsfp_0_mgt_refclk_inst (
+        .CE      (&qsfp_gtpowergood),
+        .CEMASK  (1'b1),
+        .CLR     (1'b0),
+        .CLRMASK (1'b1),
+        .DIV     (3'd0),
+        .I       (qsfp_0_mgt_refclk_int),
+        .O       (qsfp_0_mgt_refclk_bufg)
+    );
+
+end
+
+taxi_sync_reset #(
+    .N(4)
+)
+qsfp_sync_reset_inst (
+    .clk(qsfp_0_mgt_refclk_bufg),
+    .rst(rst_125mhz),
+    .out(qsfp_rst)
+);
+
+taxi_eth_mac_25g_us #(
+    .SIM(SIM),
+    .VENDOR(VENDOR),
+    .FAMILY(FAMILY),
+
+    .CNT(4),
+
+    // GT type
+    .GT_TYPE("GTY"),
+
+    // PHY parameters
+    .PADDING_EN(1'b1),
+    .DIC_EN(1'b1),
+    .MIN_FRAME_LEN(64),
+    .PTP_TS_EN(1'b0),
+    .PTP_TS_FMT_TOD(1'b1),
+    .PTP_TS_W(96),
+    .PRBS31_EN(1'b0),
+    .TX_SERDES_PIPELINE(1),
+    .RX_SERDES_PIPELINE(1),
+    .COUNT_125US(125000/6.4)
+)
+qsfp_0_mac_inst (
+    .xcvr_ctrl_clk(clk_125mhz),
+    .xcvr_ctrl_rst(qsfp_rst),
+
+    /*
+     * Common
+     */
+    .xcvr_gtpowergood_out(qsfp_gtpowergood[0]),
+    .xcvr_gtrefclk00_in(qsfp_0_mgt_refclk),
+    .xcvr_qpll0lock_out(),
+    .xcvr_qpll0clk_out(),
+    .xcvr_qpll0refclk_out(),
+
+    /*
+     * Serial data
+     */
+    .xcvr_txp(qsfp_0_tx_p),
+    .xcvr_txn(qsfp_0_tx_n),
+    .xcvr_rxp(qsfp_0_rx_p),
+    .xcvr_rxn(qsfp_0_rx_n),
+
+    /*
+     * MAC clocks
+     */
+    .rx_clk(qsfp_rx_clk[3:0]),
+    .rx_rst_in('0),
+    .rx_rst_out(qsfp_rx_rst[3:0]),
+    .tx_clk(qsfp_tx_clk[3:0]),
+    .tx_rst_in('0),
+    .tx_rst_out(qsfp_tx_rst[3:0]),
+    .ptp_sample_clk('0),
+
+    /*
+     * Transmit interface (AXI stream)
+     */
+    .s_axis_tx(axis_qsfp_tx[3:0]),
+    .m_axis_tx_cpl(axis_qsfp_tx_cpl[3:0]),
+
+    /*
+     * Receive interface (AXI stream)
+     */
+    .m_axis_rx(axis_qsfp_rx[3:0]),
+
+    /*
+     * PTP clock
+     */
+    .tx_ptp_ts('0),
+    .tx_ptp_ts_step('0),
+    .rx_ptp_ts('0),
+    .rx_ptp_ts_step('0),
+
+
+    /*
+     * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
+     */
+    .tx_lfc_req('0),
+    .tx_lfc_resend('0),
+    .rx_lfc_en('0),
+    .rx_lfc_req(),
+    .rx_lfc_ack('0),
+
+    /*
+     * Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
+     */
+    .tx_pfc_req('0),
+    .tx_pfc_resend('0),
+    .rx_pfc_en('0),
+    .rx_pfc_req(),
+    .rx_pfc_ack('0),
+
+    /*
+     * Pause interface
+     */
+    .tx_lfc_pause_en('0),
+    .tx_pause_req('0),
+    .tx_pause_ack(),
+
+    /*
+     * Status
+     */
+    .tx_start_packet(),
+    .tx_error_underflow(),
+    .rx_start_packet(),
+    .rx_error_count(),
+    .rx_error_bad_frame(),
+    .rx_error_bad_fcs(),
+    .rx_bad_block(),
+    .rx_sequence_error(),
+    .rx_block_lock(),
+    .rx_high_ber(),
+    .rx_status(qsfp_rx_status[3:0]),
+    .stat_tx_mcf(),
+    .stat_rx_mcf(),
+    .stat_tx_lfc_pkt(),
+    .stat_tx_lfc_xon(),
+    .stat_tx_lfc_xoff(),
+    .stat_tx_lfc_paused(),
+    .stat_tx_pfc_pkt(),
+    .stat_tx_pfc_xon(),
+    .stat_tx_pfc_xoff(),
+    .stat_tx_pfc_paused(),
+    .stat_rx_lfc_pkt(),
+    .stat_rx_lfc_xon(),
+    .stat_rx_lfc_xoff(),
+    .stat_rx_lfc_paused(),
+    .stat_rx_pfc_pkt(),
+    .stat_rx_pfc_xon(),
+    .stat_rx_pfc_xoff(),
+    .stat_rx_pfc_paused(),
+
+    /*
+     * Configuration
+     */
+    .cfg_ifg('{4{8'd12}}),
+    .cfg_tx_enable('1),
+    .cfg_rx_enable('1),
+    .cfg_tx_prbs31_enable('0),
+    .cfg_rx_prbs31_enable('0),
+    .cfg_mcf_rx_eth_dst_mcast('{4{48'h01_80_C2_00_00_01}}),
+    .cfg_mcf_rx_check_eth_dst_mcast('1),
+    .cfg_mcf_rx_eth_dst_ucast('{4{48'd0}}),
+    .cfg_mcf_rx_check_eth_dst_ucast('0),
+    .cfg_mcf_rx_eth_src('{4{48'd0}}),
+    .cfg_mcf_rx_check_eth_src('0),
+    .cfg_mcf_rx_eth_type('{4{16'h8808}}),
+    .cfg_mcf_rx_opcode_lfc('{4{16'h0001}}),
+    .cfg_mcf_rx_check_opcode_lfc('1),
+    .cfg_mcf_rx_opcode_pfc('{4{16'h0101}}),
+    .cfg_mcf_rx_check_opcode_pfc('1),
+    .cfg_mcf_rx_forward('0),
+    .cfg_mcf_rx_enable('0),
+    .cfg_tx_lfc_eth_dst('{4{48'h01_80_C2_00_00_01}}),
+    .cfg_tx_lfc_eth_src('{4{48'h80_23_31_43_54_4C}}),
+    .cfg_tx_lfc_eth_type('{4{16'h8808}}),
+    .cfg_tx_lfc_opcode('{4{16'h0001}}),
+    .cfg_tx_lfc_en('0),
+    .cfg_tx_lfc_quanta('{4{16'hffff}}),
+    .cfg_tx_lfc_refresh('{4{16'h7fff}}),
+    .cfg_tx_pfc_eth_dst('{4{48'h01_80_C2_00_00_01}}),
+    .cfg_tx_pfc_eth_src('{4{48'h80_23_31_43_54_4C}}),
+    .cfg_tx_pfc_eth_type('{4{16'h8808}}),
+    .cfg_tx_pfc_opcode('{4{16'h0101}}),
+    .cfg_tx_pfc_en('0),
+    .cfg_tx_pfc_quanta('{4{'{8{16'hffff}}}}),
+    .cfg_tx_pfc_refresh('{4{'{8{16'h7fff}}}}),
+    .cfg_rx_lfc_opcode('{4{16'h0001}}),
+    .cfg_rx_lfc_en('0),
+    .cfg_rx_pfc_opcode('{4{16'h0101}}),
+    .cfg_rx_pfc_en('0)
+);
+
+taxi_eth_mac_25g_us #(
+    .SIM(SIM),
+    .VENDOR(VENDOR),
+    .FAMILY(FAMILY),
+
+    .CNT(4),
+
+    // GT type
+    .GT_TYPE("GTY"),
+
+    // PHY parameters
+    .PADDING_EN(1'b1),
+    .DIC_EN(1'b1),
+    .MIN_FRAME_LEN(64),
+    .PTP_TS_EN(1'b0),
+    .PTP_TS_FMT_TOD(1'b1),
+    .PTP_TS_W(96),
+    .PRBS31_EN(1'b0),
+    .TX_SERDES_PIPELINE(1),
+    .RX_SERDES_PIPELINE(1),
+    .COUNT_125US(125000/6.4)
+)
+qsfp_1_mac_inst (
+    .xcvr_ctrl_clk(clk_125mhz),
+    .xcvr_ctrl_rst(qsfp_rst),
+
+    /*
+     * Common
+     */
+    .xcvr_gtpowergood_out(qsfp_gtpowergood[1]),
+    .xcvr_gtrefclk00_in(qsfp_0_mgt_refclk),
+    .xcvr_qpll0lock_out(),
+    .xcvr_qpll0clk_out(),
+    .xcvr_qpll0refclk_out(),
+
+    /*
+     * Serial data
+     */
+    .xcvr_txp(qsfp_1_tx_p),
+    .xcvr_txn(qsfp_1_tx_n),
+    .xcvr_rxp(qsfp_1_rx_p),
+    .xcvr_rxn(qsfp_1_rx_n),
+
+    /*
+     * MAC clocks
+     */
+    .rx_clk(qsfp_rx_clk[7:4]),
+    .rx_rst_in('0),
+    .rx_rst_out(qsfp_rx_rst[7:4]),
+    .tx_clk(qsfp_tx_clk[7:4]),
+    .tx_rst_in('0),
+    .tx_rst_out(qsfp_tx_rst[7:4]),
+    .ptp_sample_clk('0),
+
+    /*
+     * Transmit interface (AXI stream)
+     */
+    .s_axis_tx(axis_qsfp_tx[7:4]),
+    .m_axis_tx_cpl(axis_qsfp_tx_cpl[7:4]),
+
+    /*
+     * Receive interface (AXI stream)
+     */
+    .m_axis_rx(axis_qsfp_rx[7:4]),
+
+    /*
+     * PTP clock
+     */
+    .tx_ptp_ts('0),
+    .tx_ptp_ts_step('0),
+    .rx_ptp_ts('0),
+    .rx_ptp_ts_step('0),
+
+
+    /*
+     * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
+     */
+    .tx_lfc_req('0),
+    .tx_lfc_resend('0),
+    .rx_lfc_en('0),
+    .rx_lfc_req(),
+    .rx_lfc_ack('0),
+
+    /*
+     * Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
+     */
+    .tx_pfc_req('0),
+    .tx_pfc_resend('0),
+    .rx_pfc_en('0),
+    .rx_pfc_req(),
+    .rx_pfc_ack('0),
+
+    /*
+     * Pause interface
+     */
+    .tx_lfc_pause_en('0),
+    .tx_pause_req('0),
+    .tx_pause_ack(),
+
+    /*
+     * Status
+     */
+    .tx_start_packet(),
+    .tx_error_underflow(),
+    .rx_start_packet(),
+    .rx_error_count(),
+    .rx_error_bad_frame(),
+    .rx_error_bad_fcs(),
+    .rx_bad_block(),
+    .rx_sequence_error(),
+    .rx_block_lock(),
+    .rx_high_ber(),
+    .rx_status(qsfp_rx_status[7:4]),
+    .stat_tx_mcf(),
+    .stat_rx_mcf(),
+    .stat_tx_lfc_pkt(),
+    .stat_tx_lfc_xon(),
+    .stat_tx_lfc_xoff(),
+    .stat_tx_lfc_paused(),
+    .stat_tx_pfc_pkt(),
+    .stat_tx_pfc_xon(),
+    .stat_tx_pfc_xoff(),
+    .stat_tx_pfc_paused(),
+    .stat_rx_lfc_pkt(),
+    .stat_rx_lfc_xon(),
+    .stat_rx_lfc_xoff(),
+    .stat_rx_lfc_paused(),
+    .stat_rx_pfc_pkt(),
+    .stat_rx_pfc_xon(),
+    .stat_rx_pfc_xoff(),
+    .stat_rx_pfc_paused(),
+
+    /*
+     * Configuration
+     */
+    .cfg_ifg('{4{8'd12}}),
+    .cfg_tx_enable('1),
+    .cfg_rx_enable('1),
+    .cfg_tx_prbs31_enable('0),
+    .cfg_rx_prbs31_enable('0),
+    .cfg_mcf_rx_eth_dst_mcast('{4{48'h01_80_C2_00_00_01}}),
+    .cfg_mcf_rx_check_eth_dst_mcast('1),
+    .cfg_mcf_rx_eth_dst_ucast('{4{48'd0}}),
+    .cfg_mcf_rx_check_eth_dst_ucast('0),
+    .cfg_mcf_rx_eth_src('{4{48'd0}}),
+    .cfg_mcf_rx_check_eth_src('0),
+    .cfg_mcf_rx_eth_type('{4{16'h8808}}),
+    .cfg_mcf_rx_opcode_lfc('{4{16'h0001}}),
+    .cfg_mcf_rx_check_opcode_lfc('1),
+    .cfg_mcf_rx_opcode_pfc('{4{16'h0101}}),
+    .cfg_mcf_rx_check_opcode_pfc('1),
+    .cfg_mcf_rx_forward('0),
+    .cfg_mcf_rx_enable('0),
+    .cfg_tx_lfc_eth_dst('{4{48'h01_80_C2_00_00_01}}),
+    .cfg_tx_lfc_eth_src('{4{48'h80_23_31_43_54_4C}}),
+    .cfg_tx_lfc_eth_type('{4{16'h8808}}),
+    .cfg_tx_lfc_opcode('{4{16'h0001}}),
+    .cfg_tx_lfc_en('0),
+    .cfg_tx_lfc_quanta('{4{16'hffff}}),
+    .cfg_tx_lfc_refresh('{4{16'h7fff}}),
+    .cfg_tx_pfc_eth_dst('{4{48'h01_80_C2_00_00_01}}),
+    .cfg_tx_pfc_eth_src('{4{48'h80_23_31_43_54_4C}}),
+    .cfg_tx_pfc_eth_type('{4{16'h8808}}),
+    .cfg_tx_pfc_opcode('{4{16'h0101}}),
+    .cfg_tx_pfc_en('0),
+    .cfg_tx_pfc_quanta('{4{'{8{16'hffff}}}}),
+    .cfg_tx_pfc_refresh('{4{'{8{16'h7fff}}}}),
+    .cfg_rx_lfc_opcode('{4{16'h0001}}),
+    .cfg_rx_lfc_en('0),
+    .cfg_rx_pfc_opcode('{4{16'h0101}}),
+    .cfg_rx_pfc_en('0)
+);
+
+for (genvar n = 0; n < 8; n = n + 1) begin : qsfp_ch
+
+    taxi_axis_async_fifo #(
+        .DEPTH(16384),
+        .RAM_PIPELINE(2),
+        .FRAME_FIFO(1),
+        .USER_BAD_FRAME_VALUE(1'b1),
+        .USER_BAD_FRAME_MASK(1'b1),
+        .DROP_OVERSIZE_FRAME(1),
+        .DROP_BAD_FRAME(1),
+        .DROP_WHEN_FULL(1)
+    )
+    ch_fifo (
+        /*
+         * AXI4-Stream input (sink)
+         */
+        .s_clk(qsfp_rx_clk[n]),
+        .s_rst(qsfp_rx_rst[n]),
+        .s_axis(axis_qsfp_rx[n]),
+
+        /*
+         * AXI4-Stream output (source)
+         */
+        .m_clk(qsfp_tx_clk[n]),
+        .m_rst(qsfp_tx_rst[n]),
+        .m_axis(axis_qsfp_tx[n]),
+
+        /*
+         * Pause
+         */
+        .s_pause_req(1'b0),
+        .s_pause_ack(),
+        .m_pause_req(1'b0),
+        .m_pause_ack(),
+
+        /*
+         * Status
+         */
+        .s_status_depth(),
+        .s_status_depth_commit(),
+        .s_status_overflow(),
+        .s_status_bad_frame(),
+        .s_status_good_frame(),
+        .m_status_depth(),
+        .m_status_depth_commit(),
+        .m_status_overflow(),
+        .m_status_bad_frame(),
+        .m_status_good_frame()
+    );
+
+end
+
+endmodule
+
+`resetall
--- a/example/ADM_PCIE_9V3/fpga/tb/fpga_core/Makefile
+++ b/example/ADM_PCIE_9V3/fpga/tb/fpga_core/Makefile
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2020-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+DUT      = fpga_core
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = $(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += ../../rtl/$(DUT).sv
+VERILOG_SOURCES += ../../lib/taxi/rtl/eth/us/taxi_eth_mac_25g_us.f
+VERILOG_SOURCES += ../../lib/taxi/rtl/axis/taxi_axis_async_fifo.f
+VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_reset.sv
+VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_signal.sv
+VERILOG_SOURCES += ../../lib/taxi/rtl/io/taxi_debounce_switch.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_SIM := "1'b1"
+export PARAM_VENDOR := "\"XILINX\""
+export PARAM_FAMILY := "\"virtexuplus\""
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim
--- a/example/ADM_PCIE_9V3/fpga/tb/fpga_core/baser.py
+++ b/example/ADM_PCIE_9V3/fpga/tb/fpga_core/baser.py
@@ -0,0 +1 @@
+../../lib/taxi/tb/eth/baser.py
--- a/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py
+++ b/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py
@@ -0,0 +1,192 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: MIT
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import logging
+import os
+import sys
+
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.log import SimLog
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge, Combine
+
+from cocotbext.eth import XgmiiFrame
+
+try:
+    from baser import BaseRSerdesSource, BaseRSerdesSink
+except ImportError:
+    # attempt import from current directory
+    sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
+    try:
+        from baser import BaseRSerdesSource, BaseRSerdesSink
+    finally:
+        del sys.path[0]
+
+
+class TB:
+    def __init__(self, dut, speed=1000e6):
+        self.dut = dut
+
+        self.log = SimLog("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start())
+        cocotb.start_soon(Clock(dut.qsfp_0_mgt_refclk_p, 6.206, units="ns").start())
+
+        self.qsfp_sources = []
+        self.qsfp_sinks = []
+
+        for ch in list(dut.qsfp_0_mac_inst.ch)+list(dut.qsfp_1_mac_inst.ch):
+            cocotb.start_soon(Clock(ch.ch_inst.tx_clk, 2.56, units="ns").start())
+            cocotb.start_soon(Clock(ch.ch_inst.rx_clk, 2.56, units="ns").start())
+
+            self.qsfp_sources.append(BaseRSerdesSource(ch.ch_inst.serdes_rx_data, ch.ch_inst.serdes_rx_hdr, ch.ch_inst.rx_clk, slip=ch.ch_inst.serdes_rx_bitslip, reverse=True))
+            self.qsfp_sinks.append(BaseRSerdesSink(ch.ch_inst.serdes_tx_data, ch.ch_inst.serdes_tx_hdr, ch.ch_inst.tx_clk, reverse=True))
+
+        dut.user_sw.setimmediatevalue(0)
+
+    async def init(self):
+
+        self.dut.rst_125mhz.setimmediatevalue(0)
+
+        for k in range(10):
+            await RisingEdge(self.dut.clk_125mhz)
+
+        self.dut.rst_125mhz.value = 1
+
+        for k in range(10):
+            await RisingEdge(self.dut.clk_125mhz)
+
+        self.dut.rst_125mhz.value = 0
+
+        for k in range(10):
+            await RisingEdge(self.dut.clk_125mhz)
+
+
+async def mac_test(tb, source, sink):
+    tb.log.info("Test MAC")
+
+    tb.log.info("Multiple small packets")
+
+    count = 64
+
+    pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
+
+    for p in pkts:
+        await source.send(XgmiiFrame.from_payload(p))
+
+    for k in range(count):
+        rx_frame = await sink.recv()
+
+        tb.log.info("RX frame: %s", rx_frame)
+
+        assert rx_frame.get_payload() == pkts[k]
+        assert rx_frame.check_fcs()
+
+    tb.log.info("Multiple large packets")
+
+    count = 32
+
+    pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
+
+    for p in pkts:
+        await source.send(XgmiiFrame.from_payload(p))
+
+    for k in range(count):
+        rx_frame = await sink.recv()
+
+        tb.log.info("RX frame: %s", rx_frame)
+
+        assert rx_frame.get_payload() == pkts[k]
+        assert rx_frame.check_fcs()
+
+    tb.log.info("MAC test done")
+
+
+@cocotb.test()
+async def run_test(dut):
+
+    tb = TB(dut)
+
+    await tb.init()
+
+    tests = []
+
+    for k in range(len(tb.qsfp_sources)):
+        tb.log.info("Start QSFP %d MAC loopback test", k)
+
+        tests.append(cocotb.start_soon(mac_test(tb, tb.qsfp_sources[k], tb.qsfp_sinks[k])))
+
+    await Combine(*tests)
+
+    await RisingEdge(dut.clk_125mhz)
+    await RisingEdge(dut.clk_125mhz)
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+def test_fpga_core(request):
+    dut = "fpga_core"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = dut
+
+    verilog_sources = [
+        os.path.join(rtl_dir, f"{dut}.sv"),
+        os.path.join(lib_dir, "taxi", "rtl", "eth", "us", "taxi_eth_mac_25g_us.f"),
+        os.path.join(lib_dir, "taxi", "rtl", "axis", "taxi_axis_async_fifo.f"),
+        os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_reset.sv"),
+        os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_signal.sv"),
+        os.path.join(lib_dir, "taxi", "rtl", "io", "taxi_debounce_switch.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['SIM'] = "1'b1"
+    parameters['VENDOR'] = "\"XILINX\""
+    parameters['FAMILY'] = "\"virtexuplus\""
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )