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example/ADM_PCIE_9V3: Add example design for ADM-PCIE-9V3
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
243
example/ADM_PCIE_9V3/fpga/rtl/fpga.sv
Normal file
243
example/ADM_PCIE_9V3/fpga/rtl/fpga.sv
Normal file
@@ -0,0 +1,243 @@
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// SPDX-License-Identifier: MIT
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/*
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Copyright (c) 2014-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA top-level module
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*/
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module fpga #
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(
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parameter logic SIM = 1'b0,
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parameter string VENDOR = "XILINX",
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parameter string FAMILY = "virtexuplus"
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)
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(
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/*
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* Clock: 300MHz LVDS
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*/
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input wire logic clk_300mhz_p,
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input wire logic clk_300mhz_n,
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/*
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* GPIO
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*/
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output wire logic [1:0] user_led_g,
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output wire logic user_led_r,
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output wire logic [1:0] front_led,
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input wire logic [1:0] user_sw,
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/*
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* Ethernet: QSFP28
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*/
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output wire logic [3:0] qsfp_0_tx_p,
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output wire logic [3:0] qsfp_0_tx_n,
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input wire logic [3:0] qsfp_0_rx_p,
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input wire logic [3:0] qsfp_0_rx_n,
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input wire logic qsfp_0_mgt_refclk_p,
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input wire logic qsfp_0_mgt_refclk_n,
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input wire logic qsfp_0_modprs_l,
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output wire logic qsfp_0_sel_l,
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output wire logic [3:0] qsfp_1_tx_p,
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output wire logic [3:0] qsfp_1_tx_n,
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input wire logic [3:0] qsfp_1_rx_p,
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input wire logic [3:0] qsfp_1_rx_n,
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// input wire logic qsfp_1_mgt_refclk_p,
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// input wire logic qsfp_1_mgt_refclk_n,
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input wire logic qsfp_1_modprs_l,
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output wire logic qsfp_1_sel_l,
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output wire logic qsfp_reset_l,
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input wire logic qsfp_int_l
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);
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// Clock and reset
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wire clk_300mhz_ibufg;
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// Internal 125 MHz clock
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wire clk_125mhz_mmcm_out;
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wire clk_125mhz_int;
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wire rst_125mhz_int;
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wire mmcm_rst = 1'b0;
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wire mmcm_locked;
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wire mmcm_clkfb;
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IBUFGDS #(
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.DIFF_TERM("FALSE"),
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.IBUF_LOW_PWR("FALSE")
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)
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clk_300mhz_ibufg_inst (
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.O (clk_300mhz_ibufg),
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.I (clk_300mhz_p),
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.IB (clk_300mhz_n)
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);
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// MMCM instance
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MMCME4_BASE #(
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// 300 MHz input
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.CLKIN1_PERIOD(3.333),
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.REF_JITTER1(0.010),
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// 300 MHz input / 3 = 100 MHz PFD (range 10 MHz to 500 MHz)
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.DIVCLK_DIVIDE(3),
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// 100 MHz PFD * 12.5 = 1250 MHz VCO (range 800 MHz to 1600 MHz)
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.CLKFBOUT_MULT_F(12.5),
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.CLKFBOUT_PHASE(0),
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// 1250 MHz / 10 = 125 MHz, 0 degrees
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.CLKOUT0_DIVIDE_F(10),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0),
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// Not used
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.CLKOUT1_DIVIDE(10),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_PHASE(90),
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// Not used
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.CLKOUT2_DIVIDE(20),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT2_PHASE(0),
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// Not used
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.CLKOUT3_DIVIDE(4),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_PHASE(0),
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// Not used
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.CLKOUT4_DIVIDE(1),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_PHASE(0),
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.CLKOUT4_CASCADE("FALSE"),
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// Not used
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.CLKOUT5_DIVIDE(1),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT5_PHASE(0),
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// Not used
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.CLKOUT6_DIVIDE(1),
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.CLKOUT6_DUTY_CYCLE(0.5),
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.CLKOUT6_PHASE(0),
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// optimized bandwidth
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.BANDWIDTH("OPTIMIZED"),
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// don't wait for lock during startup
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.STARTUP_WAIT("FALSE")
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)
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clk_mmcm_inst (
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// 300 MHz input
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.CLKIN1(clk_300mhz_ibufg),
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// direct clkfb feeback
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.CLKFBIN(mmcm_clkfb),
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.CLKFBOUT(mmcm_clkfb),
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.CLKFBOUTB(),
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// 125 MHz, 0 degrees
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.CLKOUT0(clk_125mhz_mmcm_out),
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.CLKOUT0B(),
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// Not used
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.CLKOUT1(),
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.CLKOUT1B(),
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// Not used
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.CLKOUT2(),
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.CLKOUT2B(),
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// Not used
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.CLKOUT3(),
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.CLKOUT3B(),
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// Not used
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.CLKOUT4(),
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// Not used
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.CLKOUT5(),
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// Not used
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.CLKOUT6(),
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// reset input
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.RST(mmcm_rst),
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// don't power down
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.PWRDWN(1'b0),
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// locked output
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.LOCKED(mmcm_locked)
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);
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BUFG
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clk_125mhz_bufg_inst (
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.I(clk_125mhz_mmcm_out),
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.O(clk_125mhz_int)
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);
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taxi_sync_reset #(
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.N(4)
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)
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sync_reset_125mhz_inst (
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.clk(clk_125mhz_int),
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.rst(~mmcm_locked),
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.out(rst_125mhz_int)
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);
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// GPIO
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wire [1:0] user_sw_int;
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taxi_debounce_switch #(
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.WIDTH(2),
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.N(4),
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.RATE(125000)
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)
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debounce_switch_inst (
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.clk(clk_125mhz_int),
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.rst(rst_125mhz_int),
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.in({user_sw}),
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.out({user_sw_int})
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);
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fpga_core #(
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.SIM(SIM),
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.VENDOR(VENDOR),
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.FAMILY(FAMILY)
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)
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core_inst (
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/*
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* Clock: 125 MHz
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* Synchronous reset
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*/
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.clk_125mhz(clk_125mhz_int),
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.rst_125mhz(rst_125mhz_int),
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/*
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* GPIO
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*/
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.user_led_g(user_led_g),
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.user_led_r(user_led_r),
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.front_led(front_led),
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.user_sw(user_sw_int),
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/*
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* Ethernet: QSFP28
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*/
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.qsfp_0_tx_p(qsfp_0_tx_p),
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.qsfp_0_tx_n(qsfp_0_tx_n),
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.qsfp_0_rx_p(qsfp_0_rx_p),
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.qsfp_0_rx_n(qsfp_0_rx_n),
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.qsfp_0_mgt_refclk_p(qsfp_0_mgt_refclk_p),
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.qsfp_0_mgt_refclk_n(qsfp_0_mgt_refclk_n),
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.qsfp_0_modprs_l(qsfp_0_modprs_l),
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.qsfp_0_sel_l(qsfp_0_sel_l),
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.qsfp_1_tx_p(qsfp_1_tx_p),
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.qsfp_1_tx_n(qsfp_1_tx_n),
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.qsfp_1_rx_p(qsfp_1_rx_p),
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.qsfp_1_rx_n(qsfp_1_rx_n),
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// .qsfp_1_mgt_refclk_p(qsfp_1_mgt_refclk_p),
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// .qsfp_1_mgt_refclk_n(qsfp_1_mgt_refclk_n),
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.qsfp_1_modprs_l(qsfp_1_modprs_l),
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.qsfp_1_sel_l(qsfp_1_sel_l),
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.qsfp_reset_l(qsfp_reset_l),
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.qsfp_int_l(qsfp_int_l)
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);
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endmodule
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`resetall
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529
example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv
Normal file
529
example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv
Normal file
@@ -0,0 +1,529 @@
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// SPDX-License-Identifier: MIT
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/*
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Copyright (c) 2014-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA core logic
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*/
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module fpga_core #
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(
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parameter logic SIM = 1'b0,
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parameter string VENDOR = "XILINX",
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parameter string FAMILY = "virtexuplus"
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)
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(
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/*
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* Clock: 125 MHz
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* Synchronous reset
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*/
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input wire clk_125mhz,
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input wire rst_125mhz,
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/*
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* GPIO
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*/
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output wire [1:0] user_led_g,
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output wire user_led_r,
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output wire [1:0] front_led,
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input wire [1:0] user_sw,
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/*
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* Ethernet: QSFP28
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*/
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output wire logic [3:0] qsfp_0_tx_p,
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output wire logic [3:0] qsfp_0_tx_n,
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input wire logic [3:0] qsfp_0_rx_p,
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input wire logic [3:0] qsfp_0_rx_n,
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input wire logic qsfp_0_mgt_refclk_p,
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input wire logic qsfp_0_mgt_refclk_n,
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input wire logic qsfp_0_modprs_l,
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output wire logic qsfp_0_sel_l,
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output wire logic [3:0] qsfp_1_tx_p,
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output wire logic [3:0] qsfp_1_tx_n,
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input wire logic [3:0] qsfp_1_rx_p,
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input wire logic [3:0] qsfp_1_rx_n,
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// input wire logic qsfp_1_mgt_refclk_p,
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// input wire logic qsfp_1_mgt_refclk_n,
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input wire logic qsfp_1_modprs_l,
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output wire logic qsfp_1_sel_l,
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output wire logic qsfp_reset_l,
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input wire logic qsfp_int_l
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);
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// QSFP28
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assign qsfp_0_sel_l = 1'b1;
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assign qsfp_1_sel_l = 1'b1;
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assign qsfp_reset_l = 1'b1;
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wire [7:0] qsfp_tx_clk;
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wire [7:0] qsfp_tx_rst;
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wire [7:0] qsfp_rx_clk;
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wire [7:0] qsfp_rx_rst;
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wire [7:0] qsfp_rx_status;
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wire [1:0] qsfp_gtpowergood;
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wire qsfp_0_mgt_refclk;
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wire qsfp_0_mgt_refclk_int;
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wire qsfp_0_mgt_refclk_bufg;
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wire qsfp_rst;
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taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_qsfp_tx[7:0]();
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taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_qsfp_tx_cpl[7:0]();
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taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_qsfp_rx[7:0]();
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if (SIM) begin
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assign qsfp_gtpowergood = '1;
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assign qsfp_0_mgt_refclk = qsfp_0_mgt_refclk_p;
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assign qsfp_0_mgt_refclk_int = qsfp_0_mgt_refclk_p;
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assign qsfp_0_mgt_refclk_bufg = qsfp_0_mgt_refclk_int;
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end else begin
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IBUFDS_GTE4 ibufds_gte4_qsfp_0_mgt_refclk_inst (
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.I (qsfp_0_mgt_refclk_p),
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.IB (qsfp_0_mgt_refclk_n),
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.CEB (1'b0),
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.O (qsfp_0_mgt_refclk),
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.ODIV2 (qsfp_0_mgt_refclk_int)
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);
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BUFG_GT bufg_gt_qsfp_0_mgt_refclk_inst (
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.CE (&qsfp_gtpowergood),
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.CEMASK (1'b1),
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.CLR (1'b0),
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.CLRMASK (1'b1),
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.DIV (3'd0),
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.I (qsfp_0_mgt_refclk_int),
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.O (qsfp_0_mgt_refclk_bufg)
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);
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end
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taxi_sync_reset #(
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.N(4)
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)
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qsfp_sync_reset_inst (
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.clk(qsfp_0_mgt_refclk_bufg),
|
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.rst(rst_125mhz),
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.out(qsfp_rst)
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);
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taxi_eth_mac_25g_us #(
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.SIM(SIM),
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.VENDOR(VENDOR),
|
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.FAMILY(FAMILY),
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.CNT(4),
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// GT type
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.GT_TYPE("GTY"),
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// PHY parameters
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.PADDING_EN(1'b1),
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.DIC_EN(1'b1),
|
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.MIN_FRAME_LEN(64),
|
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.PTP_TS_EN(1'b0),
|
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.PTP_TS_FMT_TOD(1'b1),
|
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.PTP_TS_W(96),
|
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.PRBS31_EN(1'b0),
|
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.TX_SERDES_PIPELINE(1),
|
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.RX_SERDES_PIPELINE(1),
|
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.COUNT_125US(125000/6.4)
|
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)
|
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qsfp_0_mac_inst (
|
||||
.xcvr_ctrl_clk(clk_125mhz),
|
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.xcvr_ctrl_rst(qsfp_rst),
|
||||
|
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/*
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* Common
|
||||
*/
|
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.xcvr_gtpowergood_out(qsfp_gtpowergood[0]),
|
||||
.xcvr_gtrefclk00_in(qsfp_0_mgt_refclk),
|
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.xcvr_qpll0lock_out(),
|
||||
.xcvr_qpll0clk_out(),
|
||||
.xcvr_qpll0refclk_out(),
|
||||
|
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/*
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* Serial data
|
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*/
|
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.xcvr_txp(qsfp_0_tx_p),
|
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.xcvr_txn(qsfp_0_tx_n),
|
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.xcvr_rxp(qsfp_0_rx_p),
|
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.xcvr_rxn(qsfp_0_rx_n),
|
||||
|
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/*
|
||||
* MAC clocks
|
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*/
|
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.rx_clk(qsfp_rx_clk[3:0]),
|
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.rx_rst_in('0),
|
||||
.rx_rst_out(qsfp_rx_rst[3:0]),
|
||||
.tx_clk(qsfp_tx_clk[3:0]),
|
||||
.tx_rst_in('0),
|
||||
.tx_rst_out(qsfp_tx_rst[3:0]),
|
||||
.ptp_sample_clk('0),
|
||||
|
||||
/*
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* Transmit interface (AXI stream)
|
||||
*/
|
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.s_axis_tx(axis_qsfp_tx[3:0]),
|
||||
.m_axis_tx_cpl(axis_qsfp_tx_cpl[3:0]),
|
||||
|
||||
/*
|
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* Receive interface (AXI stream)
|
||||
*/
|
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.m_axis_rx(axis_qsfp_rx[3:0]),
|
||||
|
||||
/*
|
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* PTP clock
|
||||
*/
|
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.tx_ptp_ts('0),
|
||||
.tx_ptp_ts_step('0),
|
||||
.rx_ptp_ts('0),
|
||||
.rx_ptp_ts_step('0),
|
||||
|
||||
|
||||
/*
|
||||
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
|
||||
*/
|
||||
.tx_lfc_req('0),
|
||||
.tx_lfc_resend('0),
|
||||
.rx_lfc_en('0),
|
||||
.rx_lfc_req(),
|
||||
.rx_lfc_ack('0),
|
||||
|
||||
/*
|
||||
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
|
||||
*/
|
||||
.tx_pfc_req('0),
|
||||
.tx_pfc_resend('0),
|
||||
.rx_pfc_en('0),
|
||||
.rx_pfc_req(),
|
||||
.rx_pfc_ack('0),
|
||||
|
||||
/*
|
||||
* Pause interface
|
||||
*/
|
||||
.tx_lfc_pause_en('0),
|
||||
.tx_pause_req('0),
|
||||
.tx_pause_ack(),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_start_packet(),
|
||||
.tx_error_underflow(),
|
||||
.rx_start_packet(),
|
||||
.rx_error_count(),
|
||||
.rx_error_bad_frame(),
|
||||
.rx_error_bad_fcs(),
|
||||
.rx_bad_block(),
|
||||
.rx_sequence_error(),
|
||||
.rx_block_lock(),
|
||||
.rx_high_ber(),
|
||||
.rx_status(qsfp_rx_status[3:0]),
|
||||
.stat_tx_mcf(),
|
||||
.stat_rx_mcf(),
|
||||
.stat_tx_lfc_pkt(),
|
||||
.stat_tx_lfc_xon(),
|
||||
.stat_tx_lfc_xoff(),
|
||||
.stat_tx_lfc_paused(),
|
||||
.stat_tx_pfc_pkt(),
|
||||
.stat_tx_pfc_xon(),
|
||||
.stat_tx_pfc_xoff(),
|
||||
.stat_tx_pfc_paused(),
|
||||
.stat_rx_lfc_pkt(),
|
||||
.stat_rx_lfc_xon(),
|
||||
.stat_rx_lfc_xoff(),
|
||||
.stat_rx_lfc_paused(),
|
||||
.stat_rx_pfc_pkt(),
|
||||
.stat_rx_pfc_xon(),
|
||||
.stat_rx_pfc_xoff(),
|
||||
.stat_rx_pfc_paused(),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_ifg('{4{8'd12}}),
|
||||
.cfg_tx_enable('1),
|
||||
.cfg_rx_enable('1),
|
||||
.cfg_tx_prbs31_enable('0),
|
||||
.cfg_rx_prbs31_enable('0),
|
||||
.cfg_mcf_rx_eth_dst_mcast('{4{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_mcf_rx_check_eth_dst_mcast('1),
|
||||
.cfg_mcf_rx_eth_dst_ucast('{4{48'd0}}),
|
||||
.cfg_mcf_rx_check_eth_dst_ucast('0),
|
||||
.cfg_mcf_rx_eth_src('{4{48'd0}}),
|
||||
.cfg_mcf_rx_check_eth_src('0),
|
||||
.cfg_mcf_rx_eth_type('{4{16'h8808}}),
|
||||
.cfg_mcf_rx_opcode_lfc('{4{16'h0001}}),
|
||||
.cfg_mcf_rx_check_opcode_lfc('1),
|
||||
.cfg_mcf_rx_opcode_pfc('{4{16'h0101}}),
|
||||
.cfg_mcf_rx_check_opcode_pfc('1),
|
||||
.cfg_mcf_rx_forward('0),
|
||||
.cfg_mcf_rx_enable('0),
|
||||
.cfg_tx_lfc_eth_dst('{4{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_tx_lfc_eth_src('{4{48'h80_23_31_43_54_4C}}),
|
||||
.cfg_tx_lfc_eth_type('{4{16'h8808}}),
|
||||
.cfg_tx_lfc_opcode('{4{16'h0001}}),
|
||||
.cfg_tx_lfc_en('0),
|
||||
.cfg_tx_lfc_quanta('{4{16'hffff}}),
|
||||
.cfg_tx_lfc_refresh('{4{16'h7fff}}),
|
||||
.cfg_tx_pfc_eth_dst('{4{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_tx_pfc_eth_src('{4{48'h80_23_31_43_54_4C}}),
|
||||
.cfg_tx_pfc_eth_type('{4{16'h8808}}),
|
||||
.cfg_tx_pfc_opcode('{4{16'h0101}}),
|
||||
.cfg_tx_pfc_en('0),
|
||||
.cfg_tx_pfc_quanta('{4{'{8{16'hffff}}}}),
|
||||
.cfg_tx_pfc_refresh('{4{'{8{16'h7fff}}}}),
|
||||
.cfg_rx_lfc_opcode('{4{16'h0001}}),
|
||||
.cfg_rx_lfc_en('0),
|
||||
.cfg_rx_pfc_opcode('{4{16'h0101}}),
|
||||
.cfg_rx_pfc_en('0)
|
||||
);
|
||||
|
||||
taxi_eth_mac_25g_us #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
|
||||
.CNT(4),
|
||||
|
||||
// GT type
|
||||
.GT_TYPE("GTY"),
|
||||
|
||||
// PHY parameters
|
||||
.PADDING_EN(1'b1),
|
||||
.DIC_EN(1'b1),
|
||||
.MIN_FRAME_LEN(64),
|
||||
.PTP_TS_EN(1'b0),
|
||||
.PTP_TS_FMT_TOD(1'b1),
|
||||
.PTP_TS_W(96),
|
||||
.PRBS31_EN(1'b0),
|
||||
.TX_SERDES_PIPELINE(1),
|
||||
.RX_SERDES_PIPELINE(1),
|
||||
.COUNT_125US(125000/6.4)
|
||||
)
|
||||
qsfp_1_mac_inst (
|
||||
.xcvr_ctrl_clk(clk_125mhz),
|
||||
.xcvr_ctrl_rst(qsfp_rst),
|
||||
|
||||
/*
|
||||
* Common
|
||||
*/
|
||||
.xcvr_gtpowergood_out(qsfp_gtpowergood[1]),
|
||||
.xcvr_gtrefclk00_in(qsfp_0_mgt_refclk),
|
||||
.xcvr_qpll0lock_out(),
|
||||
.xcvr_qpll0clk_out(),
|
||||
.xcvr_qpll0refclk_out(),
|
||||
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp(qsfp_1_tx_p),
|
||||
.xcvr_txn(qsfp_1_tx_n),
|
||||
.xcvr_rxp(qsfp_1_rx_p),
|
||||
.xcvr_rxn(qsfp_1_rx_n),
|
||||
|
||||
/*
|
||||
* MAC clocks
|
||||
*/
|
||||
.rx_clk(qsfp_rx_clk[7:4]),
|
||||
.rx_rst_in('0),
|
||||
.rx_rst_out(qsfp_rx_rst[7:4]),
|
||||
.tx_clk(qsfp_tx_clk[7:4]),
|
||||
.tx_rst_in('0),
|
||||
.tx_rst_out(qsfp_tx_rst[7:4]),
|
||||
.ptp_sample_clk('0),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(axis_qsfp_tx[7:4]),
|
||||
.m_axis_tx_cpl(axis_qsfp_tx_cpl[7:4]),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(axis_qsfp_rx[7:4]),
|
||||
|
||||
/*
|
||||
* PTP clock
|
||||
*/
|
||||
.tx_ptp_ts('0),
|
||||
.tx_ptp_ts_step('0),
|
||||
.rx_ptp_ts('0),
|
||||
.rx_ptp_ts_step('0),
|
||||
|
||||
|
||||
/*
|
||||
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
|
||||
*/
|
||||
.tx_lfc_req('0),
|
||||
.tx_lfc_resend('0),
|
||||
.rx_lfc_en('0),
|
||||
.rx_lfc_req(),
|
||||
.rx_lfc_ack('0),
|
||||
|
||||
/*
|
||||
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
|
||||
*/
|
||||
.tx_pfc_req('0),
|
||||
.tx_pfc_resend('0),
|
||||
.rx_pfc_en('0),
|
||||
.rx_pfc_req(),
|
||||
.rx_pfc_ack('0),
|
||||
|
||||
/*
|
||||
* Pause interface
|
||||
*/
|
||||
.tx_lfc_pause_en('0),
|
||||
.tx_pause_req('0),
|
||||
.tx_pause_ack(),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_start_packet(),
|
||||
.tx_error_underflow(),
|
||||
.rx_start_packet(),
|
||||
.rx_error_count(),
|
||||
.rx_error_bad_frame(),
|
||||
.rx_error_bad_fcs(),
|
||||
.rx_bad_block(),
|
||||
.rx_sequence_error(),
|
||||
.rx_block_lock(),
|
||||
.rx_high_ber(),
|
||||
.rx_status(qsfp_rx_status[7:4]),
|
||||
.stat_tx_mcf(),
|
||||
.stat_rx_mcf(),
|
||||
.stat_tx_lfc_pkt(),
|
||||
.stat_tx_lfc_xon(),
|
||||
.stat_tx_lfc_xoff(),
|
||||
.stat_tx_lfc_paused(),
|
||||
.stat_tx_pfc_pkt(),
|
||||
.stat_tx_pfc_xon(),
|
||||
.stat_tx_pfc_xoff(),
|
||||
.stat_tx_pfc_paused(),
|
||||
.stat_rx_lfc_pkt(),
|
||||
.stat_rx_lfc_xon(),
|
||||
.stat_rx_lfc_xoff(),
|
||||
.stat_rx_lfc_paused(),
|
||||
.stat_rx_pfc_pkt(),
|
||||
.stat_rx_pfc_xon(),
|
||||
.stat_rx_pfc_xoff(),
|
||||
.stat_rx_pfc_paused(),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_ifg('{4{8'd12}}),
|
||||
.cfg_tx_enable('1),
|
||||
.cfg_rx_enable('1),
|
||||
.cfg_tx_prbs31_enable('0),
|
||||
.cfg_rx_prbs31_enable('0),
|
||||
.cfg_mcf_rx_eth_dst_mcast('{4{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_mcf_rx_check_eth_dst_mcast('1),
|
||||
.cfg_mcf_rx_eth_dst_ucast('{4{48'd0}}),
|
||||
.cfg_mcf_rx_check_eth_dst_ucast('0),
|
||||
.cfg_mcf_rx_eth_src('{4{48'd0}}),
|
||||
.cfg_mcf_rx_check_eth_src('0),
|
||||
.cfg_mcf_rx_eth_type('{4{16'h8808}}),
|
||||
.cfg_mcf_rx_opcode_lfc('{4{16'h0001}}),
|
||||
.cfg_mcf_rx_check_opcode_lfc('1),
|
||||
.cfg_mcf_rx_opcode_pfc('{4{16'h0101}}),
|
||||
.cfg_mcf_rx_check_opcode_pfc('1),
|
||||
.cfg_mcf_rx_forward('0),
|
||||
.cfg_mcf_rx_enable('0),
|
||||
.cfg_tx_lfc_eth_dst('{4{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_tx_lfc_eth_src('{4{48'h80_23_31_43_54_4C}}),
|
||||
.cfg_tx_lfc_eth_type('{4{16'h8808}}),
|
||||
.cfg_tx_lfc_opcode('{4{16'h0001}}),
|
||||
.cfg_tx_lfc_en('0),
|
||||
.cfg_tx_lfc_quanta('{4{16'hffff}}),
|
||||
.cfg_tx_lfc_refresh('{4{16'h7fff}}),
|
||||
.cfg_tx_pfc_eth_dst('{4{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_tx_pfc_eth_src('{4{48'h80_23_31_43_54_4C}}),
|
||||
.cfg_tx_pfc_eth_type('{4{16'h8808}}),
|
||||
.cfg_tx_pfc_opcode('{4{16'h0101}}),
|
||||
.cfg_tx_pfc_en('0),
|
||||
.cfg_tx_pfc_quanta('{4{'{8{16'hffff}}}}),
|
||||
.cfg_tx_pfc_refresh('{4{'{8{16'h7fff}}}}),
|
||||
.cfg_rx_lfc_opcode('{4{16'h0001}}),
|
||||
.cfg_rx_lfc_en('0),
|
||||
.cfg_rx_pfc_opcode('{4{16'h0101}}),
|
||||
.cfg_rx_pfc_en('0)
|
||||
);
|
||||
|
||||
for (genvar n = 0; n < 8; n = n + 1) begin : qsfp_ch
|
||||
|
||||
taxi_axis_async_fifo #(
|
||||
.DEPTH(16384),
|
||||
.RAM_PIPELINE(2),
|
||||
.FRAME_FIFO(1),
|
||||
.USER_BAD_FRAME_VALUE(1'b1),
|
||||
.USER_BAD_FRAME_MASK(1'b1),
|
||||
.DROP_OVERSIZE_FRAME(1),
|
||||
.DROP_BAD_FRAME(1),
|
||||
.DROP_WHEN_FULL(1)
|
||||
)
|
||||
ch_fifo (
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_clk(qsfp_rx_clk[n]),
|
||||
.s_rst(qsfp_rx_rst[n]),
|
||||
.s_axis(axis_qsfp_rx[n]),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_clk(qsfp_tx_clk[n]),
|
||||
.m_rst(qsfp_tx_rst[n]),
|
||||
.m_axis(axis_qsfp_tx[n]),
|
||||
|
||||
/*
|
||||
* Pause
|
||||
*/
|
||||
.s_pause_req(1'b0),
|
||||
.s_pause_ack(),
|
||||
.m_pause_req(1'b0),
|
||||
.m_pause_ack(),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.s_status_depth(),
|
||||
.s_status_depth_commit(),
|
||||
.s_status_overflow(),
|
||||
.s_status_bad_frame(),
|
||||
.s_status_good_frame(),
|
||||
.m_status_depth(),
|
||||
.m_status_depth_commit(),
|
||||
.m_status_overflow(),
|
||||
.m_status_bad_frame(),
|
||||
.m_status_good_frame()
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user