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zircon: Use AXI stream tie module

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-04-07 15:37:02 -07:00
parent 1fe508a6bf
commit 9a6320c3f7
4 changed files with 12 additions and 31 deletions
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26
src/zircon/rtl/zircon_ip_len_cksum.sv
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@@ -84,27 +84,11 @@ logic [ID_W-1:0] m_axis_meta_id_reg = '0;
logic [DEST_W-1:0] m_axis_meta_dest_reg = '0;
logic [USER_W-1:0] m_axis_meta_user_reg = '0;
assign m_axis_pkt.tdata = s_axis_pkt.tdata;
assign m_axis_pkt.tkeep = s_axis_pkt.tkeep;
assign m_axis_pkt.tstrb = s_axis_pkt.tstrb;
if (ID_EN) begin
assign m_axis_pkt.tid = s_axis_pkt.tid;
end else begin
assign m_axis_pkt.tid = '0;
end
if (DEST_EN) begin
assign m_axis_pkt.tdest = s_axis_pkt.tdest;
end else begin
assign m_axis_pkt.tdest = '0;
end
if (USER_EN) begin
assign m_axis_pkt.tuser = s_axis_pkt.tuser;
end else begin
assign m_axis_pkt.tuser = '0;
end
assign m_axis_pkt.tlast = s_axis_pkt.tlast;
assign m_axis_pkt.tvalid = s_axis_pkt.tvalid;
assign s_axis_pkt.tready = m_axis_pkt.tready;
taxi_axis_tie
axis_tie_pkt_inst (
.s_axis(s_axis_pkt),
.m_axis(m_axis_pkt)
);
assign m_axis_meta.tdata = {m_axis_meta_csum_reg, m_axis_meta_len_reg};
assign m_axis_meta.tkeep = '1;

15
src/zircon/rtl/zircon_ip_tx_egress.sv
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@@ -85,16 +85,11 @@ hdr_adapter_inst (
.m_axis(pkt_parts[0])
);
assign pkt_parts[1].tdata = s_axis_pkt.tdata;
assign pkt_parts[1].tkeep = s_axis_pkt.tkeep;
assign pkt_parts[1].tstrb = s_axis_pkt.tstrb;
assign pkt_parts[1].tvalid = s_axis_pkt.tvalid;
assign pkt_parts[1].tlast = s_axis_pkt.tlast;
assign pkt_parts[1].tid = s_axis_pkt.tid;
assign pkt_parts[1].tdest = s_axis_pkt.tdest;
assign pkt_parts[1].tuser = s_axis_pkt.tuser;
assign s_axis_pkt.tready = pkt_parts[1].tready;
taxi_axis_tie
axis_tie_pkt_inst (
.s_axis(s_axis_pkt),
.m_axis(pkt_parts[1])
);
// combine header and payload
taxi_axis_concat #(

1
src/zircon/tb/zircon_ip_len_cksum/Makefile
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@@ -24,6 +24,7 @@ MODULE = $(COCOTB_TEST_MODULES)
TOPLEVEL = $(COCOTB_TOPLEVEL)
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_tie.sv
VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv
# handle file list files

1
src/zircon/tb/zircon_ip_len_cksum/test_zircon_ip_len_cksum.py
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@@ -259,6 +259,7 @@ def test_zircon_ip_len_cksum(request, data_w=32):
verilog_sources = [
os.path.join(tests_dir, f"{toplevel}.sv"),
os.path.join(rtl_dir, f"{dut}.sv"),
os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_tie.sv"),
os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"),
]