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cndm: Parameter cleanup

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-03-08 17:39:28 -07:00
parent 2bb2710bbd
commit 9af793edc6
11 changed files with 91 additions and 28 deletions
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8
src/cndm/tb/cndm_lite_pcie_us/Makefile
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@@ -38,12 +38,18 @@ export PARAM_FAMILY := "\"virtexuplus\""
# Structural configuration
export PARAM_PORTS := 2
export PARAM_SYS_CLK_PER_NS_NUM := 4
export PARAM_SYS_CLK_PER_NS_DEN := 1
# Queue configuration
export PARAM_WQN_W := 5
export PARAM_CQN_W := $(PARAM_WQN_W)
# PTP configuration
export PARAM_PTP_TS_EN := 1
export PARAM_PTP_TS_FMT_TOD := 0
export PARAM_PTP_CLK_PER_NS_NUM := 512
export PARAM_PTP_CLK_PER_NS_DENOM := 165
export PARAM_PTP_CLK_PER_NS_DEN := 165
# PCIe interface configuration
export PARAM_AXIS_PCIE_DATA_W := 512

8
src/cndm/tb/cndm_lite_pcie_us/test_cndm_lite_pcie_us.py
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@@ -482,12 +482,18 @@ def test_cndm_lite_pcie_us(request, pcie_data_w, mac_data_w):
# Structural configuration
parameters['PORTS'] = 2
parameters['SYS_CLK_PER_NS_NUM'] = 4
parameters['SYS_CLK_PER_NS_DEN'] = 1
# Queue configuration
parameters['WQN_W'] = 5
parameters['CQN_W'] = parameters['WQN_W']
# PTP configuration
parameters['PTP_TS_EN'] = 1
parameters['PTP_TS_FMT_TOD'] = 0
parameters['PTP_CLK_PER_NS_NUM'] = 512
parameters['PTP_CLK_PER_NS_DENOM'] = 165
parameters['PTP_CLK_PER_NS_DEN'] = 165
# PCIe interface configuration
parameters['AXIS_PCIE_DATA_W'] = pcie_data_w

16
src/cndm/tb/cndm_lite_pcie_us/test_cndm_lite_pcie_us.sv
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@@ -34,12 +34,18 @@ module test_cndm_lite_pcie_us #
// Structural configuration
parameter PORTS = 2,
parameter SYS_CLK_PER_NS_NUM = 4,
parameter SYS_CLK_PER_NS_DEN = 1,
// Queue configuration
parameter WQN_W = 5,
parameter CQN_W = WQN_W,
// PTP configuration
parameter logic PTP_TS_EN = 1'b1,
parameter logic PTP_TS_FMT_TOD = 1'b0,
parameter PTP_CLK_PER_NS_NUM = 512,
parameter PTP_CLK_PER_NS_DENOM = 165,
parameter PTP_CLK_PER_NS_DEN = 165,
// PCIe interface configuration
parameter AXIS_PCIE_DATA_W = 512,
@@ -206,12 +212,18 @@ cndm_lite_pcie_us #(
// Structural configuration
.PORTS(PORTS),
.SYS_CLK_PER_NS_NUM(SYS_CLK_PER_NS_NUM),
.SYS_CLK_PER_NS_DEN(SYS_CLK_PER_NS_DEN),
// Queue configuration
.WQN_W(WQN_W),
.CQN_W(CQN_W),
// PTP configuration
.PTP_TS_EN(PTP_TS_EN),
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
.PTP_CLK_PER_NS_NUM(PTP_CLK_PER_NS_NUM),
.PTP_CLK_PER_NS_DENOM(PTP_CLK_PER_NS_DENOM),
.PTP_CLK_PER_NS_DEN(PTP_CLK_PER_NS_DEN),
// PCIe interface configuration
.RQ_SEQ_NUM_W(RQ_SEQ_NUM_W),

8
src/cndm/tb/cndm_micro_pcie_us/Makefile
View File

@@ -38,12 +38,18 @@ export PARAM_FAMILY := "\"virtexuplus\""
# Structural configuration
export PARAM_PORTS := 2
export PARAM_SYS_CLK_PER_NS_NUM := 4
export PARAM_SYS_CLK_PER_NS_DEN := 1
# Queue configuration
export PARAM_WQN_W := 5
export PARAM_CQN_W := $(PARAM_WQN_W)
# PTP configuration
export PARAM_PTP_TS_EN := 1
export PARAM_PTP_TS_FMT_TOD := 0
export PARAM_PTP_CLK_PER_NS_NUM := 512
export PARAM_PTP_CLK_PER_NS_DENOM := 165
export PARAM_PTP_CLK_PER_NS_DEN := 165
# PCIe interface configuration
export PARAM_AXIS_PCIE_DATA_W := 256

8
src/cndm/tb/cndm_micro_pcie_us/test_cndm_micro_pcie_us.py
View File

@@ -481,12 +481,18 @@ def test_cndm_micro_pcie_us(request, pcie_data_w, mac_data_w):
# Structural configuration
parameters['PORTS'] = 2
parameters['SYS_CLK_PER_NS_NUM'] = 4
parameters['SYS_CLK_PER_NS_DEN'] = 1
# Queue configuration
parameters['WQN_W'] = 5
parameters['CQN_W'] = parameters['WQN_W']
# PTP configuration
parameters['PTP_TS_EN'] = 1
parameters['PTP_TS_FMT_TOD'] = 0
parameters['PTP_CLK_PER_NS_NUM'] = 512
parameters['PTP_CLK_PER_NS_DENOM'] = 165
parameters['PTP_CLK_PER_NS_DEN'] = 165
# PCIe interface configuration
parameters['AXIS_PCIE_DATA_W'] = pcie_data_w

16
src/cndm/tb/cndm_micro_pcie_us/test_cndm_micro_pcie_us.sv
View File

@@ -34,12 +34,18 @@ module test_cndm_micro_pcie_us #
// Structural configuration
parameter PORTS = 2,
parameter SYS_CLK_PER_NS_NUM = 4,
parameter SYS_CLK_PER_NS_DEN = 1,
// Queue configuration
parameter WQN_W = 5,
parameter CQN_W = WQN_W,
// PTP configuration
parameter logic PTP_TS_EN = 1'b1,
parameter logic PTP_TS_FMT_TOD = 1'b0,
parameter PTP_CLK_PER_NS_NUM = 512,
parameter PTP_CLK_PER_NS_DENOM = 165,
parameter PTP_CLK_PER_NS_DEN = 165,
// PCIe interface configuration
parameter AXIS_PCIE_DATA_W = 256,
@@ -206,12 +212,18 @@ cndm_micro_pcie_us #(
// Structural configuration
.PORTS(PORTS),
.SYS_CLK_PER_NS_NUM(SYS_CLK_PER_NS_NUM),
.SYS_CLK_PER_NS_DEN(SYS_CLK_PER_NS_DEN),
// Queue configuration
.WQN_W(WQN_W),
.CQN_W(CQN_W),
// PTP configuration
.PTP_TS_EN(PTP_TS_EN),
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
.PTP_CLK_PER_NS_NUM(PTP_CLK_PER_NS_NUM),
.PTP_CLK_PER_NS_DENOM(PTP_CLK_PER_NS_DENOM),
.PTP_CLK_PER_NS_DEN(PTP_CLK_PER_NS_DEN),
// PCIe interface configuration
.RQ_SEQ_NUM_W(RQ_SEQ_NUM_W),