sync: Add reset synchronizer module

Signed-off-by: Alex Forencich <alex@alexforencich.com>

rtl/sync/taxi_sync_reset.sv

@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2014-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * Synchronizes an active-high asynchronous reset signal to a given clock by
+ * using a pipeline of N registers.
+ */
+module taxi_sync_reset #
+(
+    // depth of synchronizer
+    parameter N = 2
+)
+(
+    input  wire logic  clk,
+    input  wire logic  rst,
+
+    output wire logic  out
+);
+
+(* srl_style = "register" *)
+logic [N-1:0] sync_reg = '1;
+
+assign out = sync_reg[N-1];
+
+always_ff @(posedge clk or posedge rst) begin
+    if (rst) begin
+        sync_reg <= '1;
+    end else begin
+        sync_reg <= {sync_reg[N-2:0], 1'b0};
+    end
+end
+
+endmodule
+
+`resetall

syn/vivado/taxi_sync_reset.tcl

@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2020-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# reset synchronizer timing constraints
+
+foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == taxi_sync_reset || REF_NAME == taxi_sync_reset)}] {
+    puts "Inserting timing constraints for taxi_sync_reset instance $inst"
+
+    # reset synchronization
+    set reset_ffs [get_cells -quiet -hier -regexp ".*/sync_reg_reg\\\[\\d+\\\]" -filter "PARENT == $inst"]
+
+    set_property ASYNC_REG TRUE $reset_ffs
+    set_false_path -to [get_pins -of_objects $reset_ffs -filter {IS_PRESET || IS_RESET}]
+}