eth: Clean up multiple quad handling in Ethernet example designs

Signed-off-by: Alex Forencich <alex@alexforencich.com>

src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv

@@ -146,7 +146,7 @@ assign qsfp_rx_n[4*0 +: 4] = qsfp_0_rx_n;
 assign qsfp_rx_p[4*1 +: 4] = qsfp_1_rx_p;
 assign qsfp_rx_n[4*1 +: 4] = qsfp_1_rx_n;
 
-for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
+for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
 
     localparam CNT = 4;
 

src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py

@@ -9,6 +9,7 @@ Authors:
 
 """
 
+import itertools
 import logging
 import os
 import sys
@@ -46,8 +47,7 @@ class TB:
         self.qsfp_sources = []
         self.qsfp_sinks = []
 
-        for inst in dut.gty_quad:
+        for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.gt_quad]):
-            for ch in inst.mac_inst.ch:
             gt_inst = ch.ch_inst.gt.gt_inst
 
             if ch.ch_inst.DATA_W.value == 64:

src/eth/example/Alveo/fpga/rtl/fpga_core.sv

@@ -249,7 +249,7 @@ wire eth_gty_mgt_refclk_bufg[GTY_CLK_CNT];
 
 wire eth_gty_rst[GTY_CLK_CNT];
 
-for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gty_clk
+for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gt_clk
 
     wire eth_gty_mgt_refclk_int;
 
@@ -297,7 +297,7 @@ end
 localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP1[4] = '{"QSFP1.1", "QSFP1.2", "QSFP1.3",  "QSFP1.4"};
 localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP2[4] = '{"QSFP2.1", "QSFP2.2", "QSFP2.3",  "QSFP2.4"};
 
-for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
+for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad
 
     localparam CLK = n;
     localparam CNT = 4;

src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py

@@ -9,6 +9,7 @@ Authors:
 
 """
 
+import itertools
 import logging
 import os
 import sys
@@ -51,8 +52,7 @@ class TB:
         for clk in dut.eth_gty_mgt_refclk_p:
             cocotb.start_soon(Clock(clk, 6.4, units="ns").start())
 
-        for inst in dut.gty_quad:
+        for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.gt_quad]):
-            for ch in inst.mac_inst.ch:
             gt_inst = ch.ch_inst.gt.gt_inst
 
             if ch.ch_inst.DATA_W.value == 64:

src/eth/example/HTG9200/fpga/rtl/fpga_core.sv

@@ -317,7 +317,7 @@ wire eth_gty_mgt_refclk_bufg[GTY_CLK_CNT];
 
 wire eth_gty_rst[GTY_CLK_CNT];
 
-for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gty_clk
+for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gt_clk
 
     wire eth_gty_mgt_refclk_int;
 
@@ -378,7 +378,7 @@ localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP13[4] = '{"QSFP13.1", "QSFP13.2",
 localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP14[4] = '{"QSFP14.1", "QSFP14.2", "QSFP14.3",  "QSFP14.4"};
 localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP15[4] = '{"QSFP15.1", "QSFP15.2", "QSFP15.3",  "QSFP15.4"};
 
-for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
+for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad
 
     localparam CLK = n;
     localparam CNT = 4;

src/eth/example/HTG9200/fpga/tb/fpga_core/test_fpga_core.py

@@ -9,6 +9,7 @@ Authors:
 
 """
 
+import itertools
 import logging
 import os
 import sys
@@ -52,8 +53,7 @@ class TB:
         for clk in dut.eth_gty_mgt_refclk_p:
             cocotb.start_soon(Clock(clk, 6.206, units="ns").start())
 
-        for inst in dut.gty_quad:
+        for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.gt_quad]):
-            for ch in inst.mac_inst.ch:
             gt_inst = ch.ch_inst.gt.gt_inst
 
             if ch.ch_inst.DATA_W.value == 64:

src/eth/example/Nexus_K3P_Q/fpga/rtl/fpga_core.sv

@@ -161,7 +161,7 @@ assign qsfp_rx_n[4*0 +: 4] = qsfp_0_rx_n;
 assign qsfp_rx_p[4*1 +: 4] = qsfp_1_rx_p;
 assign qsfp_rx_n[4*1 +: 4] = qsfp_1_rx_n;
 
-for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
+for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
 
     localparam CNT = 4;
 

src/eth/example/Nexus_K3P_Q/fpga/tb/fpga_core/test_fpga_core.py

@@ -9,6 +9,7 @@ Authors:
 
 """
 
+import itertools
 import logging
 import os
 import sys
@@ -46,8 +47,7 @@ class TB:
         self.qsfp_sources = []
         self.qsfp_sinks = []
 
-        for inst in dut.gty_quad:
+        for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.gt_quad]):
-            for ch in inst.mac_inst.ch:
             gt_inst = ch.ch_inst.gt.gt_inst
 
             if ch.ch_inst.DATA_W.value == 64:

src/eth/example/VCU118/fpga/rtl/fpga_core.sv

@@ -550,7 +550,7 @@ assign qsfp_rx_n[4*1 +: 4] = qsfp2_rx_n;
 localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP1[4] = '{"QSFP1.1", "QSFP1.2", "QSFP1.3",  "QSFP1.4"};
 localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP2[4] = '{"QSFP2.1", "QSFP2.2", "QSFP2.3",  "QSFP2.4"};
 
-for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
+for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
 
     localparam CNT = 4;
 

src/eth/example/VCU118/fpga/tb/fpga_core/test_fpga_core.py

@@ -9,6 +9,7 @@ Authors:
 
 """
 
+import itertools
 import logging
 import os
 import sys
@@ -57,8 +58,7 @@ class TB:
         self.qsfp_sources = []
         self.qsfp_sinks = []
 
-        for inst in dut.gty_quad:
+        for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.gt_quad]):
-            for ch in inst.mac_inst.ch:
             gt_inst = ch.ch_inst.gt.gt_inst
 
             if ch.ch_inst.DATA_W.value == 64:

src/eth/example/XUPP3R/fpga/rtl/fpga_core.sv

@@ -215,7 +215,7 @@ wire eth_gty_mgt_refclk_bufg[GTY_CLK_CNT];
 
 wire eth_gty_rst[GTY_CLK_CNT];
 
-for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gty_clk
+for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gt_clk
 
     wire eth_gty_mgt_refclk_int;
 
@@ -277,7 +277,7 @@ localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP1[4] = '{"QSFP1.1", "QSFP1.2", "Q
 localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP2[4] = '{"QSFP2.1", "QSFP2.2", "QSFP2.3",  "QSFP2.4"};
 localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP3[4] = '{"QSFP3.1", "QSFP3.2", "QSFP3.3",  "QSFP3.4"};
 
-for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
+for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad
 
     localparam CNT = 4;
 

src/eth/example/XUPP3R/fpga/tb/fpga_core/test_fpga_core.py

@@ -9,6 +9,7 @@ Authors:
 
 """
 
+import itertools
 import logging
 import os
 import sys
@@ -52,8 +53,7 @@ class TB:
         for clk in dut.eth_gty_mgt_refclk_p:
             cocotb.start_soon(Clock(clk, 3.102, units="ns").start())
 
-        for inst in dut.gty_quad:
+        for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.gt_quad]):
-            for ch in inst.mac_inst.ch:
             gt_inst = ch.ch_inst.gt.gt_inst
 
             if ch.ch_inst.DATA_W.value == 64:

src/eth/example/fb2CG/fpga/rtl/fpga_core.sv

@@ -135,7 +135,7 @@ wire qsfp_mgt_refclk_bufg[2];
 
 wire qsfp_rst[2];
 
-for (genvar n = 0; n < 2; n = n + 1) begin : gty_clk
+for (genvar n = 0; n < 2; n = n + 1) begin : gt_clk
 
     wire qsfp_mgt_refclk_int;
 
@@ -192,7 +192,7 @@ assign qsfp_rx_n[4*0 +: 4] = qsfp_0_rx_n;
 assign qsfp_rx_p[4*1 +: 4] = qsfp_1_rx_p;
 assign qsfp_rx_n[4*1 +: 4] = qsfp_1_rx_n;
 
-for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
+for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
 
     localparam CLK = n;
     localparam CNT = 4;

src/eth/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py

@@ -9,6 +9,7 @@ Authors:
 
 """
 
+import itertools
 import logging
 import os
 import sys
@@ -47,8 +48,7 @@ class TB:
         self.qsfp_sources = []
         self.qsfp_sinks = []
 
-        for inst in dut.gty_quad:
+        for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.gt_quad]):
-            for ch in inst.mac_inst.ch:
             gt_inst = ch.ch_inst.gt.gt_inst
 
             if ch.ch_inst.DATA_W.value == 64: