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axi: Add STRB parameters to testbenches

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-02-27 10:06:56 -08:00
parent ff2e3c1331
commit aa9900de94
15 changed files with 22 additions and 2 deletions
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tb/axi/taxi_axi_ram/Makefile
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@@ -31,6 +31,7 @@ VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_DATA_W := 32
export PARAM_ADDR_W := 16
export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 )
export PARAM_PIPELINE_OUTPUT := 0
ifeq ($(SIM), icarus)