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axi: Add STRB parameters to testbenches

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-02-27 10:06:56 -08:00
parent ff2e3c1331
commit aa9900de94
15 changed files with 22 additions and 2 deletions
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1
tb/axi/taxi_axi_ram/Makefile
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@@ -31,6 +31,7 @@ VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_DATA_W := 32
export PARAM_ADDR_W := 16
export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 )
export PARAM_PIPELINE_OUTPUT := 0
ifeq ($(SIM), icarus)

1
tb/axi/taxi_axi_ram/test_taxi_axi_ram.py
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@@ -220,6 +220,7 @@ def test_taxi_axi_ram(request, data_w):
parameters['DATA_W'] = data_w
parameters['ADDR_W'] = 16
parameters['STRB_W'] = parameters['DATA_W'] // 8
parameters['ID_W'] = 8
parameters['PIPELINE_OUTPUT'] = 0

2
tb/axi/taxi_axi_ram/test_taxi_axi_ram.sv
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@@ -20,6 +20,7 @@ module test_taxi_axi_ram #
/* verilator lint_off WIDTHTRUNC */
parameter DATA_W = 32,
parameter ADDR_W = 16,
parameter STRB_W = (DATA_W/8),
parameter ID_W = 8,
parameter PIPELINE_OUTPUT = 0
/* verilator lint_on WIDTHTRUNC */
@@ -32,6 +33,7 @@ logic rst;
taxi_axi_if #(
.DATA_W(DATA_W),
.ADDR_W(ADDR_W+16),
.STRB_W(STRB_W),
.ID_W(ID_W)
) s_axi(), m_axi();

1
tb/axi/taxi_axi_register/Makefile
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@@ -31,6 +31,7 @@ REG_TYPE ?= 1
# module parameters
export PARAM_DATA_W := 32
export PARAM_ADDR_W := 32
export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 )
export PARAM_ID_W := 8
export PARAM_AWUSER_EN := 0
export PARAM_AWUSER_W := 1

1
tb/axi/taxi_axi_register/test_taxi_axi_register.py
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@@ -228,6 +228,7 @@ def test_taxi_axi_register(request, data_w, reg_type):
parameters['DATA_W'] = data_w
parameters['ADDR_W'] = 32
parameters['STRB_W'] = parameters['DATA_W'] // 8
parameters['ID_W'] = 8
parameters['AWUSER_EN'] = 0
parameters['AWUSER_W'] = 1

2
tb/axi/taxi_axi_register/test_taxi_axi_register.sv
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@@ -20,6 +20,7 @@ module test_taxi_axi_register #
/* verilator lint_off WIDTHTRUNC */
parameter DATA_W = 32,
parameter ADDR_W = 32,
parameter STRB_W = (DATA_W/8),
parameter ID_W = 8,
parameter logic AWUSER_EN = 1'b0,
parameter AWUSER_W = 1,
@@ -46,6 +47,7 @@ logic rst;
taxi_axi_if #(
.DATA_W(DATA_W),
.ADDR_W(ADDR_W),
.STRB_W(STRB_W),
.ID_W(ID_W),
.AWUSER_EN(AWUSER_EN),
.AWUSER_W(AWUSER_W),

1
tb/axi/taxi_axil_dp_ram/Makefile
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@@ -31,6 +31,7 @@ VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_DATA_W := 32
export PARAM_ADDR_W := 16
export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 )
export PARAM_PIPELINE_OUTPUT := 0
ifeq ($(SIM), icarus)

1
tb/axi/taxi_axil_dp_ram/test_taxi_axil_dp_ram.py
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@@ -254,6 +254,7 @@ def test_taxi_axil_dp_ram(request, data_w):
parameters['DATA_W'] = data_w
parameters['ADDR_W'] = 16
parameters['STRB_W'] = parameters['DATA_W'] // 8
parameters['PIPELINE_OUTPUT'] = 0
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}

4
tb/axi/taxi_axil_dp_ram/test_taxi_axil_dp_ram.sv
View File

@@ -20,6 +20,7 @@ module test_taxi_axil_dp_ram #
/* verilator lint_off WIDTHTRUNC */
parameter DATA_W = 32,
parameter ADDR_W = 16,
parameter STRB_W = (DATA_W/8),
parameter PIPELINE_OUTPUT = 0
/* verilator lint_on WIDTHTRUNC */
)
@@ -32,7 +33,8 @@ logic b_rst;
taxi_axil_if #(
.DATA_W(DATA_W),
.ADDR_W(ADDR_W+16)
.ADDR_W(ADDR_W+16),
.STRB_W(STRB_W)
) s_axil_a(), m_axil_a(), s_axil_b(), m_axil_b();
taxi_axil_dp_ram #(

1
tb/axi/taxi_axil_ram/Makefile
View File

@@ -31,6 +31,7 @@ VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_DATA_W := 32
export PARAM_ADDR_W := 16
export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 )
export PARAM_PIPELINE_OUTPUT := 0
ifeq ($(SIM), icarus)

1
tb/axi/taxi_axil_ram/test_taxi_axil_ram.py
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@@ -202,6 +202,7 @@ def test_taxi_axil_ram(request, data_w):
parameters['DATA_W'] = data_w
parameters['ADDR_W'] = 16
parameters['STRB_W'] = parameters['DATA_W'] // 8
parameters['PIPELINE_OUTPUT'] = 0
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}

4
tb/axi/taxi_axil_ram/test_taxi_axil_ram.sv
View File

@@ -20,6 +20,7 @@ module test_taxi_axil_ram #
/* verilator lint_off WIDTHTRUNC */
parameter DATA_W = 32,
parameter ADDR_W = 16,
parameter STRB_W = (DATA_W/8),
parameter PIPELINE_OUTPUT = 0
/* verilator lint_on WIDTHTRUNC */
)
@@ -30,7 +31,8 @@ logic rst;
taxi_axil_if #(
.DATA_W(DATA_W),
.ADDR_W(ADDR_W+16)
.ADDR_W(ADDR_W+16),
.STRB_W(STRB_W)
) s_axil(), m_axil();
taxi_axil_ram #(

1
tb/axi/taxi_axil_register/Makefile
View File

@@ -32,6 +32,7 @@ REG_TYPE ?= 1
# module parameters
export PARAM_DATA_W := 32
export PARAM_ADDR_W := 32
export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 )
export PARAM_AWUSER_EN := 0
export PARAM_AWUSER_W := 1
export PARAM_WUSER_EN := 0

1
tb/axi/taxi_axil_register/test_taxi_axil_register.py
View File

@@ -210,6 +210,7 @@ def test_taxi_axil_register(request, data_w, reg_type):
parameters['DATA_W'] = data_w
parameters['ADDR_W'] = 32
parameters['STRB_W'] = parameters['DATA_W'] // 8
parameters['AWUSER_EN'] = 0
parameters['AWUSER_W'] = 1
parameters['WUSER_EN'] = 0

2
tb/axi/taxi_axil_register/test_taxi_axil_register.sv
View File

@@ -20,6 +20,7 @@ module test_taxi_axil_register #
/* verilator lint_off WIDTHTRUNC */
parameter DATA_W = 32,
parameter ADDR_W = 32,
parameter STRB_W = (DATA_W/8),
parameter logic AWUSER_EN = 1'b0,
parameter AWUSER_W = 1,
parameter logic WUSER_EN = 1'b0,
@@ -45,6 +46,7 @@ logic rst;
taxi_axil_if #(
.DATA_W(DATA_W),
.ADDR_W(ADDR_W),
.STRB_W(STRB_W),
.AWUSER_EN(AWUSER_EN),
.AWUSER_W(AWUSER_W),
.WUSER_EN(WUSER_EN),