axi: Add STRB parameters to testbenches

Signed-off-by: Alex Forencich <alex@alexforencich.com>

tb/axi/taxi_axil_dp_ram/Makefile

@@ -31,6 +31,7 @@ VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
 # module parameters
 export PARAM_DATA_W := 32
 export PARAM_ADDR_W := 16
+export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 )
 export PARAM_PIPELINE_OUTPUT := 0
 
 ifeq ($(SIM), icarus)

tb/axi/taxi_axil_dp_ram/test_taxi_axil_dp_ram.py

@@ -254,6 +254,7 @@ def test_taxi_axil_dp_ram(request, data_w):
 
     parameters['DATA_W'] = data_w
     parameters['ADDR_W'] = 16
+    parameters['STRB_W'] = parameters['DATA_W'] // 8
     parameters['PIPELINE_OUTPUT'] = 0
 
     extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}

tb/axi/taxi_axil_dp_ram/test_taxi_axil_dp_ram.sv

@@ -20,6 +20,7 @@ module test_taxi_axil_dp_ram #
     /* verilator lint_off WIDTHTRUNC */
     parameter DATA_W = 32,
     parameter ADDR_W = 16,
+    parameter STRB_W = (DATA_W/8),
     parameter PIPELINE_OUTPUT = 0
     /* verilator lint_on WIDTHTRUNC */
 )
@@ -32,7 +33,8 @@ logic b_rst;
 
 taxi_axil_if #(
     .DATA_W(DATA_W),
-    .ADDR_W(ADDR_W+16)
+    .ADDR_W(ADDR_W+16),
+    .STRB_W(STRB_W)
 ) s_axil_a(), m_axil_a(), s_axil_b(), m_axil_b();
 
 taxi_axil_dp_ram #(