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axi: Add STRB parameters to testbenches

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-02-27 10:06:56 -08:00
parent ff2e3c1331
commit aa9900de94
15 changed files with 22 additions and 2 deletions
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4
tb/axi/taxi_axil_ram/test_taxi_axil_ram.sv
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@@ -20,6 +20,7 @@ module test_taxi_axil_ram #
/* verilator lint_off WIDTHTRUNC */
parameter DATA_W = 32,
parameter ADDR_W = 16,
parameter STRB_W = (DATA_W/8),
parameter PIPELINE_OUTPUT = 0
/* verilator lint_on WIDTHTRUNC */
)
@@ -30,7 +31,8 @@ logic rst;
taxi_axil_if #(
.DATA_W(DATA_W),
.ADDR_W(ADDR_W+16)
.ADDR_W(ADDR_W+16),
.STRB_W(STRB_W)
) s_axil(), m_axil();
taxi_axil_ram #(