bslathi19/taxi
1
0
Fork 0
mirror of https://github.com/fpganinja/taxi.git synced 2025-12-07 16:28:40 -08:00
Code Issues Packages Projects Releases Wiki Activity

axi: Add AXI lite dual-port RAM module and testbench

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-02-27 00:58:30 -08:00
parent 55c097f47d
commit ad3042e090
5 changed files with 669 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
README.md
View File

@@ -30,6 +30,7 @@ To facilitate the dual-license model, contributions to the project can only be a
* SV interface for AXI lite
* Register slice
* Single port RAM
* Dual-port RAM
* AXI stream
* SV interface for AXI stream
* Register slice

284
rtl/axi/taxi_axil_dp_ram.sv Normal file
View File

@@ -0,0 +1,284 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2018-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Lite dual-port RAM
*/
module taxi_axil_dp_ram #
(
// Width of address bus in bits
parameter ADDR_W = 16,
// Extra pipeline register on output
parameter logic PIPELINE_OUTPUT = 1'b0
)
(
/*
* Port A
*/
input wire logic a_clk,
input wire logic a_rst,
taxi_axil_if.wr_slv s_axil_wr_a,
taxi_axil_if.rd_slv s_axil_rd_a,
/*
* Port B
*/
input wire logic b_clk,
input wire logic b_rst,
taxi_axil_if.wr_slv s_axil_wr_b,
taxi_axil_if.rd_slv s_axil_rd_b
);
// extract parameters
localparam DATA_W = s_axil_wr_a.DATA_W;
localparam STRB_W = s_axil_wr_a.STRB_W;
localparam VALID_ADDR_W = ADDR_W - $clog2(STRB_W);
localparam BYTE_LANES = STRB_W;
localparam BYTE_W = DATA_W/BYTE_LANES;
// check configuration
if (BYTE_W * STRB_W != DATA_W)
$fatal(0, "Error: AXI data width not evenly divisible (instance %m)");
if (2**$clog2(BYTE_LANES) != BYTE_LANES)
$fatal(0, "Error: AXI word width must be even power of two (instance %m)");
if (s_axil_wr_a.DATA_W != s_axil_rd_a.DATA_W || s_axil_wr_b.DATA_W != s_axil_rd_b.DATA_W || s_axil_wr_a.DATA_W != s_axil_wr_b.DATA_W)
$fatal(0, "Error: AXI interface configuration mismatch (instance %m)");
if (s_axil_wr_a.ADDR_W < ADDR_W || s_axil_wr_a.ADDR_W < ADDR_W || s_axil_rd_b.ADDR_W < ADDR_W || s_axil_rd_b.ADDR_W < ADDR_W)
$fatal(0, "Error: AXI address width is insufficient (instance %m)");
logic read_eligible_a;
logic write_eligible_a;
logic read_eligible_b;
logic write_eligible_b;
logic mem_wr_en_a;
logic mem_rd_en_a;
logic mem_wr_en_b;
logic mem_rd_en_b;
logic last_read_a_reg = 1'b0, last_read_a_next;
logic last_read_b_reg = 1'b0, last_read_b_next;
logic s_axil_a_awready_reg = 1'b0, s_axil_a_awready_next;
logic s_axil_a_wready_reg = 1'b0, s_axil_a_wready_next;
logic s_axil_a_bvalid_reg = 1'b0, s_axil_a_bvalid_next;
logic s_axil_a_arready_reg = 1'b0, s_axil_a_arready_next;
logic [DATA_W-1:0] s_axil_a_rdata_reg = '0, s_axil_a_rdata_next;
logic s_axil_a_rvalid_reg = 1'b0, s_axil_a_rvalid_next;
logic [DATA_W-1:0] s_axil_a_rdata_pipe_reg = '0;
logic s_axil_a_rvalid_pipe_reg = 1'b0;
logic s_axil_b_awready_reg = 1'b0, s_axil_b_awready_next;
logic s_axil_b_wready_reg = 1'b0, s_axil_b_wready_next;
logic s_axil_b_bvalid_reg = 1'b0, s_axil_b_bvalid_next;
logic s_axil_b_arready_reg = 1'b0, s_axil_b_arready_next;
logic [DATA_W-1:0] s_axil_b_rdata_reg = '0, s_axil_b_rdata_next;
logic s_axil_b_rvalid_reg = 1'b0, s_axil_b_rvalid_next;
logic [DATA_W-1:0] s_axil_b_rdata_pipe_reg = '0;
logic s_axil_b_rvalid_pipe_reg = 1'b0;
// (* RAM_STYLE="BLOCK" *)
// verilator lint_off MULTIDRIVEN
logic [DATA_W-1:0] mem[(2**VALID_ADDR_W)-1:0];
// verilator lint_on MULTIDRIVEN
wire [VALID_ADDR_W-1:0] s_axil_a_awaddr_valid = VALID_ADDR_W'(s_axil_wr_a.awaddr >> (ADDR_W - VALID_ADDR_W));
wire [VALID_ADDR_W-1:0] s_axil_a_araddr_valid = VALID_ADDR_W'(s_axil_rd_a.araddr >> (ADDR_W - VALID_ADDR_W));
wire [VALID_ADDR_W-1:0] s_axil_b_awaddr_valid = VALID_ADDR_W'(s_axil_wr_b.awaddr >> (ADDR_W - VALID_ADDR_W));
wire [VALID_ADDR_W-1:0] s_axil_b_araddr_valid = VALID_ADDR_W'(s_axil_rd_b.araddr >> (ADDR_W - VALID_ADDR_W));
assign s_axil_wr_a.awready = s_axil_a_awready_reg;
assign s_axil_wr_a.wready = s_axil_a_wready_reg;
assign s_axil_wr_a.bresp = 2'b00;
assign s_axil_wr_a.bvalid = s_axil_a_bvalid_reg;
assign s_axil_rd_a.arready = s_axil_a_arready_reg;
assign s_axil_rd_a.rdata = PIPELINE_OUTPUT ? s_axil_a_rdata_pipe_reg : s_axil_a_rdata_reg;
assign s_axil_rd_a.rresp = 2'b00;
assign s_axil_rd_a.rvalid = PIPELINE_OUTPUT ? s_axil_a_rvalid_pipe_reg : s_axil_a_rvalid_reg;
assign s_axil_wr_b.awready = s_axil_b_awready_reg;
assign s_axil_wr_b.wready = s_axil_b_wready_reg;
assign s_axil_wr_b.bresp = 2'b00;
assign s_axil_wr_b.bvalid = s_axil_b_bvalid_reg;
assign s_axil_rd_b.arready = s_axil_b_arready_reg;
assign s_axil_rd_b.rdata = PIPELINE_OUTPUT ? s_axil_b_rdata_pipe_reg : s_axil_b_rdata_reg;
assign s_axil_rd_b.rresp = 2'b00;
assign s_axil_rd_b.rvalid = PIPELINE_OUTPUT ? s_axil_b_rvalid_pipe_reg : s_axil_b_rvalid_reg;
initial begin
// two nested loops for smaller number of iterations per loop
// workaround for synthesizer complaints about large loop counts
for (integer i = 0; i < 2**VALID_ADDR_W; i = i + 2**(VALID_ADDR_W/2)) begin
for (integer j = i; j < i + 2**(VALID_ADDR_W/2); j = j + 1) begin
mem[j] = 0;
end
end
end
always_comb begin
mem_wr_en_a = 1'b0;
mem_rd_en_a = 1'b0;
last_read_a_next = last_read_a_reg;
s_axil_a_awready_next = 1'b0;
s_axil_a_wready_next = 1'b0;
s_axil_a_bvalid_next = s_axil_a_bvalid_reg && !s_axil_wr_a.bready;
s_axil_a_arready_next = 1'b0;
s_axil_a_rvalid_next = s_axil_a_rvalid_reg && !(s_axil_rd_a.rready || (PIPELINE_OUTPUT && !s_axil_a_rvalid_pipe_reg));
write_eligible_a = s_axil_wr_a.awvalid && s_axil_wr_a.wvalid && (!s_axil_wr_a.bvalid || s_axil_wr_a.bready) && (!s_axil_wr_a.awready && !s_axil_wr_a.wready);
read_eligible_a = s_axil_rd_a.arvalid && (!s_axil_rd_a.rvalid || s_axil_rd_a.rready || (PIPELINE_OUTPUT && !s_axil_a_rvalid_pipe_reg)) && (!s_axil_rd_a.arready);
if (write_eligible_a && (!read_eligible_a || last_read_a_reg)) begin
last_read_a_next = 1'b0;
s_axil_a_awready_next = 1'b1;
s_axil_a_wready_next = 1'b1;
s_axil_a_bvalid_next = 1'b1;
mem_wr_en_a = 1'b1;
end else if (read_eligible_a) begin
last_read_a_next = 1'b1;
s_axil_a_arready_next = 1'b1;
s_axil_a_rvalid_next = 1'b1;
mem_rd_en_a = 1'b1;
end
end
always_ff @(posedge a_clk) begin
last_read_a_reg <= last_read_a_next;
s_axil_a_awready_reg <= s_axil_a_awready_next;
s_axil_a_wready_reg <= s_axil_a_wready_next;
s_axil_a_bvalid_reg <= s_axil_a_bvalid_next;
s_axil_a_arready_reg <= s_axil_a_arready_next;
s_axil_a_rvalid_reg <= s_axil_a_rvalid_next;
if (mem_rd_en_a) begin
s_axil_a_rdata_reg <= mem[s_axil_a_araddr_valid];
end else begin
for (integer i = 0; i < BYTE_LANES; i = i + 1) begin
if (mem_wr_en_a && s_axil_wr_a.wstrb[i]) begin
mem[s_axil_a_awaddr_valid][BYTE_W*i +: BYTE_W] <= s_axil_wr_a.wdata[BYTE_W*i +: BYTE_W];
end
end
end
if (!s_axil_a_rvalid_pipe_reg || s_axil_rd_a.rready) begin
s_axil_a_rdata_pipe_reg <= s_axil_a_rdata_reg;
s_axil_a_rvalid_pipe_reg <= s_axil_a_rvalid_reg;
end
if (a_rst) begin
last_read_a_reg <= 1'b0;
s_axil_a_awready_reg <= 1'b0;
s_axil_a_wready_reg <= 1'b0;
s_axil_a_bvalid_reg <= 1'b0;
s_axil_a_arready_reg <= 1'b0;
s_axil_a_rvalid_reg <= 1'b0;
s_axil_a_rvalid_pipe_reg <= 1'b0;
end
end
always_comb begin
mem_wr_en_b = 1'b0;
mem_rd_en_b = 1'b0;
last_read_b_next = last_read_b_reg;
s_axil_b_awready_next = 1'b0;
s_axil_b_wready_next = 1'b0;
s_axil_b_bvalid_next = s_axil_b_bvalid_reg && !s_axil_wr_b.bready;
s_axil_b_arready_next = 1'b0;
s_axil_b_rvalid_next = s_axil_b_rvalid_reg && !(s_axil_rd_b.rready || (PIPELINE_OUTPUT && !s_axil_b_rvalid_pipe_reg));
write_eligible_b = s_axil_wr_b.awvalid && s_axil_wr_b.wvalid && (!s_axil_wr_b.bvalid || s_axil_wr_b.bready) && (!s_axil_wr_b.awready && !s_axil_wr_b.wready);
read_eligible_b = s_axil_rd_b.arvalid && (!s_axil_rd_b.rvalid || s_axil_rd_b.rready || (PIPELINE_OUTPUT && !s_axil_b_rvalid_pipe_reg)) && (!s_axil_rd_b.arready);
if (write_eligible_b && (!read_eligible_b || last_read_b_reg)) begin
last_read_b_next = 1'b0;
s_axil_b_awready_next = 1'b1;
s_axil_b_wready_next = 1'b1;
s_axil_b_bvalid_next = 1'b1;
mem_wr_en_b = 1'b1;
end else if (read_eligible_b) begin
last_read_b_next = 1'b1;
s_axil_b_arready_next = 1'b1;
s_axil_b_rvalid_next = 1'b1;
mem_rd_en_b = 1'b1;
end
end
always_ff @(posedge b_clk) begin
last_read_b_reg <= last_read_b_next;
s_axil_b_awready_reg <= s_axil_b_awready_next;
s_axil_b_wready_reg <= s_axil_b_wready_next;
s_axil_b_bvalid_reg <= s_axil_b_bvalid_next;
s_axil_b_arready_reg <= s_axil_b_arready_next;
s_axil_b_rvalid_reg <= s_axil_b_rvalid_next;
if (mem_rd_en_b) begin
s_axil_b_rdata_reg <= mem[s_axil_b_araddr_valid];
end else begin
for (integer i = 0; i < BYTE_LANES; i = i + 1) begin
if (mem_wr_en_b && s_axil_wr_b.wstrb[i]) begin
mem[s_axil_b_awaddr_valid][BYTE_W*i +: BYTE_W] <= s_axil_wr_b.wdata[BYTE_W*i +: BYTE_W];
end
end
end
if (!s_axil_b_rvalid_pipe_reg || s_axil_rd_b.rready) begin
s_axil_b_rdata_pipe_reg <= s_axil_b_rdata_reg;
s_axil_b_rvalid_pipe_reg <= s_axil_b_rvalid_reg;
end
if (b_rst) begin
last_read_b_reg <= 1'b0;
s_axil_b_awready_reg <= 1'b0;
s_axil_b_wready_reg <= 1'b0;
s_axil_b_bvalid_reg <= 1'b0;
s_axil_b_arready_reg <= 1'b0;
s_axil_b_rvalid_reg <= 1'b0;
s_axil_b_rvalid_pipe_reg <= 1'b0;
end
end
endmodule
`resetall

49
tb/axi/taxi_axil_dp_ram/Makefile Normal file
View File

@@ -0,0 +1,49 @@
# SPDX-License-Identifier: CERN-OHL-S-2.0
#
# Copyright (c) 2020-2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
TOPLEVEL_LANG = verilog
SIM ?= verilator
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
DUT = taxi_axil_dp_ram
COCOTB_TEST_MODULES = test_$(DUT)
COCOTB_TOPLEVEL = test_$(DUT)
MODULE = $(COCOTB_TEST_MODULES)
TOPLEVEL = $(COCOTB_TOPLEVEL)
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
VERILOG_SOURCES += ../../../rtl/axi/$(DUT).sv
VERILOG_SOURCES += ../../../rtl/axi/taxi_axil_if.sv
# handle file list files
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_DATA_W := 32
export PARAM_ADDR_W := 16
export PARAM_PIPELINE_OUTPUT := 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
else ifeq ($(SIM), verilator)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst
VERILATOR_TRACE = 1
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim

273
tb/axi/taxi_axil_dp_ram/test_taxi_axil_dp_ram.py Normal file
View File

@@ -0,0 +1,273 @@
#!/usr/bin/env python
# SPDX-License-Identifier: CERN-OHL-S-2.0
"""
Copyright (c) 2020-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
"""
import itertools
import logging
import os
import random
import cocotb_test.simulator
import pytest
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, Timer
from cocotb.regression import TestFactory
from cocotbext.axi import AxiLiteBus, AxiLiteMaster
class TB(object):
def __init__(self, dut):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.a_clk, 8, units="ns").start())
cocotb.start_soon(Clock(dut.b_clk, 10, units="ns").start())
self.axil_master = []
self.axil_master.append(AxiLiteMaster(AxiLiteBus.from_entity(dut.s_axil_a), dut.a_clk, dut.a_rst))
self.axil_master.append(AxiLiteMaster(AxiLiteBus.from_entity(dut.s_axil_b), dut.b_clk, dut.b_rst))
def set_idle_generator(self, generator=None):
if generator:
for axil_master in self.axil_master:
axil_master.write_if.aw_channel.set_pause_generator(generator())
axil_master.write_if.w_channel.set_pause_generator(generator())
axil_master.read_if.ar_channel.set_pause_generator(generator())
def set_backpressure_generator(self, generator=None):
if generator:
for axil_master in self.axil_master:
axil_master.write_if.b_channel.set_pause_generator(generator())
axil_master.read_if.r_channel.set_pause_generator(generator())
async def cycle_reset(self):
self.dut.a_rst.setimmediatevalue(0)
self.dut.b_rst.setimmediatevalue(0)
await RisingEdge(self.dut.a_clk)
await RisingEdge(self.dut.a_clk)
self.dut.a_rst.value = 1
self.dut.b_rst.value = 1
await RisingEdge(self.dut.a_clk)
await RisingEdge(self.dut.a_clk)
self.dut.a_rst.value = 0
await RisingEdge(self.dut.b_clk)
self.dut.b_rst.value = 0
await RisingEdge(self.dut.a_clk)
await RisingEdge(self.dut.a_clk)
async def run_test_write(dut, port=0, data_in=None, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
axil_master = tb.axil_master[port]
byte_lanes = axil_master.write_if.byte_lanes
await tb.cycle_reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in range(1, byte_lanes*2):
for offset in range(byte_lanes):
tb.log.info("length %d, offset %d", length, offset)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
await axil_master.write(addr-4, b'\xaa'*(length+8))
await axil_master.write(addr, test_data)
data = await axil_master.read(addr-1, length+2)
assert data.data == b'\xaa'+test_data+b'\xaa'
await RisingEdge(dut.a_clk)
await RisingEdge(dut.a_clk)
async def run_test_read(dut, port=0, data_in=None, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
axil_master = tb.axil_master[port]
byte_lanes = axil_master.write_if.byte_lanes
await tb.cycle_reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in range(1, byte_lanes*2):
for offset in range(byte_lanes):
tb.log.info("length %d, offset %d", length, offset)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
await axil_master.write(addr, test_data)
data = await axil_master.read(addr, length)
assert data.data == test_data
await RisingEdge(dut.a_clk)
await RisingEdge(dut.a_clk)
async def run_test_arb(dut, data_in=None, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
await tb.cycle_reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
async def worker(master, offset):
wr_op = master.init_write(offset, b'\x11\x22\x33\x44')
rd_op = master.init_read(offset, 4)
await wr_op.wait()
await rd_op.wait()
workers = []
for k in range(10):
workers.append(cocotb.start_soon(worker(tb.axil_master[0], k*256)))
workers.append(cocotb.start_soon(worker(tb.axil_master[1], k*256)))
while workers:
await workers.pop(0).join()
await RisingEdge(dut.a_clk)
await RisingEdge(dut.a_clk)
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
await tb.cycle_reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
async def worker(master, offset, aperture, count=16):
for k in range(count):
length = random.randint(1, min(32, aperture))
addr = offset+random.randint(0, aperture-length)
test_data = bytearray([x % 256 for x in range(length)])
await Timer(random.randint(1, 100), 'ns')
await master.write(addr, test_data)
await Timer(random.randint(1, 100), 'ns')
data = await master.read(addr, length)
assert data.data == test_data
workers = []
for k in range(16):
workers.append(cocotb.start_soon(worker(tb.axil_master[k%len(tb.axil_master)], k*0x1000, 0x1000, count=16)))
while workers:
await workers.pop(0).join()
await RisingEdge(dut.a_clk)
await RisingEdge(dut.a_clk)
def cycle_pause():
return itertools.cycle([1, 1, 1, 0])
if cocotb.SIM_NAME:
for test in [run_test_write, run_test_read]:
factory = TestFactory(test)
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.add_option("port", [0, 1])
factory.generate_tests()
factory = TestFactory(run_test_arb)
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
factory = TestFactory(run_stress_test)
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
# cocotb-test
tests_dir = os.path.abspath(os.path.dirname(__file__))
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
def process_f_files(files):
lst = {}
for f in files:
if f[-2:].lower() == '.f':
with open(f, 'r') as fp:
l = fp.read().split()
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
lst[os.path.basename(f)] = f
else:
lst[os.path.basename(f)] = f
return list(lst.values())
@pytest.mark.parametrize("data_w", [8, 16, 32])
def test_taxi_axil_dp_ram(request, data_w):
dut = "taxi_axil_dp_ram"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = module
verilog_sources = [
os.path.join(tests_dir, f"{toplevel}.sv"),
os.path.join(rtl_dir, "axi", f"{dut}.sv"),
os.path.join(rtl_dir, "axi", "taxi_axil_if.sv"),
]
verilog_sources = process_f_files(verilog_sources)
parameters = {}
parameters['DATA_W'] = data_w
parameters['ADDR_W'] = 16
parameters['PIPELINE_OUTPUT'] = 0
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
simulator="verilator",
python_search=[tests_dir],
verilog_sources=verilog_sources,
toplevel=toplevel,
module=module,
parameters=parameters,
sim_build=sim_build,
extra_env=extra_env,
)

62
tb/axi/taxi_axil_dp_ram/test_taxi_axil_dp_ram.sv Normal file
View File

@@ -0,0 +1,62 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4 lite dual-port RAM testbench
*/
module test_taxi_axil_dp_ram #
(
/* verilator lint_off WIDTHTRUNC */
parameter DATA_W = 32,
parameter ADDR_W = 16,
parameter PIPELINE_OUTPUT = 0
/* verilator lint_on WIDTHTRUNC */
)
();
logic a_clk;
logic a_rst;
logic b_clk;
logic b_rst;
taxi_axil_if #(
.DATA_W(DATA_W),
.ADDR_W(ADDR_W+16)
) s_axil_a(), m_axil_a(), s_axil_b(), m_axil_b();
taxi_axil_dp_ram #(
.ADDR_W(ADDR_W),
.PIPELINE_OUTPUT(PIPELINE_OUTPUT)
)
uut (
/*
* Port A
*/
.a_clk(a_clk),
.a_rst(a_rst),
.s_axil_wr_a(s_axil_a),
.s_axil_rd_a(s_axil_a),
/*
* Port B
*/
.b_clk(b_clk),
.b_rst(b_rst),
.s_axil_wr_b(s_axil_b),
.s_axil_rd_b(s_axil_b)
);
endmodule
`resetall